hw/timer/xilinx_timer.c

   1 /*
   2  * QEMU model of the Xilinx timer block.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "hw/irq.h"
  28 #include "hw/ptimer.h"
  29 #include "hw/qdev-properties.h"
  30 #include "qemu/log.h"
  31 #include "qemu/module.h"
  32
  33 #define D(x)
  34
  35 #define R_TCSR     0
  36 #define R_TLR      1
  37 #define R_TCR      2
  38 #define R_MAX      4
  39
  40 #define TCSR_MDT        (1<<0)
  41 #define TCSR_UDT        (1<<1)
  42 #define TCSR_GENT       (1<<2)
  43 #define TCSR_CAPT       (1<<3)
  44 #define TCSR_ARHT       (1<<4)
  45 #define TCSR_LOAD       (1<<5)
  46 #define TCSR_ENIT       (1<<6)
  47 #define TCSR_ENT        (1<<7)
  48 #define TCSR_TINT       (1<<8)
  49 #define TCSR_PWMA       (1<<9)
  50 #define TCSR_ENALL      (1<<10)
  51
  52 struct xlx_timer
  53 {
  54     ptimer_state *ptimer;
  55     void *parent;
  56     int nr; /* for debug.  */
  57
  58     unsigned long timer_div;
  59
  60     uint32_t regs[R_MAX];
  61 };
  62
  63 #define TYPE_XILINX_TIMER "xlnx.xps-timer"
  64 #define XILINX_TIMER(obj) \
  65     OBJECT_CHECK(struct timerblock, (obj), TYPE_XILINX_TIMER)
  66
  67 struct timerblock
  68 {
  69     SysBusDevice parent_obj;
  70
  71     MemoryRegion mmio;
  72     qemu_irq irq;
  73     uint8_t one_timer_only;
  74     uint32_t freq_hz;
  75     struct xlx_timer *timers;
  76 };
  77
  78 static inline unsigned int num_timers(struct timerblock *t)
  79 {
  80     return 2 - t->one_timer_only;
  81 }
  82
  83 static inline unsigned int timer_from_addr(hwaddr addr)
  84 {
  85     /* Timers get a 4x32bit control reg area each.  */
  86     return addr >> 2;
  87 }
  88
  89 static void timer_update_irq(struct timerblock *t)
  90 {
  91     unsigned int i, irq = 0;
  92     uint32_t csr;
  93
  94     for (i = 0; i < num_timers(t); i++) {
  95         csr = t->timers[i].regs[R_TCSR];
  96         irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
  97     }
  98
  99     /* All timers within the same slave share a single IRQ line.  */
 100     qemu_set_irq(t->irq, !!irq);
 101 }
 102
 103 static uint64_t
 104 timer_read(void *opaque, hwaddr addr, unsigned int size)
 105 {
 106     struct timerblock *t = opaque;
 107     struct xlx_timer *xt;
 108     uint32_t r = 0;
 109     unsigned int timer;
 110
 111     addr >>= 2;
 112     timer = timer_from_addr(addr);
 113     xt = &t->timers[timer];
 114     /* Further decoding to address a specific timers reg.  */
 115     addr &= 0x3;
 116     switch (addr)
 117     {
 118         case R_TCR:
 119                 r = ptimer_get_count(xt->ptimer);
 120                 if (!(xt->regs[R_TCSR] & TCSR_UDT))
 121                     r = ~r;
 122                 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
 123                          timer, r, xt->regs[R_TCSR] & TCSR_UDT));
 124             break;
 125         default:
 126             if (addr < ARRAY_SIZE(xt->regs))
 127                 r = xt->regs[addr];
 128             break;
 129
 130     }
 131     D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
 132     return r;
 133 }
 134
 135 /* Must be called inside ptimer transaction block */
 136 static void timer_enable(struct xlx_timer *xt)
 137 {
 138     uint64_t count;
 139
 140     D(fprintf(stderr, "%s timer=%d down=%d\n", __func__,
 141               xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
 142
 143     ptimer_stop(xt->ptimer);
 144
 145     if (xt->regs[R_TCSR] & TCSR_UDT)
 146         count = xt->regs[R_TLR];
 147     else
 148         count = ~0 - xt->regs[R_TLR];
 149     ptimer_set_limit(xt->ptimer, count, 1);
 150     ptimer_run(xt->ptimer, 1);
 151 }
 152
 153 static void
 154 timer_write(void *opaque, hwaddr addr,
 155             uint64_t val64, unsigned int size)
 156 {
 157     struct timerblock *t = opaque;
 158     struct xlx_timer *xt;
 159     unsigned int timer;
 160     uint32_t value = val64;
 161
 162     addr >>= 2;
 163     timer = timer_from_addr(addr);
 164     xt = &t->timers[timer];
 165     D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n",
 166              __func__, addr * 4, value, timer, addr & 3));
 167     /* Further decoding to address a specific timers reg.  */
 168     addr &= 3;
 169     switch (addr)
 170     {
 171         case R_TCSR:
 172             if (value & TCSR_TINT)
 173                 value &= ~TCSR_TINT;
 174
 175             xt->regs[addr] = value & 0x7ff;
 176             if (value & TCSR_ENT) {
 177                 ptimer_transaction_begin(xt->ptimer);
 178                 timer_enable(xt);
 179                 ptimer_transaction_commit(xt->ptimer);
 180             }
 181             break;
 182
 183         default:
 184             if (addr < ARRAY_SIZE(xt->regs))
 185                 xt->regs[addr] = value;
 186             break;
 187     }
 188     timer_update_irq(t);
 189 }
 190
 191 static const MemoryRegionOps timer_ops = {
 192     .read = timer_read,
 193     .write = timer_write,
 194     .endianness = DEVICE_NATIVE_ENDIAN,
 195     .valid = {
 196         .min_access_size = 4,
 197         .max_access_size = 4
 198     }
 199 };
 200
 201 static void timer_hit(void *opaque)
 202 {
 203     struct xlx_timer *xt = opaque;
 204     struct timerblock *t = xt->parent;
 205     D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
 206     xt->regs[R_TCSR] |= TCSR_TINT;
 207
 208     if (xt->regs[R_TCSR] & TCSR_ARHT)
 209         timer_enable(xt);
 210     timer_update_irq(t);
 211 }
 212
 213 static void xilinx_timer_realize(DeviceState *dev, Error **errp)
 214 {
 215     struct timerblock *t = XILINX_TIMER(dev);
 216     unsigned int i;
 217
 218     /* Init all the ptimers.  */
 219     t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
 220     for (i = 0; i < num_timers(t); i++) {
 221         struct xlx_timer *xt = &t->timers[i];
 222
 223         xt->parent = t;
 224         xt->nr = i;
 225         xt->ptimer = ptimer_init(timer_hit, xt, PTIMER_POLICY_DEFAULT);
 226         ptimer_transaction_begin(xt->ptimer);
 227         ptimer_set_freq(xt->ptimer, t->freq_hz);
 228         ptimer_transaction_commit(xt->ptimer);
 229     }
 230
 231     memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
 232                           R_MAX * 4 * num_timers(t));
 233     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
 234 }
 235
 236 static void xilinx_timer_init(Object *obj)
 237 {
 238     struct timerblock *t = XILINX_TIMER(obj);
 239
 240     /* All timers share a single irq line.  */
 241     sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
 242 }
 243
 244 static Property xilinx_timer_properties[] = {
 245     DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
 246                                                                 62 * 1000000),
 247     DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
 248     DEFINE_PROP_END_OF_LIST(),
 249 };
 250
 251 static void xilinx_timer_class_init(ObjectClass *klass, void *data)
 252 {
 253     DeviceClass *dc = DEVICE_CLASS(klass);
 254
 255     dc->realize = xilinx_timer_realize;
 256     device_class_set_props(dc, xilinx_timer_properties);
 257 }
 258
 259 static const TypeInfo xilinx_timer_info = {
 260     .name          = TYPE_XILINX_TIMER,
 261     .parent        = TYPE_SYS_BUS_DEVICE,
 262     .instance_size = sizeof(struct timerblock),
 263     .instance_init = xilinx_timer_init,
 264     .class_init    = xilinx_timer_class_init,
 265 };
 266
 267 static void xilinx_timer_register_types(void)
 268 {
 269     type_register_static(&xilinx_timer_info);
 270 }
 271
 272 type_init(xilinx_timer_register_types)