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qapi: Improve specificity of type/member descriptions
[qemu/armbru.git] / hw / arm / aspeed_ast10x0.c
blob649b3b13c132e95ac5a65aa4aff1618c083aecdd
1 /*
2 * ASPEED Ast10x0 SoC
3 *
4 * Copyright (C) 2022 ASPEED Technology Inc.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 *
9 * Implementation extracted from the AST2600 and adapted for Ast10x0.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "exec/address-spaces.h"
15 #include "sysemu/sysemu.h"
16 #include "hw/qdev-clock.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19
20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
21
22 static const hwaddr aspeed_soc_ast1030_memmap[] = {
23 [ASPEED_DEV_SRAM] = 0x00000000,
24 [ASPEED_DEV_SECSRAM] = 0x79000000,
25 [ASPEED_DEV_IOMEM] = 0x7E600000,
26 [ASPEED_DEV_PWM] = 0x7E610000,
27 [ASPEED_DEV_FMC] = 0x7E620000,
28 [ASPEED_DEV_SPI1] = 0x7E630000,
29 [ASPEED_DEV_SPI2] = 0x7E640000,
30 [ASPEED_DEV_UDC] = 0x7E6A2000,
31 [ASPEED_DEV_HACE] = 0x7E6D0000,
32 [ASPEED_DEV_SCU] = 0x7E6E2000,
33 [ASPEED_DEV_JTAG0] = 0x7E6E4000,
34 [ASPEED_DEV_JTAG1] = 0x7E6E4100,
35 [ASPEED_DEV_ADC] = 0x7E6E9000,
36 [ASPEED_DEV_ESPI] = 0x7E6EE000,
37 [ASPEED_DEV_SBC] = 0x7E6F2000,
38 [ASPEED_DEV_GPIO] = 0x7E780000,
39 [ASPEED_DEV_SGPIOM] = 0x7E780500,
40 [ASPEED_DEV_TIMER1] = 0x7E782000,
41 [ASPEED_DEV_UART1] = 0x7E783000,
42 [ASPEED_DEV_UART2] = 0x7E78D000,
43 [ASPEED_DEV_UART3] = 0x7E78E000,
44 [ASPEED_DEV_UART4] = 0x7E78F000,
45 [ASPEED_DEV_UART5] = 0x7E784000,
46 [ASPEED_DEV_UART6] = 0x7E790000,
47 [ASPEED_DEV_UART7] = 0x7E790100,
48 [ASPEED_DEV_UART8] = 0x7E790200,
49 [ASPEED_DEV_UART9] = 0x7E790300,
50 [ASPEED_DEV_UART10] = 0x7E790400,
51 [ASPEED_DEV_UART11] = 0x7E790500,
52 [ASPEED_DEV_UART12] = 0x7E790600,
53 [ASPEED_DEV_UART13] = 0x7E790700,
54 [ASPEED_DEV_WDT] = 0x7E785000,
55 [ASPEED_DEV_LPC] = 0x7E789000,
56 [ASPEED_DEV_PECI] = 0x7E78B000,
57 [ASPEED_DEV_I3C] = 0x7E7A0000,
58 [ASPEED_DEV_I2C] = 0x7E7B0000,
59 };
60
61 static const int aspeed_soc_ast1030_irqmap[] = {
62 [ASPEED_DEV_UART1] = 47,
63 [ASPEED_DEV_UART2] = 48,
64 [ASPEED_DEV_UART3] = 49,
65 [ASPEED_DEV_UART4] = 50,
66 [ASPEED_DEV_UART5] = 8,
67 [ASPEED_DEV_UART6] = 57,
68 [ASPEED_DEV_UART7] = 58,
69 [ASPEED_DEV_UART8] = 59,
70 [ASPEED_DEV_UART9] = 60,
71 [ASPEED_DEV_UART10] = 61,
72 [ASPEED_DEV_UART11] = 62,
73 [ASPEED_DEV_UART12] = 63,
74 [ASPEED_DEV_UART13] = 64,
75 [ASPEED_DEV_GPIO] = 11,
76 [ASPEED_DEV_TIMER1] = 16,
77 [ASPEED_DEV_TIMER2] = 17,
78 [ASPEED_DEV_TIMER3] = 18,
79 [ASPEED_DEV_TIMER4] = 19,
80 [ASPEED_DEV_TIMER5] = 20,
81 [ASPEED_DEV_TIMER6] = 21,
82 [ASPEED_DEV_TIMER7] = 22,
83 [ASPEED_DEV_TIMER8] = 23,
84 [ASPEED_DEV_WDT] = 24,
85 [ASPEED_DEV_LPC] = 35,
86 [ASPEED_DEV_PECI] = 38,
87 [ASPEED_DEV_FMC] = 39,
88 [ASPEED_DEV_ESPI] = 42,
89 [ASPEED_DEV_PWM] = 44,
90 [ASPEED_DEV_ADC] = 46,
91 [ASPEED_DEV_SPI1] = 65,
92 [ASPEED_DEV_SPI2] = 66,
93 [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */
94 [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
95 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
96 [ASPEED_DEV_UDC] = 9,
97 [ASPEED_DEV_SGPIOM] = 51,
98 [ASPEED_DEV_JTAG0] = 27,
99 [ASPEED_DEV_JTAG1] = 53,
100 };
101
102 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
103 {
104 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
105
106 return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
107 }
108
109 static void aspeed_soc_ast1030_init(Object *obj)
110 {
111 AspeedSoCState *s = ASPEED_SOC(obj);
112 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
113 char socname[8];
114 char typename[64];
115 int i;
116
117 if (sscanf(sc->name, "%7s", socname) != 1) {
118 g_assert_not_reached();
119 }
120
121 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
122
123 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
124
125 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
126 object_initialize_child(obj, "scu", &s->scu, typename);
127 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
128
129 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
130 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
131
132 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
133 object_initialize_child(obj, "i2c", &s->i2c, typename);
134
135 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
136
137 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
138 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
139
140 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
141 object_initialize_child(obj, "adc", &s->adc, typename);
142
143 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
144 object_initialize_child(obj, "fmc", &s->fmc, typename);
145
146 for (i = 0; i < sc->spis_num; i++) {
147 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
148 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
149 }
150
151 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
152
153 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
154
155 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
156
157 for (i = 0; i < sc->wdts_num; i++) {
158 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
159 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
160 }
161
162 for (i = 0; i < sc->uarts_num; i++) {
163 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
164 }
165
166 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
167 object_initialize_child(obj, "gpio", &s->gpio, typename);
168
169 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
170 object_initialize_child(obj, "hace", &s->hace, typename);
171
172 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
173 object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
174 TYPE_UNIMPLEMENTED_DEVICE);
175 object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
176 object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
177 object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
178 object_initialize_child(obj, "sgpiom", &s->sgpiom,
179 TYPE_UNIMPLEMENTED_DEVICE);
180 object_initialize_child(obj, "jtag[0]", &s->jtag[0],
181 TYPE_UNIMPLEMENTED_DEVICE);
182 object_initialize_child(obj, "jtag[1]", &s->jtag[1],
183 TYPE_UNIMPLEMENTED_DEVICE);
184 }
185
186 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
187 {
188 AspeedSoCState *s = ASPEED_SOC(dev_soc);
189 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
190 DeviceState *armv7m;
191 Error *err = NULL;
192 int i;
193 g_autofree char *sram_name = NULL;
194
195 if (!clock_has_source(s->sysclk)) {
196 error_setg(errp, "sysclk clock must be wired up by the board code");
197 return;
198 }
199
200 /* General I/O memory space to catch all unimplemented device */
201 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
202 sc->memmap[ASPEED_DEV_IOMEM],
203 ASPEED_SOC_IOMEM_SIZE);
204 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sbc_unimplemented),
205 "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC],
206 0x40000);
207
208 /* AST1030 CPU Core */
209 armv7m = DEVICE(&s->armv7m);
210 qdev_prop_set_uint32(armv7m, "num-irq", 256);
211 qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
212 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
213 object_property_set_link(OBJECT(&s->armv7m), "memory",
214 OBJECT(s->memory), &error_abort);
215 sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
216
217 /* Internal SRAM */
218 sram_name = g_strdup_printf("aspeed.sram.%d",
219 CPU(s->armv7m.cpu)->cpu_index);
220 memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
221 if (err != NULL) {
222 error_propagate(errp, err);
223 return;
224 }
225 memory_region_add_subregion(s->memory,
226 sc->memmap[ASPEED_DEV_SRAM],
227 &s->sram);
228 memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
229 sc->secsram_size, &err);
230 if (err != NULL) {
231 error_propagate(errp, err);
232 return;
233 }
234 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
235 &s->secsram);
236
237 /* SCU */
238 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
239 return;
240 }
241 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
242
243 /* I2C */
244
245 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram),
246 &error_abort);
247 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
248 return;
249 }
250 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
251 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
252 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
253 sc->irqmap[ASPEED_DEV_I2C] + i);
254 /* The AST1030 I2C controller has one IRQ per bus. */
255 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
256 }
257
258 /* I3C */
259 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
260 return;
261 }
262 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
263 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
264 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
265 sc->irqmap[ASPEED_DEV_I3C] + i);
266 /* The AST1030 I3C controller has one IRQ per bus. */
267 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
268 }
269
270 /* PECI */
271 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
272 return;
273 }
274 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
275 sc->memmap[ASPEED_DEV_PECI]);
276 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
277 aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
278
279 /* LPC */
280 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
281 return;
282 }
283 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
284
285 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
286 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
287 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
288
289 /*
290 * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
291 */
292 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
293 qdev_get_gpio_in(DEVICE(&s->armv7m),
294 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
295
296 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
297 qdev_get_gpio_in(DEVICE(&s->armv7m),
298 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
299
300 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
301 qdev_get_gpio_in(DEVICE(&s->armv7m),
302 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
303
304 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
305 qdev_get_gpio_in(DEVICE(&s->armv7m),
306 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
307
308 /* UART */
309 if (!aspeed_soc_uart_realize(s, errp)) {
310 return;
311 }
312
313 /* Timer */
314 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
315 &error_abort);
316 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
317 return;
318 }
319 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
320 sc->memmap[ASPEED_DEV_TIMER1]);
321 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
322 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
323 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
324 }
325
326 /* ADC */
327 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
328 return;
329 }
330 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
331 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
332 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
333
334 /* FMC, The number of CS is set at the board level */
335 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
336 &error_abort);
337 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
338 return;
339 }
340 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
341 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
342 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
343 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
344 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
345
346 /* SPI */
347 for (i = 0; i < sc->spis_num; i++) {
348 object_property_set_link(OBJECT(&s->spi[i]), "dram",
349 OBJECT(&s->sram), &error_abort);
350 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
351 return;
352 }
353 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
354 sc->memmap[ASPEED_DEV_SPI1 + i]);
355 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
356 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
357 }
358
359 /* Secure Boot Controller */
360 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
361 return;
362 }
363 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
364
365 /* HACE */
366 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram),
367 &error_abort);
368 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
369 return;
370 }
371 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
372 sc->memmap[ASPEED_DEV_HACE]);
373 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
374 aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
375
376 /* Watch dog */
377 for (i = 0; i < sc->wdts_num; i++) {
378 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
379 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
380
381 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
382 &error_abort);
383 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
384 return;
385 }
386 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
387 }
388
389 /* GPIO */
390 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
391 return;
392 }
393 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
394 sc->memmap[ASPEED_DEV_GPIO]);
395 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
396 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
397
398 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm",
399 sc->memmap[ASPEED_DEV_PWM], 0x100);
400
401 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi",
402 sc->memmap[ASPEED_DEV_ESPI], 0x800);
403
404 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc",
405 sc->memmap[ASPEED_DEV_UDC], 0x1000);
406 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom",
407 sc->memmap[ASPEED_DEV_SGPIOM], 0x100);
408
409 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag",
410 sc->memmap[ASPEED_DEV_JTAG0], 0x20);
411 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag",
412 sc->memmap[ASPEED_DEV_JTAG1], 0x20);
413 }
414
415 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
416 {
417 DeviceClass *dc = DEVICE_CLASS(klass);
418 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
419
420 dc->realize = aspeed_soc_ast1030_realize;
421
422 sc->name = "ast1030-a1";
423 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */
424 sc->silicon_rev = AST1030_A1_SILICON_REV;
425 sc->sram_size = 0xc0000;
426 sc->secsram_size = 0x40000; /* 256 * KiB */
427 sc->spis_num = 2;
428 sc->ehcis_num = 0;
429 sc->wdts_num = 4;
430 sc->macs_num = 1;
431 sc->uarts_num = 13;
432 sc->irqmap = aspeed_soc_ast1030_irqmap;
433 sc->memmap = aspeed_soc_ast1030_memmap;
434 sc->num_cpus = 1;
435 sc->get_irq = aspeed_soc_ast1030_get_irq;
436 }
437
438 static const TypeInfo aspeed_soc_ast1030_type_info = {
439 .name = "ast1030-a1",
440 .parent = TYPE_ASPEED_SOC,
441 .instance_size = sizeof(AspeedSoCState),
442 .instance_init = aspeed_soc_ast1030_init,
443 .class_init = aspeed_soc_ast1030_class_init,
444 .class_size = sizeof(AspeedSoCClass),
445 };
446
447 static void aspeed_soc_register_types(void)
448 {
449 type_register_static(&aspeed_soc_ast1030_type_info);
450 }
451
452 type_init(aspeed_soc_register_types)
armbru's QEMU hackery