hw/arm/mainstone.c

   1 /*
   2  * PXA270-based Intel Mainstone platforms.
   3  *
   4  * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
   5  *                                    <akuster@mvista.com>
   6  *
   7  * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
   8  *
   9  * This code is licensed under the GNU GPL v2.
  10  *
  11  * Contributions after 2012-01-13 are licensed under the terms of the
  12  * GNU GPL, version 2 or (at your option) any later version.
  13  */
  14 #include "qemu/osdep.h"
  15 #include "qemu/units.h"
  16 #include "qemu/error-report.h"
  17 #include "qapi/error.h"
  18 #include "hw/arm/pxa.h"
  19 #include "hw/arm/boot.h"
  20 #include "net/net.h"
  21 #include "hw/net/smc91c111.h"
  22 #include "hw/boards.h"
  23 #include "hw/block/flash.h"
  24 #include "hw/sysbus.h"
  25 #include "exec/address-spaces.h"
  26 #include "cpu.h"
  27
  28 /* Device addresses */
  29 #define MST_FPGA_PHYS   0x08000000
  30 #define MST_ETH_PHYS    0x10000300
  31 #define MST_FLASH_0             0x00000000
  32 #define MST_FLASH_1             0x04000000
  33
  34 /* IRQ definitions */
  35 #define MMC_IRQ       0
  36 #define USIM_IRQ      1
  37 #define USBC_IRQ      2
  38 #define ETHERNET_IRQ  3
  39 #define AC97_IRQ      4
  40 #define PEN_IRQ       5
  41 #define MSINS_IRQ     6
  42 #define EXBRD_IRQ     7
  43 #define S0_CD_IRQ     9
  44 #define S0_STSCHG_IRQ 10
  45 #define S0_IRQ        11
  46 #define S1_CD_IRQ     13
  47 #define S1_STSCHG_IRQ 14
  48 #define S1_IRQ        15
  49
  50 static const struct keymap map[0xE0] = {
  51     [0 ... 0xDF] = { -1, -1 },
  52     [0x1e] = {0,0}, /* a */
  53     [0x30] = {0,1}, /* b */
  54     [0x2e] = {0,2}, /* c */
  55     [0x20] = {0,3}, /* d */
  56     [0x12] = {0,4}, /* e */
  57     [0x21] = {0,5}, /* f */
  58     [0x22] = {1,0}, /* g */
  59     [0x23] = {1,1}, /* h */
  60     [0x17] = {1,2}, /* i */
  61     [0x24] = {1,3}, /* j */
  62     [0x25] = {1,4}, /* k */
  63     [0x26] = {1,5}, /* l */
  64     [0x32] = {2,0}, /* m */
  65     [0x31] = {2,1}, /* n */
  66     [0x18] = {2,2}, /* o */
  67     [0x19] = {2,3}, /* p */
  68     [0x10] = {2,4}, /* q */
  69     [0x13] = {2,5}, /* r */
  70     [0x1f] = {3,0}, /* s */
  71     [0x14] = {3,1}, /* t */
  72     [0x16] = {3,2}, /* u */
  73     [0x2f] = {3,3}, /* v */
  74     [0x11] = {3,4}, /* w */
  75     [0x2d] = {3,5}, /* x */
  76     [0x34] = {4,0}, /* . */
  77     [0x15] = {4,2}, /* y */
  78     [0x2c] = {4,3}, /* z */
  79     [0x35] = {4,4}, /* / */
  80     [0xc7] = {5,0}, /* Home */
  81     [0x2a] = {5,1}, /* shift */
  82     /*
  83      * There are two matrix positions which map to space,
  84      * but QEMU can only use one of them for the reverse
  85      * mapping, so simply use the second one.
  86      */
  87     /* [0x39] = {5,2}, space */
  88     [0x39] = {5,3}, /* space */
  89     /*
  90      * Matrix position {5,4} and other keys are missing here.
  91      * TODO: Compare with Linux code and test real hardware.
  92      */
  93     [0x1c] = {5,4}, /* enter */
  94     [0x0e] = {5,5}, /* backspace */
  95     [0xc8] = {6,0}, /* up */
  96     [0xd0] = {6,1}, /* down */
  97     [0xcb] = {6,2}, /* left */
  98     [0xcd] = {6,3}, /* right */
  99 };
 100
 101 enum mainstone_model_e { mainstone };
 102
 103 #define MAINSTONE_RAM_SIZE      (64 * MiB)
 104 #define MAINSTONE_ROM_SIZE      (8 * MiB)
 105 #define MAINSTONE_FLASH_SIZE    (32 * MiB)
 106
 107 static struct arm_boot_info mainstone_binfo = {
 108     .loader_start = PXA2XX_SDRAM_BASE,
 109     .ram_size = MAINSTONE_RAM_SIZE,
 110 };
 111
 112 #define FLASH_SECTOR_SIZE   (256 * KiB)
 113
 114 static void mainstone_common_init(MachineState *machine,
 115                                   enum mainstone_model_e model, int arm_id)
 116 {
 117     hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
 118     PXA2xxState *mpu;
 119     DeviceState *mst_irq;
 120     DriveInfo *dinfo;
 121     int i;
 122     MemoryRegion *rom = g_new(MemoryRegion, 1);
 123
 124     /* Setup CPU & memory */
 125     mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type);
 126     memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM_SIZE,
 127                            &error_fatal);
 128     memory_region_add_subregion(get_system_memory(), 0x00000000, rom);
 129
 130     /* There are two 32MiB flash devices on the board */
 131     for (i = 0; i < 2; i ++) {
 132         dinfo = drive_get(IF_PFLASH, 0, i);
 133         pflash_cfi01_register(mainstone_flash_base[i],
 134                               i ? "mainstone.flash1" : "mainstone.flash0",
 135                               MAINSTONE_FLASH_SIZE,
 136                               dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 137                               FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
 138     }
 139
 140     mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
 141                     qdev_get_gpio_in(mpu->gpio, 0));
 142
 143     /* setup keypad */
 144     pxa27x_register_keypad(mpu->kp, map, 0xe0);
 145
 146     /* MMC/SD host */
 147     pxa2xx_mmci_handlers(mpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
 148
 149     pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[0],
 150             qdev_get_gpio_in(mst_irq, S0_IRQ),
 151             qdev_get_gpio_in(mst_irq, S0_CD_IRQ));
 152     pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[1],
 153             qdev_get_gpio_in(mst_irq, S1_IRQ),
 154             qdev_get_gpio_in(mst_irq, S1_CD_IRQ));
 155
 156     smc91c111_init(&nd_table[0], MST_ETH_PHYS,
 157                     qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
 158
 159     mainstone_binfo.board_id = arm_id;
 160     arm_load_kernel(mpu->cpu, machine, &mainstone_binfo);
 161 }
 162
 163 static void mainstone_init(MachineState *machine)
 164 {
 165     mainstone_common_init(machine, mainstone, 0x196);
 166 }
 167
 168 static void mainstone2_machine_init(MachineClass *mc)
 169 {
 170     mc->desc = "Mainstone II (PXA27x)";
 171     mc->init = mainstone_init;
 172     mc->ignore_memory_transaction_failures = true;
 173     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
 174 }
 175
 176 DEFINE_MACHINE("mainstone", mainstone2_machine_init)