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qapi: Improve specificity of type/member descriptions
[qemu/armbru.git] / hw / audio / intel-hda.c
blobb9ed231fe849a068f00e7893450ca738c637e495
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <kraxel@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/pci/pci.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/pci/msi.h"
24 #include "qemu/timer.h"
25 #include "qemu/bitops.h"
26 #include "qemu/log.h"
27 #include "qemu/module.h"
28 #include "qemu/error-report.h"
29 #include "hw/audio/soundhw.h"
30 #include "intel-hda.h"
31 #include "migration/vmstate.h"
32 #include "intel-hda-defs.h"
33 #include "sysemu/dma.h"
34 #include "qapi/error.h"
35 #include "qom/object.h"
36
37 /* --------------------------------------------------------------------- */
38 /* hda bus */
39
40 static Property hda_props[] = {
41 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
42 DEFINE_PROP_END_OF_LIST()
43 };
44
45 static const TypeInfo hda_codec_bus_info = {
46 .name = TYPE_HDA_BUS,
47 .parent = TYPE_BUS,
48 .instance_size = sizeof(HDACodecBus),
49 };
50
51 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
52 hda_codec_response_func response,
53 hda_codec_xfer_func xfer)
54 {
55 qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
56 bus->response = response;
57 bus->xfer = xfer;
58 }
59
60 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp)
61 {
62 HDACodecBus *bus = HDA_BUS(qdev->parent_bus);
63 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
64 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
65
66 if (dev->cad == -1) {
67 dev->cad = bus->next_cad;
68 }
69 if (dev->cad >= 15) {
70 error_setg(errp, "HDA audio codec address is full");
71 return;
72 }
73 bus->next_cad = dev->cad + 1;
74 if (cdc->init(dev) != 0) {
75 error_setg(errp, "HDA audio init failed");
76 }
77 }
78
79 static void hda_codec_dev_unrealize(DeviceState *qdev)
80 {
81 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
82 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
83
84 if (cdc->exit) {
85 cdc->exit(dev);
86 }
87 }
88
89 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
90 {
91 BusChild *kid;
92 HDACodecDevice *cdev;
93
94 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
95 DeviceState *qdev = kid->child;
96 cdev = HDA_CODEC_DEVICE(qdev);
97 if (cdev->cad == cad) {
98 return cdev;
99 }
100 }
101 return NULL;
102 }
103
104 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
105 {
106 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
107 bus->response(dev, solicited, response);
108 }
109
110 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
111 uint8_t *buf, uint32_t len)
112 {
113 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
114 return bus->xfer(dev, stnr, output, buf, len);
115 }
116
117 /* --------------------------------------------------------------------- */
118 /* intel hda emulation */
119
120 typedef struct IntelHDAStream IntelHDAStream;
121 typedef struct IntelHDAState IntelHDAState;
122 typedef struct IntelHDAReg IntelHDAReg;
123
124 typedef struct bpl {
125 uint64_t addr;
126 uint32_t len;
127 uint32_t flags;
128 } bpl;
129
130 struct IntelHDAStream {
131 /* registers */
132 uint32_t ctl;
133 uint32_t lpib;
134 uint32_t cbl;
135 uint32_t lvi;
136 uint32_t fmt;
137 uint32_t bdlp_lbase;
138 uint32_t bdlp_ubase;
139
140 /* state */
141 bpl *bpl;
142 uint32_t bentries;
143 uint32_t bsize, be, bp;
144 };
145
146 struct IntelHDAState {
147 PCIDevice pci;
148 const char *name;
149 HDACodecBus codecs;
150
151 /* registers */
152 uint32_t g_ctl;
153 uint32_t wake_en;
154 uint32_t state_sts;
155 uint32_t int_ctl;
156 uint32_t int_sts;
157 uint32_t wall_clk;
158
159 uint32_t corb_lbase;
160 uint32_t corb_ubase;
161 uint32_t corb_rp;
162 uint32_t corb_wp;
163 uint32_t corb_ctl;
164 uint32_t corb_sts;
165 uint32_t corb_size;
166
167 uint32_t rirb_lbase;
168 uint32_t rirb_ubase;
169 uint32_t rirb_wp;
170 uint32_t rirb_cnt;
171 uint32_t rirb_ctl;
172 uint32_t rirb_sts;
173 uint32_t rirb_size;
174
175 uint32_t dp_lbase;
176 uint32_t dp_ubase;
177
178 uint32_t icw;
179 uint32_t irr;
180 uint32_t ics;
181
182 /* streams */
183 IntelHDAStream st[8];
184
185 /* state */
186 MemoryRegion container;
187 MemoryRegion mmio;
188 MemoryRegion alias;
189 uint32_t rirb_count;
190 int64_t wall_base_ns;
191
192 /* debug logging */
193 const IntelHDAReg *last_reg;
194 uint32_t last_val;
195 uint32_t last_write;
196 uint32_t last_sec;
197 uint32_t repeat_count;
198
199 /* properties */
200 uint32_t debug;
201 OnOffAuto msi;
202 bool old_msi_addr;
203 };
204
205 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
206
207 DECLARE_INSTANCE_CHECKER(IntelHDAState, INTEL_HDA,
208 TYPE_INTEL_HDA_GENERIC)
209
210 struct IntelHDAReg {
211 const char *name; /* register name */
212 uint32_t size; /* size in bytes */
213 uint32_t reset; /* reset value */
214 uint32_t wmask; /* write mask */
215 uint32_t wclear; /* write 1 to clear bits */
216 uint32_t offset; /* location in IntelHDAState */
217 uint32_t shift; /* byte access entries for dwords */
218 uint32_t stream;
219 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
220 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
221 };
222
223 /* --------------------------------------------------------------------- */
224
225 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
226 {
227 return ((uint64_t)ubase << 32) | lbase;
228 }
229
230 static void intel_hda_update_int_sts(IntelHDAState *d)
231 {
232 uint32_t sts = 0;
233 uint32_t i;
234
235 /* update controller status */
236 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
237 sts |= (1 << 30);
238 }
239 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
240 sts |= (1 << 30);
241 }
242 if (d->state_sts & d->wake_en) {
243 sts |= (1 << 30);
244 }
245
246 /* update stream status */
247 for (i = 0; i < 8; i++) {
248 /* buffer completion interrupt */
249 if (d->st[i].ctl & (1 << 26)) {
250 sts |= (1 << i);
251 }
252 }
253
254 /* update global status */
255 if (sts & d->int_ctl) {
256 sts |= (1U << 31);
257 }
258
259 d->int_sts = sts;
260 }
261
262 static void intel_hda_update_irq(IntelHDAState *d)
263 {
264 bool msi = msi_enabled(&d->pci);
265 int level;
266
267 intel_hda_update_int_sts(d);
268 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) {
269 level = 1;
270 } else {
271 level = 0;
272 }
273 dprint(d, 2, "%s: level %d [%s]\n", __func__,
274 level, msi ? "msi" : "intx");
275 if (msi) {
276 if (level) {
277 msi_notify(&d->pci, 0);
278 }
279 } else {
280 pci_set_irq(&d->pci, level);
281 }
282 }
283
284 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
285 {
286 uint32_t cad, nid, data;
287 HDACodecDevice *codec;
288 HDACodecDeviceClass *cdc;
289
290 cad = (verb >> 28) & 0x0f;
291 if (verb & (1 << 27)) {
292 /* indirect node addressing, not specified in HDA 1.0 */
293 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__);
294 return -1;
295 }
296 nid = (verb >> 20) & 0x7f;
297 data = verb & 0xfffff;
298
299 codec = hda_codec_find(&d->codecs, cad);
300 if (codec == NULL) {
301 dprint(d, 1, "%s: addressed non-existing codec\n", __func__);
302 return -1;
303 }
304 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
305 cdc->command(codec, nid, data);
306 return 0;
307 }
308
309 static void intel_hda_corb_run(IntelHDAState *d)
310 {
311 hwaddr addr;
312 uint32_t rp, verb;
313
314 if (d->ics & ICH6_IRS_BUSY) {
315 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw);
316 intel_hda_send_command(d, d->icw);
317 return;
318 }
319
320 for (;;) {
321 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
322 dprint(d, 2, "%s: !run\n", __func__);
323 return;
324 }
325 if ((d->corb_rp & 0xff) == d->corb_wp) {
326 dprint(d, 2, "%s: corb ring empty\n", __func__);
327 return;
328 }
329 if (d->rirb_count == d->rirb_cnt) {
330 dprint(d, 2, "%s: rirb count reached\n", __func__);
331 return;
332 }
333
334 rp = (d->corb_rp + 1) & 0xff;
335 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
336 ldl_le_pci_dma(&d->pci, addr + 4 * rp, &verb, MEMTXATTRS_UNSPECIFIED);
337 d->corb_rp = rp;
338
339 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb);
340 intel_hda_send_command(d, verb);
341 }
342 }
343
344 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
345 {
346 const MemTxAttrs attrs = { .memory = true };
347 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
348 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
349 hwaddr addr;
350 uint32_t wp, ex;
351 MemTxResult res = MEMTX_OK;
352
353 if (d->ics & ICH6_IRS_BUSY) {
354 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
355 __func__, response, dev->cad);
356 d->irr = response;
357 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
358 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
359 return;
360 }
361
362 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
363 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__);
364 return;
365 }
366
367 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
368 wp = (d->rirb_wp + 1) & 0xff;
369 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
370 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs);
371 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs);
372 if (res != MEMTX_OK && (d->rirb_ctl & ICH6_RBCTL_OVERRUN_EN)) {
373 d->rirb_sts |= ICH6_RBSTS_OVERRUN;
374 intel_hda_update_irq(d);
375 }
376 d->rirb_wp = wp;
377
378 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
379 __func__, wp, response, ex);
380
381 d->rirb_count++;
382 if (d->rirb_count == d->rirb_cnt) {
383 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count);
384 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
385 d->rirb_sts |= ICH6_RBSTS_IRQ;
386 intel_hda_update_irq(d);
387 }
388 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
389 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__,
390 d->rirb_count, d->rirb_cnt);
391 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
392 d->rirb_sts |= ICH6_RBSTS_IRQ;
393 intel_hda_update_irq(d);
394 }
395 }
396 }
397
398 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
399 uint8_t *buf, uint32_t len)
400 {
401 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
402 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
403 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
404 hwaddr addr;
405 uint32_t s, copy, left;
406 IntelHDAStream *st;
407 bool irq = false;
408
409 st = output ? d->st + 4 : d->st;
410 for (s = 0; s < 4; s++) {
411 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
412 st = st + s;
413 break;
414 }
415 }
416 if (s == 4) {
417 return false;
418 }
419 if (st->bpl == NULL) {
420 return false;
421 }
422
423 left = len;
424 s = st->bentries;
425 while (left > 0 && s-- > 0) {
426 copy = left;
427 if (copy > st->bsize - st->lpib)
428 copy = st->bsize - st->lpib;
429 if (copy > st->bpl[st->be].len - st->bp)
430 copy = st->bpl[st->be].len - st->bp;
431
432 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
433 st->be, st->bp, st->bpl[st->be].len, copy);
434
435 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output,
436 attrs);
437 st->lpib += copy;
438 st->bp += copy;
439 buf += copy;
440 left -= copy;
441
442 if (st->bpl[st->be].len == st->bp) {
443 /* bpl entry filled */
444 if (st->bpl[st->be].flags & 0x01) {
445 irq = true;
446 }
447 st->bp = 0;
448 st->be++;
449 if (st->be == st->bentries) {
450 /* bpl wrap around */
451 st->be = 0;
452 st->lpib = 0;
453 }
454 }
455 }
456 if (d->dp_lbase & 0x01) {
457 s = st - d->st;
458 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
459 stl_le_pci_dma(&d->pci, addr + 8 * s, st->lpib, attrs);
460 }
461 dprint(d, 3, "dma: --\n");
462
463 if (irq) {
464 st->ctl |= (1 << 26); /* buffer completion interrupt */
465 intel_hda_update_irq(d);
466 }
467 return true;
468 }
469
470 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
471 {
472 hwaddr addr;
473 uint8_t buf[16];
474 uint32_t i;
475
476 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
477 st->bentries = st->lvi +1;
478 g_free(st->bpl);
479 st->bpl = g_new(bpl, st->bentries);
480 for (i = 0; i < st->bentries; i++, addr += 16) {
481 pci_dma_read(&d->pci, addr, buf, 16);
482 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
483 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
484 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
485 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
486 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
487 }
488
489 st->bsize = st->cbl;
490 st->lpib = 0;
491 st->be = 0;
492 st->bp = 0;
493 }
494
495 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
496 {
497 BusChild *kid;
498 HDACodecDevice *cdev;
499
500 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
501 DeviceState *qdev = kid->child;
502 HDACodecDeviceClass *cdc;
503
504 cdev = HDA_CODEC_DEVICE(qdev);
505 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
506 if (cdc->stream) {
507 cdc->stream(cdev, stream, running, output);
508 }
509 }
510 }
511
512 /* --------------------------------------------------------------------- */
513
514 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
515 {
516 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
517 device_cold_reset(DEVICE(d));
518 }
519 }
520
521 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
522 {
523 intel_hda_update_irq(d);
524 }
525
526 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
527 {
528 intel_hda_update_irq(d);
529 }
530
531 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
532 {
533 intel_hda_update_irq(d);
534 }
535
536 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
537 {
538 int64_t ns;
539
540 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
541 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
542 }
543
544 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
545 {
546 intel_hda_corb_run(d);
547 }
548
549 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
550 {
551 intel_hda_corb_run(d);
552 }
553
554 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
555 {
556 if (d->rirb_wp & ICH6_RIRBWP_RST) {
557 d->rirb_wp = 0;
558 }
559 }
560
561 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
562 {
563 intel_hda_update_irq(d);
564
565 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
566 /* cleared ICH6_RBSTS_IRQ */
567 d->rirb_count = 0;
568 intel_hda_corb_run(d);
569 }
570 }
571
572 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
573 {
574 if (d->ics & ICH6_IRS_BUSY) {
575 intel_hda_corb_run(d);
576 }
577 }
578
579 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
580 {
581 bool output = reg->stream >= 4;
582 IntelHDAStream *st = d->st + reg->stream;
583
584 if (st->ctl & 0x01) {
585 /* reset */
586 dprint(d, 1, "st #%d: reset\n", reg->stream);
587 st->ctl = SD_STS_FIFO_READY << 24 | SD_CTL_STREAM_RESET;
588 }
589 if ((st->ctl & 0x02) != (old & 0x02)) {
590 uint32_t stnr = (st->ctl >> 20) & 0x0f;
591 /* run bit flipped */
592 if (st->ctl & 0x02) {
593 /* start */
594 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
595 reg->stream, stnr, st->cbl);
596 intel_hda_parse_bdl(d, st);
597 intel_hda_notify_codecs(d, stnr, true, output);
598 } else {
599 /* stop */
600 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
601 intel_hda_notify_codecs(d, stnr, false, output);
602 }
603 }
604 intel_hda_update_irq(d);
605 }
606
607 /* --------------------------------------------------------------------- */
608
609 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
610
611 static const struct IntelHDAReg regtab[] = {
612 /* global */
613 [ ICH6_REG_GCAP ] = {
614 .name = "GCAP",
615 .size = 2,
616 .reset = 0x4401,
617 },
618 [ ICH6_REG_VMIN ] = {
619 .name = "VMIN",
620 .size = 1,
621 },
622 [ ICH6_REG_VMAJ ] = {
623 .name = "VMAJ",
624 .size = 1,
625 .reset = 1,
626 },
627 [ ICH6_REG_OUTPAY ] = {
628 .name = "OUTPAY",
629 .size = 2,
630 .reset = 0x3c,
631 },
632 [ ICH6_REG_INPAY ] = {
633 .name = "INPAY",
634 .size = 2,
635 .reset = 0x1d,
636 },
637 [ ICH6_REG_GCTL ] = {
638 .name = "GCTL",
639 .size = 4,
640 .wmask = 0x0103,
641 .offset = offsetof(IntelHDAState, g_ctl),
642 .whandler = intel_hda_set_g_ctl,
643 },
644 [ ICH6_REG_WAKEEN ] = {
645 .name = "WAKEEN",
646 .size = 2,
647 .wmask = 0x7fff,
648 .offset = offsetof(IntelHDAState, wake_en),
649 .whandler = intel_hda_set_wake_en,
650 },
651 [ ICH6_REG_STATESTS ] = {
652 .name = "STATESTS",
653 .size = 2,
654 .wmask = 0x7fff,
655 .wclear = 0x7fff,
656 .offset = offsetof(IntelHDAState, state_sts),
657 .whandler = intel_hda_set_state_sts,
658 },
659
660 /* interrupts */
661 [ ICH6_REG_INTCTL ] = {
662 .name = "INTCTL",
663 .size = 4,
664 .wmask = 0xc00000ff,
665 .offset = offsetof(IntelHDAState, int_ctl),
666 .whandler = intel_hda_set_int_ctl,
667 },
668 [ ICH6_REG_INTSTS ] = {
669 .name = "INTSTS",
670 .size = 4,
671 .wmask = 0xc00000ff,
672 .wclear = 0xc00000ff,
673 .offset = offsetof(IntelHDAState, int_sts),
674 },
675
676 /* misc */
677 [ ICH6_REG_WALLCLK ] = {
678 .name = "WALLCLK",
679 .size = 4,
680 .offset = offsetof(IntelHDAState, wall_clk),
681 .rhandler = intel_hda_get_wall_clk,
682 },
683
684 /* dma engine */
685 [ ICH6_REG_CORBLBASE ] = {
686 .name = "CORBLBASE",
687 .size = 4,
688 .wmask = 0xffffff80,
689 .offset = offsetof(IntelHDAState, corb_lbase),
690 },
691 [ ICH6_REG_CORBUBASE ] = {
692 .name = "CORBUBASE",
693 .size = 4,
694 .wmask = 0xffffffff,
695 .offset = offsetof(IntelHDAState, corb_ubase),
696 },
697 [ ICH6_REG_CORBWP ] = {
698 .name = "CORBWP",
699 .size = 2,
700 .wmask = 0xff,
701 .offset = offsetof(IntelHDAState, corb_wp),
702 .whandler = intel_hda_set_corb_wp,
703 },
704 [ ICH6_REG_CORBRP ] = {
705 .name = "CORBRP",
706 .size = 2,
707 .wmask = 0x80ff,
708 .offset = offsetof(IntelHDAState, corb_rp),
709 },
710 [ ICH6_REG_CORBCTL ] = {
711 .name = "CORBCTL",
712 .size = 1,
713 .wmask = 0x03,
714 .offset = offsetof(IntelHDAState, corb_ctl),
715 .whandler = intel_hda_set_corb_ctl,
716 },
717 [ ICH6_REG_CORBSTS ] = {
718 .name = "CORBSTS",
719 .size = 1,
720 .wmask = 0x01,
721 .wclear = 0x01,
722 .offset = offsetof(IntelHDAState, corb_sts),
723 },
724 [ ICH6_REG_CORBSIZE ] = {
725 .name = "CORBSIZE",
726 .size = 1,
727 .reset = 0x42,
728 .offset = offsetof(IntelHDAState, corb_size),
729 },
730 [ ICH6_REG_RIRBLBASE ] = {
731 .name = "RIRBLBASE",
732 .size = 4,
733 .wmask = 0xffffff80,
734 .offset = offsetof(IntelHDAState, rirb_lbase),
735 },
736 [ ICH6_REG_RIRBUBASE ] = {
737 .name = "RIRBUBASE",
738 .size = 4,
739 .wmask = 0xffffffff,
740 .offset = offsetof(IntelHDAState, rirb_ubase),
741 },
742 [ ICH6_REG_RIRBWP ] = {
743 .name = "RIRBWP",
744 .size = 2,
745 .wmask = 0x8000,
746 .offset = offsetof(IntelHDAState, rirb_wp),
747 .whandler = intel_hda_set_rirb_wp,
748 },
749 [ ICH6_REG_RINTCNT ] = {
750 .name = "RINTCNT",
751 .size = 2,
752 .wmask = 0xff,
753 .offset = offsetof(IntelHDAState, rirb_cnt),
754 },
755 [ ICH6_REG_RIRBCTL ] = {
756 .name = "RIRBCTL",
757 .size = 1,
758 .wmask = 0x07,
759 .offset = offsetof(IntelHDAState, rirb_ctl),
760 },
761 [ ICH6_REG_RIRBSTS ] = {
762 .name = "RIRBSTS",
763 .size = 1,
764 .wmask = 0x05,
765 .wclear = 0x05,
766 .offset = offsetof(IntelHDAState, rirb_sts),
767 .whandler = intel_hda_set_rirb_sts,
768 },
769 [ ICH6_REG_RIRBSIZE ] = {
770 .name = "RIRBSIZE",
771 .size = 1,
772 .reset = 0x42,
773 .offset = offsetof(IntelHDAState, rirb_size),
774 },
775
776 [ ICH6_REG_DPLBASE ] = {
777 .name = "DPLBASE",
778 .size = 4,
779 .wmask = 0xffffff81,
780 .offset = offsetof(IntelHDAState, dp_lbase),
781 },
782 [ ICH6_REG_DPUBASE ] = {
783 .name = "DPUBASE",
784 .size = 4,
785 .wmask = 0xffffffff,
786 .offset = offsetof(IntelHDAState, dp_ubase),
787 },
788
789 [ ICH6_REG_IC ] = {
790 .name = "ICW",
791 .size = 4,
792 .wmask = 0xffffffff,
793 .offset = offsetof(IntelHDAState, icw),
794 },
795 [ ICH6_REG_IR ] = {
796 .name = "IRR",
797 .size = 4,
798 .offset = offsetof(IntelHDAState, irr),
799 },
800 [ ICH6_REG_IRS ] = {
801 .name = "ICS",
802 .size = 2,
803 .wmask = 0x0003,
804 .wclear = 0x0002,
805 .offset = offsetof(IntelHDAState, ics),
806 .whandler = intel_hda_set_ics,
807 },
808
809 #define HDA_STREAM(_t, _i) \
810 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
811 .stream = _i, \
812 .name = _t stringify(_i) " CTL", \
813 .size = 4, \
814 .wmask = 0x1cff001f, \
815 .offset = offsetof(IntelHDAState, st[_i].ctl), \
816 .whandler = intel_hda_set_st_ctl, \
817 }, \
818 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
819 .stream = _i, \
820 .name = _t stringify(_i) " CTL(stnr)", \
821 .size = 1, \
822 .shift = 16, \
823 .wmask = 0x00ff0000, \
824 .offset = offsetof(IntelHDAState, st[_i].ctl), \
825 .whandler = intel_hda_set_st_ctl, \
826 }, \
827 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
828 .stream = _i, \
829 .name = _t stringify(_i) " CTL(sts)", \
830 .size = 1, \
831 .shift = 24, \
832 .wmask = 0x1c000000, \
833 .wclear = 0x1c000000, \
834 .offset = offsetof(IntelHDAState, st[_i].ctl), \
835 .whandler = intel_hda_set_st_ctl, \
836 .reset = SD_STS_FIFO_READY << 24 \
837 }, \
838 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
839 .stream = _i, \
840 .name = _t stringify(_i) " LPIB", \
841 .size = 4, \
842 .offset = offsetof(IntelHDAState, st[_i].lpib), \
843 }, \
844 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
845 .stream = _i, \
846 .name = _t stringify(_i) " CBL", \
847 .size = 4, \
848 .wmask = 0xffffffff, \
849 .offset = offsetof(IntelHDAState, st[_i].cbl), \
850 }, \
851 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
852 .stream = _i, \
853 .name = _t stringify(_i) " LVI", \
854 .size = 2, \
855 .wmask = 0x00ff, \
856 .offset = offsetof(IntelHDAState, st[_i].lvi), \
857 }, \
858 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
859 .stream = _i, \
860 .name = _t stringify(_i) " FIFOS", \
861 .size = 2, \
862 .reset = HDA_BUFFER_SIZE, \
863 }, \
864 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
865 .stream = _i, \
866 .name = _t stringify(_i) " FMT", \
867 .size = 2, \
868 .wmask = 0x7f7f, \
869 .offset = offsetof(IntelHDAState, st[_i].fmt), \
870 }, \
871 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
872 .stream = _i, \
873 .name = _t stringify(_i) " BDLPL", \
874 .size = 4, \
875 .wmask = 0xffffff80, \
876 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
877 }, \
878 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
879 .stream = _i, \
880 .name = _t stringify(_i) " BDLPU", \
881 .size = 4, \
882 .wmask = 0xffffffff, \
883 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
884 }, \
885
886 HDA_STREAM("IN", 0)
887 HDA_STREAM("IN", 1)
888 HDA_STREAM("IN", 2)
889 HDA_STREAM("IN", 3)
890
891 HDA_STREAM("OUT", 4)
892 HDA_STREAM("OUT", 5)
893 HDA_STREAM("OUT", 6)
894 HDA_STREAM("OUT", 7)
895
896 };
897
898 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
899 {
900 const IntelHDAReg *reg;
901
902 if (addr >= ARRAY_SIZE(regtab)) {
903 goto noreg;
904 }
905 reg = regtab+addr;
906 if (reg->name == NULL) {
907 goto noreg;
908 }
909 return reg;
910
911 noreg:
912 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
913 return NULL;
914 }
915
916 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
917 {
918 uint8_t *addr = (void*)d;
919
920 addr += reg->offset;
921 return (uint32_t*)addr;
922 }
923
924 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
925 uint32_t wmask)
926 {
927 uint32_t *addr;
928 uint32_t old;
929
930 if (!reg) {
931 return;
932 }
933 if (!reg->wmask) {
934 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n",
935 reg->name);
936 return;
937 }
938
939 if (d->debug) {
940 time_t now = time(NULL);
941 if (d->last_write && d->last_reg == reg && d->last_val == val) {
942 d->repeat_count++;
943 if (d->last_sec != now) {
944 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
945 d->last_sec = now;
946 d->repeat_count = 0;
947 }
948 } else {
949 if (d->repeat_count) {
950 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
951 }
952 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
953 d->last_write = 1;
954 d->last_reg = reg;
955 d->last_val = val;
956 d->last_sec = now;
957 d->repeat_count = 0;
958 }
959 }
960 assert(reg->offset != 0);
961
962 addr = intel_hda_reg_addr(d, reg);
963 old = *addr;
964
965 if (reg->shift) {
966 val <<= reg->shift;
967 wmask <<= reg->shift;
968 }
969 wmask &= reg->wmask;
970 *addr &= ~wmask;
971 *addr |= wmask & val;
972 *addr &= ~(val & reg->wclear);
973
974 if (reg->whandler) {
975 reg->whandler(d, reg, old);
976 }
977 }
978
979 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
980 uint32_t rmask)
981 {
982 uint32_t *addr, ret;
983
984 if (!reg) {
985 return 0;
986 }
987
988 if (reg->rhandler) {
989 reg->rhandler(d, reg);
990 }
991
992 if (reg->offset == 0) {
993 /* constant read-only register */
994 ret = reg->reset;
995 } else {
996 addr = intel_hda_reg_addr(d, reg);
997 ret = *addr;
998 if (reg->shift) {
999 ret >>= reg->shift;
1000 }
1001 ret &= rmask;
1002 }
1003 if (d->debug) {
1004 time_t now = time(NULL);
1005 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1006 d->repeat_count++;
1007 if (d->last_sec != now) {
1008 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1009 d->last_sec = now;
1010 d->repeat_count = 0;
1011 }
1012 } else {
1013 if (d->repeat_count) {
1014 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1015 }
1016 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1017 d->last_write = 0;
1018 d->last_reg = reg;
1019 d->last_val = ret;
1020 d->last_sec = now;
1021 d->repeat_count = 0;
1022 }
1023 }
1024 return ret;
1025 }
1026
1027 static void intel_hda_regs_reset(IntelHDAState *d)
1028 {
1029 uint32_t *addr;
1030 int i;
1031
1032 for (i = 0; i < ARRAY_SIZE(regtab); i++) {
1033 if (regtab[i].name == NULL) {
1034 continue;
1035 }
1036 if (regtab[i].offset == 0) {
1037 continue;
1038 }
1039 addr = intel_hda_reg_addr(d, regtab + i);
1040 *addr = regtab[i].reset;
1041 }
1042 }
1043
1044 /* --------------------------------------------------------------------- */
1045
1046 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val,
1047 unsigned size)
1048 {
1049 IntelHDAState *d = opaque;
1050 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1051
1052 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8));
1053 }
1054
1055 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size)
1056 {
1057 IntelHDAState *d = opaque;
1058 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1059
1060 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8));
1061 }
1062
1063 static const MemoryRegionOps intel_hda_mmio_ops = {
1064 .read = intel_hda_mmio_read,
1065 .write = intel_hda_mmio_write,
1066 .impl = {
1067 .min_access_size = 1,
1068 .max_access_size = 4,
1069 },
1070 .endianness = DEVICE_NATIVE_ENDIAN,
1071 };
1072
1073 /* --------------------------------------------------------------------- */
1074
1075 static void intel_hda_reset(DeviceState *dev)
1076 {
1077 BusChild *kid;
1078 IntelHDAState *d = INTEL_HDA(dev);
1079 HDACodecDevice *cdev;
1080
1081 intel_hda_regs_reset(d);
1082 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1083
1084 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1085 DeviceState *qdev = kid->child;
1086 cdev = HDA_CODEC_DEVICE(qdev);
1087 d->state_sts |= (1 << cdev->cad);
1088 }
1089 intel_hda_update_irq(d);
1090 }
1091
1092 static void intel_hda_realize(PCIDevice *pci, Error **errp)
1093 {
1094 IntelHDAState *d = INTEL_HDA(pci);
1095 uint8_t *conf = d->pci.config;
1096 Error *err = NULL;
1097 int ret;
1098
1099 d->name = object_get_typename(OBJECT(d));
1100
1101 pci_config_set_interrupt_pin(conf, 1);
1102
1103 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1104 conf[0x40] = 0x01;
1105
1106 if (d->msi != ON_OFF_AUTO_OFF) {
1107 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60,
1108 1, true, false, &err);
1109 /* Any error other than -ENOTSUP(board's MSI support is broken)
1110 * is a programming error */
1111 assert(!ret || ret == -ENOTSUP);
1112 if (ret && d->msi == ON_OFF_AUTO_ON) {
1113 /* Can't satisfy user's explicit msi=on request, fail */
1114 error_append_hint(&err, "You have to use msi=auto (default) or "
1115 "msi=off with this machine type.\n");
1116 error_propagate(errp, err);
1117 return;
1118 }
1119 assert(!err || d->msi == ON_OFF_AUTO_AUTO);
1120 /* With msi=auto, we fall back to MSI off silently */
1121 error_free(err);
1122 }
1123
1124 memory_region_init(&d->container, OBJECT(d),
1125 "intel-hda-container", 0x4000);
1126 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
1127 "intel-hda", 0x2000);
1128 memory_region_add_subregion(&d->container, 0x0000, &d->mmio);
1129 memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias",
1130 &d->mmio, 0, 0x2000);
1131 memory_region_add_subregion(&d->container, 0x2000, &d->alias);
1132 pci_register_bar(&d->pci, 0, 0, &d->container);
1133
1134 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
1135 intel_hda_response, intel_hda_xfer);
1136 }
1137
1138 static void intel_hda_exit(PCIDevice *pci)
1139 {
1140 IntelHDAState *d = INTEL_HDA(pci);
1141
1142 msi_uninit(&d->pci);
1143 }
1144
1145 static int intel_hda_post_load(void *opaque, int version)
1146 {
1147 IntelHDAState* d = opaque;
1148 int i;
1149
1150 dprint(d, 1, "%s\n", __func__);
1151 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1152 if (d->st[i].ctl & 0x02) {
1153 intel_hda_parse_bdl(d, &d->st[i]);
1154 }
1155 }
1156 intel_hda_update_irq(d);
1157 return 0;
1158 }
1159
1160 static const VMStateDescription vmstate_intel_hda_stream = {
1161 .name = "intel-hda-stream",
1162 .version_id = 1,
1163 .fields = (VMStateField[]) {
1164 VMSTATE_UINT32(ctl, IntelHDAStream),
1165 VMSTATE_UINT32(lpib, IntelHDAStream),
1166 VMSTATE_UINT32(cbl, IntelHDAStream),
1167 VMSTATE_UINT32(lvi, IntelHDAStream),
1168 VMSTATE_UINT32(fmt, IntelHDAStream),
1169 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1170 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1171 VMSTATE_END_OF_LIST()
1172 }
1173 };
1174
1175 static const VMStateDescription vmstate_intel_hda = {
1176 .name = "intel-hda",
1177 .version_id = 1,
1178 .post_load = intel_hda_post_load,
1179 .fields = (VMStateField[]) {
1180 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1181
1182 /* registers */
1183 VMSTATE_UINT32(g_ctl, IntelHDAState),
1184 VMSTATE_UINT32(wake_en, IntelHDAState),
1185 VMSTATE_UINT32(state_sts, IntelHDAState),
1186 VMSTATE_UINT32(int_ctl, IntelHDAState),
1187 VMSTATE_UINT32(int_sts, IntelHDAState),
1188 VMSTATE_UINT32(wall_clk, IntelHDAState),
1189 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1190 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1191 VMSTATE_UINT32(corb_rp, IntelHDAState),
1192 VMSTATE_UINT32(corb_wp, IntelHDAState),
1193 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1194 VMSTATE_UINT32(corb_sts, IntelHDAState),
1195 VMSTATE_UINT32(corb_size, IntelHDAState),
1196 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1197 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1198 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1199 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1200 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1201 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1202 VMSTATE_UINT32(rirb_size, IntelHDAState),
1203 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1204 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1205 VMSTATE_UINT32(icw, IntelHDAState),
1206 VMSTATE_UINT32(irr, IntelHDAState),
1207 VMSTATE_UINT32(ics, IntelHDAState),
1208 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1209 vmstate_intel_hda_stream,
1210 IntelHDAStream),
1211
1212 /* additional state info */
1213 VMSTATE_UINT32(rirb_count, IntelHDAState),
1214 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1215
1216 VMSTATE_END_OF_LIST()
1217 }
1218 };
1219
1220 static Property intel_hda_properties[] = {
1221 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1222 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO),
1223 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false),
1224 DEFINE_PROP_END_OF_LIST(),
1225 };
1226
1227 static void intel_hda_class_init(ObjectClass *klass, void *data)
1228 {
1229 DeviceClass *dc = DEVICE_CLASS(klass);
1230 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1231
1232 k->realize = intel_hda_realize;
1233 k->exit = intel_hda_exit;
1234 k->vendor_id = PCI_VENDOR_ID_INTEL;
1235 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
1236 dc->reset = intel_hda_reset;
1237 dc->vmsd = &vmstate_intel_hda;
1238 device_class_set_props(dc, intel_hda_properties);
1239 }
1240
1241 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
1242 {
1243 DeviceClass *dc = DEVICE_CLASS(klass);
1244 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1245
1246 k->device_id = 0x2668;
1247 k->revision = 1;
1248 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1249 dc->desc = "Intel HD Audio Controller (ich6)";
1250 }
1251
1252 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
1253 {
1254 DeviceClass *dc = DEVICE_CLASS(klass);
1255 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1256
1257 k->device_id = 0x293e;
1258 k->revision = 3;
1259 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1260 dc->desc = "Intel HD Audio Controller (ich9)";
1261 }
1262
1263 static const TypeInfo intel_hda_info = {
1264 .name = TYPE_INTEL_HDA_GENERIC,
1265 .parent = TYPE_PCI_DEVICE,
1266 .instance_size = sizeof(IntelHDAState),
1267 .class_init = intel_hda_class_init,
1268 .abstract = true,
1269 .interfaces = (InterfaceInfo[]) {
1270 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1271 { },
1272 },
1273 };
1274
1275 static const TypeInfo intel_hda_info_ich6 = {
1276 .name = "intel-hda",
1277 .parent = TYPE_INTEL_HDA_GENERIC,
1278 .class_init = intel_hda_class_init_ich6,
1279 };
1280
1281 static const TypeInfo intel_hda_info_ich9 = {
1282 .name = "ich9-intel-hda",
1283 .parent = TYPE_INTEL_HDA_GENERIC,
1284 .class_init = intel_hda_class_init_ich9,
1285 };
1286
1287 static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1288 {
1289 DeviceClass *k = DEVICE_CLASS(klass);
1290 k->realize = hda_codec_dev_realize;
1291 k->unrealize = hda_codec_dev_unrealize;
1292 set_bit(DEVICE_CATEGORY_SOUND, k->categories);
1293 k->bus_type = TYPE_HDA_BUS;
1294 device_class_set_props(k, hda_props);
1295 }
1296
1297 static const TypeInfo hda_codec_device_type_info = {
1298 .name = TYPE_HDA_CODEC_DEVICE,
1299 .parent = TYPE_DEVICE,
1300 .instance_size = sizeof(HDACodecDevice),
1301 .abstract = true,
1302 .class_size = sizeof(HDACodecDeviceClass),
1303 .class_init = hda_codec_device_class_init,
1304 };
1305
1306 /*
1307 * create intel hda controller with codec attached to it,
1308 * so '-soundhw hda' works.
1309 */
1310 static int intel_hda_and_codec_init(PCIBus *bus, const char *audiodev)
1311 {
1312 DeviceState *controller;
1313 BusState *hdabus;
1314 DeviceState *codec;
1315
1316 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
1317 hdabus = QLIST_FIRST(&controller->child_bus);
1318 codec = qdev_new("hda-duplex");
1319 qdev_prop_set_string(codec, "audiodev", audiodev);
1320 qdev_realize_and_unref(codec, hdabus, &error_fatal);
1321 return 0;
1322 }
1323
1324 static void intel_hda_register_types(void)
1325 {
1326 type_register_static(&hda_codec_bus_info);
1327 type_register_static(&intel_hda_info);
1328 type_register_static(&intel_hda_info_ich6);
1329 type_register_static(&intel_hda_info_ich9);
1330 type_register_static(&hda_codec_device_type_info);
1331 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init);
1332 }
1333
1334 type_init(intel_hda_register_types)
armbru's QEMU hackery