hw/char/stm32f2xx_usart.c

   1 /*
   2  * STM32F2XX USART
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/char/stm32f2xx_usart.h"
  27 #include "hw/irq.h"
  28 #include "hw/qdev-properties.h"
  29 #include "hw/qdev-properties-system.h"
  30 #include "qemu/log.h"
  31 #include "qemu/module.h"
  32
  33 #ifndef STM_USART_ERR_DEBUG
  34 #define STM_USART_ERR_DEBUG 0
  35 #endif
  36
  37 #define DB_PRINT_L(lvl, fmt, args...) do { \
  38     if (STM_USART_ERR_DEBUG >= lvl) { \
  39         qemu_log("%s: " fmt, __func__, ## args); \
  40     } \
  41 } while (0)
  42
  43 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
  44
  45 static int stm32f2xx_usart_can_receive(void *opaque)
  46 {
  47     STM32F2XXUsartState *s = opaque;
  48
  49     if (!(s->usart_sr & USART_SR_RXNE)) {
  50         return 1;
  51     }
  52
  53     return 0;
  54 }
  55
  56 static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
  57 {
  58     STM32F2XXUsartState *s = opaque;
  59
  60     if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
  61         /* USART not enabled - drop the chars */
  62         DB_PRINT("Dropping the chars\n");
  63         return;
  64     }
  65
  66     s->usart_dr = *buf;
  67     s->usart_sr |= USART_SR_RXNE;
  68
  69     if (s->usart_cr1 & USART_CR1_RXNEIE) {
  70         qemu_set_irq(s->irq, 1);
  71     }
  72
  73     DB_PRINT("Receiving: %c\n", s->usart_dr);
  74 }
  75
  76 static void stm32f2xx_usart_reset(DeviceState *dev)
  77 {
  78     STM32F2XXUsartState *s = STM32F2XX_USART(dev);
  79
  80     s->usart_sr = USART_SR_RESET;
  81     s->usart_dr = 0x00000000;
  82     s->usart_brr = 0x00000000;
  83     s->usart_cr1 = 0x00000000;
  84     s->usart_cr2 = 0x00000000;
  85     s->usart_cr3 = 0x00000000;
  86     s->usart_gtpr = 0x00000000;
  87
  88     qemu_set_irq(s->irq, 0);
  89 }
  90
  91 static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
  92                                        unsigned int size)
  93 {
  94     STM32F2XXUsartState *s = opaque;
  95     uint64_t retvalue;
  96
  97     DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
  98
  99     switch (addr) {
 100     case USART_SR:
 101         retvalue = s->usart_sr;
 102         qemu_chr_fe_accept_input(&s->chr);
 103         return retvalue;
 104     case USART_DR:
 105         DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
 106         retvalue = s->usart_dr & 0x3FF;
 107         s->usart_sr &= ~USART_SR_RXNE;
 108         qemu_chr_fe_accept_input(&s->chr);
 109         qemu_set_irq(s->irq, 0);
 110         return retvalue;
 111     case USART_BRR:
 112         return s->usart_brr;
 113     case USART_CR1:
 114         return s->usart_cr1;
 115     case USART_CR2:
 116         return s->usart_cr2;
 117     case USART_CR3:
 118         return s->usart_cr3;
 119     case USART_GTPR:
 120         return s->usart_gtpr;
 121     default:
 122         qemu_log_mask(LOG_GUEST_ERROR,
 123                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 124         return 0;
 125     }
 126
 127     return 0;
 128 }
 129
 130 static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
 131                                   uint64_t val64, unsigned int size)
 132 {
 133     STM32F2XXUsartState *s = opaque;
 134     uint32_t value = val64;
 135     unsigned char ch;
 136
 137     DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
 138
 139     switch (addr) {
 140     case USART_SR:
 141         if (value <= 0x3FF) {
 142             /* I/O being synchronous, TXE is always set. In addition, it may
 143                only be set by hardware, so keep it set here. */
 144             s->usart_sr = value | USART_SR_TXE;
 145         } else {
 146             s->usart_sr &= value;
 147         }
 148         if (!(s->usart_sr & USART_SR_RXNE)) {
 149             qemu_set_irq(s->irq, 0);
 150         }
 151         return;
 152     case USART_DR:
 153         if (value < 0xF000) {
 154             ch = value;
 155             /* XXX this blocks entire thread. Rewrite to use
 156              * qemu_chr_fe_write and background I/O callbacks */
 157             qemu_chr_fe_write_all(&s->chr, &ch, 1);
 158             /* XXX I/O are currently synchronous, making it impossible for
 159                software to observe transient states where TXE or TC aren't
 160                set. Unlike TXE however, which is read-only, software may
 161                clear TC by writing 0 to the SR register, so set it again
 162                on each write. */
 163             s->usart_sr |= USART_SR_TC;
 164         }
 165         return;
 166     case USART_BRR:
 167         s->usart_brr = value;
 168         return;
 169     case USART_CR1:
 170         s->usart_cr1 = value;
 171             if (s->usart_cr1 & USART_CR1_RXNEIE &&
 172                 s->usart_sr & USART_SR_RXNE) {
 173                 qemu_set_irq(s->irq, 1);
 174             }
 175         return;
 176     case USART_CR2:
 177         s->usart_cr2 = value;
 178         return;
 179     case USART_CR3:
 180         s->usart_cr3 = value;
 181         return;
 182     case USART_GTPR:
 183         s->usart_gtpr = value;
 184         return;
 185     default:
 186         qemu_log_mask(LOG_GUEST_ERROR,
 187                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 188     }
 189 }
 190
 191 static const MemoryRegionOps stm32f2xx_usart_ops = {
 192     .read = stm32f2xx_usart_read,
 193     .write = stm32f2xx_usart_write,
 194     .endianness = DEVICE_NATIVE_ENDIAN,
 195 };
 196
 197 static Property stm32f2xx_usart_properties[] = {
 198     DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr),
 199     DEFINE_PROP_END_OF_LIST(),
 200 };
 201
 202 static void stm32f2xx_usart_init(Object *obj)
 203 {
 204     STM32F2XXUsartState *s = STM32F2XX_USART(obj);
 205
 206     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 207
 208     memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
 209                           TYPE_STM32F2XX_USART, 0x400);
 210     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 211 }
 212
 213 static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp)
 214 {
 215     STM32F2XXUsartState *s = STM32F2XX_USART(dev);
 216
 217     qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive,
 218                              stm32f2xx_usart_receive, NULL, NULL,
 219                              s, NULL, true);
 220 }
 221
 222 static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
 223 {
 224     DeviceClass *dc = DEVICE_CLASS(klass);
 225
 226     dc->reset = stm32f2xx_usart_reset;
 227     device_class_set_props(dc, stm32f2xx_usart_properties);
 228     dc->realize = stm32f2xx_usart_realize;
 229 }
 230
 231 static const TypeInfo stm32f2xx_usart_info = {
 232     .name          = TYPE_STM32F2XX_USART,
 233     .parent        = TYPE_SYS_BUS_DEVICE,
 234     .instance_size = sizeof(STM32F2XXUsartState),
 235     .instance_init = stm32f2xx_usart_init,
 236     .class_init    = stm32f2xx_usart_class_init,
 237 };
 238
 239 static void stm32f2xx_usart_register_types(void)
 240 {
 241     type_register_static(&stm32f2xx_usart_info);
 242 }
 243
 244 type_init(stm32f2xx_usart_register_types)