hw/i2c/smbus_ich9.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
   6  *               VA Linux Systems Japan K.K.
   7  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, see <http://www.gnu.org/licenses/>
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qemu/range.h"
  25 #include "hw/i2c/pm_smbus.h"
  26 #include "hw/pci/pci.h"
  27 #include "migration/vmstate.h"
  28 #include "qemu/module.h"
  29
  30 #include "hw/southbridge/ich9.h"
  31 #include "qom/object.h"
  32 #include "hw/acpi/acpi_aml_interface.h"
  33
  34 OBJECT_DECLARE_SIMPLE_TYPE(ICH9SMBState, ICH9_SMB_DEVICE)
  35
  36 struct ICH9SMBState {
  37     PCIDevice dev;
  38
  39     bool irq_enabled;
  40
  41     PMSMBus smb;
  42 };
  43
  44 static bool ich9_vmstate_need_smbus(void *opaque, int version_id)
  45 {
  46     return pm_smbus_vmstate_needed();
  47 }
  48
  49 static const VMStateDescription vmstate_ich9_smbus = {
  50     .name = "ich9_smb",
  51     .version_id = 1,
  52     .minimum_version_id = 1,
  53     .fields = (VMStateField[]) {
  54         VMSTATE_PCI_DEVICE(dev, ICH9SMBState),
  55         VMSTATE_BOOL_TEST(irq_enabled, ICH9SMBState, ich9_vmstate_need_smbus),
  56         VMSTATE_STRUCT_TEST(smb, ICH9SMBState, ich9_vmstate_need_smbus, 1,
  57                             pmsmb_vmstate, PMSMBus),
  58         VMSTATE_END_OF_LIST()
  59     }
  60 };
  61
  62 static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
  63                                     uint32_t val, int len)
  64 {
  65     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
  66
  67     pci_default_write_config(d, address, val, len);
  68     if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) {
  69         uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
  70         if (hostc & ICH9_SMB_HOSTC_HST_EN) {
  71             memory_region_set_enabled(&s->smb.io, true);
  72         } else {
  73             memory_region_set_enabled(&s->smb.io, false);
  74         }
  75         s->smb.i2c_enable = (hostc & ICH9_SMB_HOSTC_I2C_EN) != 0;
  76         if (hostc & ICH9_SMB_HOSTC_SSRESET) {
  77             s->smb.reset(&s->smb);
  78             s->dev.config[ICH9_SMB_HOSTC] &= ~ICH9_SMB_HOSTC_SSRESET;
  79         }
  80     }
  81 }
  82
  83 static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
  84 {
  85     ICH9SMBState *s = pmsmb->opaque;
  86
  87     if (enabled == s->irq_enabled) {
  88         return;
  89     }
  90
  91     s->irq_enabled = enabled;
  92     pci_set_irq(&s->dev, enabled);
  93 }
  94
  95 static void ich9_smbus_realize(PCIDevice *d, Error **errp)
  96 {
  97     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
  98
  99     /* TODO? D31IP.SMIP in chipset configuration space */
 100     pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
 101
 102     pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
 103     /* TODO bar0, bar1: 64bit BAR support*/
 104
 105     pm_smbus_init(&d->qdev, &s->smb, false);
 106     pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
 107                      &s->smb.io);
 108
 109     s->smb.set_irq = ich9_smb_set_irq;
 110     s->smb.opaque = s;
 111 }
 112
 113 static void build_ich9_smb_aml(AcpiDevAmlIf *adev, Aml *scope)
 114 {
 115     ICH9SMBState *s = ICH9_SMB_DEVICE(adev);
 116     BusState *bus = BUS(s->smb.smbus);
 117
 118     qbus_build_aml(bus, scope);
 119 }
 120
 121 static void ich9_smb_class_init(ObjectClass *klass, void *data)
 122 {
 123     DeviceClass *dc = DEVICE_CLASS(klass);
 124     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 125     AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 126
 127     k->vendor_id = PCI_VENDOR_ID_INTEL;
 128     k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
 129     k->revision = ICH9_A2_SMB_REVISION;
 130     k->class_id = PCI_CLASS_SERIAL_SMBUS;
 131     dc->vmsd = &vmstate_ich9_smbus;
 132     dc->desc = "ICH9 SMBUS Bridge";
 133     k->realize = ich9_smbus_realize;
 134     k->config_write = ich9_smbus_write_config;
 135     /*
 136      * Reason: part of ICH9 southbridge, needs to be wired up by
 137      * pc_q35_init()
 138      */
 139     dc->user_creatable = false;
 140     adevc->build_dev_aml = build_ich9_smb_aml;
 141 }
 142
 143 static const TypeInfo ich9_smb_info = {
 144     .name   = TYPE_ICH9_SMB_DEVICE,
 145     .parent = TYPE_PCI_DEVICE,
 146     .instance_size = sizeof(ICH9SMBState),
 147     .class_init = ich9_smb_class_init,
 148     .interfaces = (InterfaceInfo[]) {
 149         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 150         { TYPE_ACPI_DEV_AML_IF },
 151         { },
 152     },
 153 };
 154
 155 static void ich9_smb_register(void)
 156 {
 157     type_register_static(&ich9_smb_info);
 158 }
 159
 160 type_init(ich9_smb_register);