hw/intc/xilinx_intc.c

   1 /*
   2  * QEMU Xilinx OPB Interrupt Controller.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "qemu/module.h"
  28 #include "hw/irq.h"
  29 #include "hw/qdev-properties.h"
  30 #include "qom/object.h"
  31
  32 #define D(x)
  33
  34 #define R_ISR       0
  35 #define R_IPR       1
  36 #define R_IER       2
  37 #define R_IAR       3
  38 #define R_SIE       4
  39 #define R_CIE       5
  40 #define R_IVR       6
  41 #define R_MER       7
  42 #define R_MAX       8
  43
  44 #define TYPE_XILINX_INTC "xlnx.xps-intc"
  45 typedef struct XpsIntc XpsIntc;
  46 DECLARE_INSTANCE_CHECKER(XpsIntc, XILINX_INTC, TYPE_XILINX_INTC)
  47
  48 struct XpsIntc
  49 {
  50     SysBusDevice parent_obj;
  51
  52     MemoryRegion mmio;
  53     qemu_irq parent_irq;
  54
  55     /* Configuration reg chosen at synthesis-time. QEMU populates
  56        the bits at board-setup.  */
  57     uint32_t c_kind_of_intr;
  58
  59     /* Runtime control registers.  */
  60     uint32_t regs[R_MAX];
  61     /* state of the interrupt input pins */
  62     uint32_t irq_pin_state;
  63 };
  64
  65 static void update_irq(XpsIntc *p)
  66 {
  67     uint32_t i;
  68
  69     /* level triggered interrupt */
  70     if (p->regs[R_MER] & 2) {
  71         p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr;
  72     }
  73
  74     /* Update the pending register.  */
  75     p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER];
  76
  77     /* Update the vector register.  */
  78     for (i = 0; i < 32; i++) {
  79         if (p->regs[R_IPR] & (1U << i)) {
  80             break;
  81         }
  82     }
  83     if (i == 32)
  84         i = ~0;
  85
  86     p->regs[R_IVR] = i;
  87     qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
  88 }
  89
  90 static uint64_t pic_read(void *opaque, hwaddr addr, unsigned int size)
  91 {
  92     XpsIntc *p = opaque;
  93     uint32_t r = 0;
  94
  95     addr >>= 2;
  96     switch (addr)
  97     {
  98         default:
  99             if (addr < ARRAY_SIZE(p->regs))
 100                 r = p->regs[addr];
 101             break;
 102
 103     }
 104     D(printf("%s %x=%x\n", __func__, addr * 4, r));
 105     return r;
 106 }
 107
 108 static void pic_write(void *opaque, hwaddr addr,
 109                       uint64_t val64, unsigned int size)
 110 {
 111     XpsIntc *p = opaque;
 112     uint32_t value = val64;
 113
 114     addr >>= 2;
 115     D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
 116     switch (addr)
 117     {
 118         case R_IAR:
 119             p->regs[R_ISR] &= ~value; /* ACK.  */
 120             break;
 121         case R_SIE:
 122             p->regs[R_IER] |= value;  /* Atomic set ie.  */
 123             break;
 124         case R_CIE:
 125             p->regs[R_IER] &= ~value; /* Atomic clear ie.  */
 126             break;
 127         case R_MER:
 128             p->regs[R_MER] = value & 0x3;
 129             break;
 130         case R_ISR:
 131             if ((p->regs[R_MER] & 2)) {
 132                 break;
 133             }
 134             /* fallthrough */
 135         default:
 136             if (addr < ARRAY_SIZE(p->regs))
 137                 p->regs[addr] = value;
 138             break;
 139     }
 140     update_irq(p);
 141 }
 142
 143 static const MemoryRegionOps pic_ops = {
 144     .read = pic_read,
 145     .write = pic_write,
 146     .endianness = DEVICE_NATIVE_ENDIAN,
 147     .valid = {
 148         .min_access_size = 4,
 149         .max_access_size = 4
 150     }
 151 };
 152
 153 static void irq_handler(void *opaque, int irq, int level)
 154 {
 155     XpsIntc *p = opaque;
 156
 157     /* edge triggered interrupt */
 158     if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
 159         p->regs[R_ISR] |= (level << irq);
 160     }
 161
 162     p->irq_pin_state &= ~(1 << irq);
 163     p->irq_pin_state |= level << irq;
 164     update_irq(p);
 165 }
 166
 167 static void xilinx_intc_init(Object *obj)
 168 {
 169     XpsIntc *p = XILINX_INTC(obj);
 170
 171     qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
 172     sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
 173
 174     memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc",
 175                           R_MAX * 4);
 176     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
 177 }
 178
 179 static Property xilinx_intc_properties[] = {
 180     DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
 181     DEFINE_PROP_END_OF_LIST(),
 182 };
 183
 184 static void xilinx_intc_class_init(ObjectClass *klass, void *data)
 185 {
 186     DeviceClass *dc = DEVICE_CLASS(klass);
 187
 188     device_class_set_props(dc, xilinx_intc_properties);
 189 }
 190
 191 static const TypeInfo xilinx_intc_info = {
 192     .name          = TYPE_XILINX_INTC,
 193     .parent        = TYPE_SYS_BUS_DEVICE,
 194     .instance_size = sizeof(XpsIntc),
 195     .instance_init = xilinx_intc_init,
 196     .class_init    = xilinx_intc_class_init,
 197 };
 198
 199 static void xilinx_intc_register_types(void)
 200 {
 201     type_register_static(&xilinx_intc_info);
 202 }
 203
 204 type_init(xilinx_intc_register_types)