2 * QEMU Firmware configuration device emulation
4 * Copyright (c) 2008 Gleb Natapov
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/datadir.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/dma.h"
29 #include "sysemu/reset.h"
30 #include "hw/boards.h"
31 #include "hw/nvram/fw_cfg.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/sysbus.h"
34 #include "migration/qemu-file-types.h"
35 #include "migration/vmstate.h"
37 #include "qemu/error-report.h"
38 #include "qemu/option.h"
39 #include "qemu/config-file.h"
40 #include "qemu/cutils.h"
41 #include "qapi/error.h"
42 #include "hw/acpi/aml-build.h"
43 #include "hw/pci/pci_bus.h"
44 #include "hw/loader.h"
46 #define FW_CFG_FILE_SLOTS_DFLT 0x20
48 /* FW_CFG_VERSION bits */
49 #define FW_CFG_VERSION 0x01
50 #define FW_CFG_VERSION_DMA 0x02
52 /* FW_CFG_DMA_CONTROL bits */
53 #define FW_CFG_DMA_CTL_ERROR 0x01
54 #define FW_CFG_DMA_CTL_READ 0x02
55 #define FW_CFG_DMA_CTL_SKIP 0x04
56 #define FW_CFG_DMA_CTL_SELECT 0x08
57 #define FW_CFG_DMA_CTL_WRITE 0x10
59 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
65 void *callback_opaque
;
66 FWCfgCallback select_cb
;
67 FWCfgWriteCallback write_cb
;
73 * @key: The uint16 selector key.
75 * Returns: The stringified name if the selector refers to a well-known
76 * numerically defined item, or NULL on key lookup failure.
78 static const char *key_name(uint16_t key
)
80 static const char *fw_cfg_wellknown_keys
[FW_CFG_FILE_FIRST
] = {
81 [FW_CFG_SIGNATURE
] = "signature",
83 [FW_CFG_UUID
] = "uuid",
84 [FW_CFG_RAM_SIZE
] = "ram_size",
85 [FW_CFG_NOGRAPHIC
] = "nographic",
86 [FW_CFG_NB_CPUS
] = "nb_cpus",
87 [FW_CFG_MACHINE_ID
] = "machine_id",
88 [FW_CFG_KERNEL_ADDR
] = "kernel_addr",
89 [FW_CFG_KERNEL_SIZE
] = "kernel_size",
90 [FW_CFG_KERNEL_CMDLINE
] = "kernel_cmdline",
91 [FW_CFG_INITRD_ADDR
] = "initrd_addr",
92 [FW_CFG_INITRD_SIZE
] = "initdr_size",
93 [FW_CFG_BOOT_DEVICE
] = "boot_device",
94 [FW_CFG_NUMA
] = "numa",
95 [FW_CFG_BOOT_MENU
] = "boot_menu",
96 [FW_CFG_MAX_CPUS
] = "max_cpus",
97 [FW_CFG_KERNEL_ENTRY
] = "kernel_entry",
98 [FW_CFG_KERNEL_DATA
] = "kernel_data",
99 [FW_CFG_INITRD_DATA
] = "initrd_data",
100 [FW_CFG_CMDLINE_ADDR
] = "cmdline_addr",
101 [FW_CFG_CMDLINE_SIZE
] = "cmdline_size",
102 [FW_CFG_CMDLINE_DATA
] = "cmdline_data",
103 [FW_CFG_SETUP_ADDR
] = "setup_addr",
104 [FW_CFG_SETUP_SIZE
] = "setup_size",
105 [FW_CFG_SETUP_DATA
] = "setup_data",
106 [FW_CFG_FILE_DIR
] = "file_dir",
109 if (key
& FW_CFG_ARCH_LOCAL
) {
110 return fw_cfg_arch_key_name(key
);
112 if (key
< FW_CFG_FILE_FIRST
) {
113 return fw_cfg_wellknown_keys
[key
];
119 static inline const char *trace_key_name(uint16_t key
)
121 const char *name
= key_name(key
);
123 return name
? name
: "unknown";
129 static char *read_splashfile(char *filename
, gsize
*file_sizep
,
135 unsigned int filehead
;
138 if (!g_file_get_contents(filename
, &content
, file_sizep
, &err
)) {
139 error_report("failed to read splash file '%s': %s",
140 filename
, err
->message
);
145 /* check file size */
146 if (*file_sizep
< 30) {
151 filehead
= lduw_le_p(content
);
152 if (filehead
== 0xd8ff) {
153 file_type
= JPG_FILE
;
154 } else if (filehead
== 0x4d42) {
155 file_type
= BMP_FILE
;
161 if (file_type
== BMP_FILE
) {
162 bmp_bpp
= lduw_le_p(&content
[28]);
169 *file_typep
= file_type
;
174 error_report("splash file '%s' format not recognized; must be JPEG "
175 "or 24 bit BMP", filename
);
180 static void fw_cfg_bootsplash(FWCfgState
*s
)
182 char *filename
, *file_data
;
186 /* insert splash time if user configurated */
187 if (current_machine
->boot_config
.has_splash_time
) {
188 int64_t bst_val
= current_machine
->boot_config
.splash_time
;
191 /* validate the input */
192 if (bst_val
< 0 || bst_val
> 0xffff) {
193 error_report("splash-time is invalid,"
194 "it should be a value between 0 and 65535");
197 /* use little endian format */
198 bst_le16
= cpu_to_le16(bst_val
);
199 fw_cfg_add_file(s
, "etc/boot-menu-wait",
200 g_memdup(&bst_le16
, sizeof bst_le16
), sizeof bst_le16
);
203 /* insert splash file if user configurated */
204 if (current_machine
->boot_config
.splash
) {
205 const char *boot_splash_filename
= current_machine
->boot_config
.splash
;
206 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, boot_splash_filename
);
207 if (filename
== NULL
) {
208 error_report("failed to find file '%s'", boot_splash_filename
);
212 /* loading file data */
213 file_data
= read_splashfile(filename
, &file_size
, &file_type
);
214 if (file_data
== NULL
) {
218 g_free(boot_splash_filedata
);
219 boot_splash_filedata
= (uint8_t *)file_data
;
222 if (file_type
== JPG_FILE
) {
223 fw_cfg_add_file(s
, "bootsplash.jpg",
224 boot_splash_filedata
, file_size
);
226 fw_cfg_add_file(s
, "bootsplash.bmp",
227 boot_splash_filedata
, file_size
);
233 static void fw_cfg_reboot(FWCfgState
*s
)
235 uint64_t rt_val
= -1;
238 if (current_machine
->boot_config
.has_reboot_timeout
) {
239 rt_val
= current_machine
->boot_config
.reboot_timeout
;
241 /* validate the input */
242 if (rt_val
> 0xffff && rt_val
!= (uint64_t)-1) {
243 error_report("reboot timeout is invalid,"
244 "it should be a value between -1 and 65535");
249 rt_le32
= cpu_to_le32(rt_val
);
250 fw_cfg_add_file(s
, "etc/boot-fail-wait", g_memdup(&rt_le32
, 4), 4);
253 static void fw_cfg_write(FWCfgState
*s
, uint8_t value
)
255 /* nothing, write support removed in QEMU v2.4+ */
258 static inline uint16_t fw_cfg_file_slots(const FWCfgState
*s
)
260 return s
->file_slots
;
263 /* Note: this function returns an exclusive limit. */
264 static inline uint32_t fw_cfg_max_entry(const FWCfgState
*s
)
266 return FW_CFG_FILE_FIRST
+ fw_cfg_file_slots(s
);
269 static int fw_cfg_select(FWCfgState
*s
, uint16_t key
)
275 if ((key
& FW_CFG_ENTRY_MASK
) >= fw_cfg_max_entry(s
)) {
276 s
->cur_entry
= FW_CFG_INVALID
;
281 /* entry successfully selected, now run callback if present */
282 arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
283 e
= &s
->entries
[arch
][key
& FW_CFG_ENTRY_MASK
];
285 e
->select_cb(e
->callback_opaque
);
289 trace_fw_cfg_select(s
, key
, trace_key_name(key
), ret
);
293 static uint64_t fw_cfg_data_read(void *opaque
, hwaddr addr
, unsigned size
)
295 FWCfgState
*s
= opaque
;
296 int arch
= !!(s
->cur_entry
& FW_CFG_ARCH_LOCAL
);
297 FWCfgEntry
*e
= (s
->cur_entry
== FW_CFG_INVALID
) ? NULL
:
298 &s
->entries
[arch
][s
->cur_entry
& FW_CFG_ENTRY_MASK
];
301 assert(size
> 0 && size
<= sizeof(value
));
302 if (s
->cur_entry
!= FW_CFG_INVALID
&& e
->data
&& s
->cur_offset
< e
->len
) {
303 /* The least significant 'size' bytes of the return value are
304 * expected to contain a string preserving portion of the item
305 * data, padded with zeros on the right in case we run out early.
306 * In technical terms, we're composing the host-endian representation
307 * of the big endian interpretation of the fw_cfg string.
310 value
= (value
<< 8) | e
->data
[s
->cur_offset
++];
311 } while (--size
&& s
->cur_offset
< e
->len
);
312 /* If size is still not zero, we *did* run out early, so continue
313 * left-shifting, to add the appropriate number of padding zeros
319 trace_fw_cfg_read(s
, value
);
323 static void fw_cfg_data_mem_write(void *opaque
, hwaddr addr
,
324 uint64_t value
, unsigned size
)
326 FWCfgState
*s
= opaque
;
330 fw_cfg_write(s
, value
>> (8 * --i
));
334 static void fw_cfg_dma_transfer(FWCfgState
*s
)
340 int read
= 0, write
= 0;
343 /* Reset the address before the next access */
344 dma_addr
= s
->dma_addr
;
347 if (dma_memory_read(s
->dma_as
, dma_addr
,
348 &dma
, sizeof(dma
), MEMTXATTRS_UNSPECIFIED
)) {
349 stl_be_dma(s
->dma_as
, dma_addr
+ offsetof(FWCfgDmaAccess
, control
),
350 FW_CFG_DMA_CTL_ERROR
, MEMTXATTRS_UNSPECIFIED
);
354 dma
.address
= be64_to_cpu(dma
.address
);
355 dma
.length
= be32_to_cpu(dma
.length
);
356 dma
.control
= be32_to_cpu(dma
.control
);
358 if (dma
.control
& FW_CFG_DMA_CTL_SELECT
) {
359 fw_cfg_select(s
, dma
.control
>> 16);
362 arch
= !!(s
->cur_entry
& FW_CFG_ARCH_LOCAL
);
363 e
= (s
->cur_entry
== FW_CFG_INVALID
) ? NULL
:
364 &s
->entries
[arch
][s
->cur_entry
& FW_CFG_ENTRY_MASK
];
366 if (dma
.control
& FW_CFG_DMA_CTL_READ
) {
369 } else if (dma
.control
& FW_CFG_DMA_CTL_WRITE
) {
372 } else if (dma
.control
& FW_CFG_DMA_CTL_SKIP
) {
381 while (dma
.length
> 0 && !(dma
.control
& FW_CFG_DMA_CTL_ERROR
)) {
382 if (s
->cur_entry
== FW_CFG_INVALID
|| !e
->data
||
383 s
->cur_offset
>= e
->len
) {
386 /* If the access is not a read access, it will be a skip access,
390 if (dma_memory_set(s
->dma_as
, dma
.address
, 0, len
,
391 MEMTXATTRS_UNSPECIFIED
)) {
392 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
396 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
399 if (dma
.length
<= (e
->len
- s
->cur_offset
)) {
402 len
= (e
->len
- s
->cur_offset
);
405 /* If the access is not a read access, it will be a skip access,
409 if (dma_memory_write(s
->dma_as
, dma
.address
,
410 &e
->data
[s
->cur_offset
], len
,
411 MEMTXATTRS_UNSPECIFIED
)) {
412 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
416 if (!e
->allow_write
||
418 dma_memory_read(s
->dma_as
, dma
.address
,
419 &e
->data
[s
->cur_offset
], len
,
420 MEMTXATTRS_UNSPECIFIED
)) {
421 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
422 } else if (e
->write_cb
) {
423 e
->write_cb(e
->callback_opaque
, s
->cur_offset
, len
);
427 s
->cur_offset
+= len
;
435 stl_be_dma(s
->dma_as
, dma_addr
+ offsetof(FWCfgDmaAccess
, control
),
436 dma
.control
, MEMTXATTRS_UNSPECIFIED
);
438 trace_fw_cfg_read(s
, 0);
441 static uint64_t fw_cfg_dma_mem_read(void *opaque
, hwaddr addr
,
444 /* Return a signature value (and handle various read sizes) */
445 return extract64(FW_CFG_DMA_SIGNATURE
, (8 - addr
- size
) * 8, size
* 8);
448 static void fw_cfg_dma_mem_write(void *opaque
, hwaddr addr
,
449 uint64_t value
, unsigned size
)
451 FWCfgState
*s
= opaque
;
455 /* FWCfgDmaAccess high address */
456 s
->dma_addr
= value
<< 32;
457 } else if (addr
== 4) {
458 /* FWCfgDmaAccess low address */
459 s
->dma_addr
|= value
;
460 fw_cfg_dma_transfer(s
);
462 } else if (size
== 8 && addr
== 0) {
464 fw_cfg_dma_transfer(s
);
468 static bool fw_cfg_dma_mem_valid(void *opaque
, hwaddr addr
,
469 unsigned size
, bool is_write
,
472 return !is_write
|| ((size
== 4 && (addr
== 0 || addr
== 4)) ||
473 (size
== 8 && addr
== 0));
476 static bool fw_cfg_data_mem_valid(void *opaque
, hwaddr addr
,
477 unsigned size
, bool is_write
,
483 static uint64_t fw_cfg_ctl_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
488 static void fw_cfg_ctl_mem_write(void *opaque
, hwaddr addr
,
489 uint64_t value
, unsigned size
)
491 fw_cfg_select(opaque
, (uint16_t)value
);
494 static bool fw_cfg_ctl_mem_valid(void *opaque
, hwaddr addr
,
495 unsigned size
, bool is_write
,
498 return is_write
&& size
== 2;
501 static void fw_cfg_comb_write(void *opaque
, hwaddr addr
,
502 uint64_t value
, unsigned size
)
506 fw_cfg_write(opaque
, (uint8_t)value
);
509 fw_cfg_select(opaque
, (uint16_t)value
);
514 static bool fw_cfg_comb_valid(void *opaque
, hwaddr addr
,
515 unsigned size
, bool is_write
,
518 return (size
== 1) || (is_write
&& size
== 2);
521 static const MemoryRegionOps fw_cfg_ctl_mem_ops
= {
522 .read
= fw_cfg_ctl_mem_read
,
523 .write
= fw_cfg_ctl_mem_write
,
524 .endianness
= DEVICE_BIG_ENDIAN
,
525 .valid
.accepts
= fw_cfg_ctl_mem_valid
,
528 static const MemoryRegionOps fw_cfg_data_mem_ops
= {
529 .read
= fw_cfg_data_read
,
530 .write
= fw_cfg_data_mem_write
,
531 .endianness
= DEVICE_BIG_ENDIAN
,
533 .min_access_size
= 1,
534 .max_access_size
= 1,
535 .accepts
= fw_cfg_data_mem_valid
,
539 static const MemoryRegionOps fw_cfg_comb_mem_ops
= {
540 .read
= fw_cfg_data_read
,
541 .write
= fw_cfg_comb_write
,
542 .endianness
= DEVICE_LITTLE_ENDIAN
,
543 .valid
.accepts
= fw_cfg_comb_valid
,
546 static const MemoryRegionOps fw_cfg_dma_mem_ops
= {
547 .read
= fw_cfg_dma_mem_read
,
548 .write
= fw_cfg_dma_mem_write
,
549 .endianness
= DEVICE_BIG_ENDIAN
,
550 .valid
.accepts
= fw_cfg_dma_mem_valid
,
551 .valid
.max_access_size
= 8,
552 .impl
.max_access_size
= 8,
555 static void fw_cfg_reset(DeviceState
*d
)
557 FWCfgState
*s
= FW_CFG(d
);
559 /* we never register a read callback for FW_CFG_SIGNATURE */
560 fw_cfg_select(s
, FW_CFG_SIGNATURE
);
563 /* Save restore 32 bit int as uint16_t
564 This is a Big hack, but it is how the old state did it.
565 Or we broke compatibility in the state, or we can't use struct tm
568 static int get_uint32_as_uint16(QEMUFile
*f
, void *pv
, size_t size
,
569 const VMStateField
*field
)
572 *v
= qemu_get_be16(f
);
576 static int put_unused(QEMUFile
*f
, void *pv
, size_t size
,
577 const VMStateField
*field
, JSONWriter
*vmdesc
)
579 fprintf(stderr
, "uint32_as_uint16 is only used for backward compatibility.\n");
580 fprintf(stderr
, "This functions shouldn't be called.\n");
585 static const VMStateInfo vmstate_hack_uint32_as_uint16
= {
586 .name
= "int32_as_uint16",
587 .get
= get_uint32_as_uint16
,
591 #define VMSTATE_UINT16_HACK(_f, _s, _t) \
592 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
595 static bool is_version_1(void *opaque
, int version_id
)
597 return version_id
== 1;
600 bool fw_cfg_dma_enabled(void *opaque
)
602 FWCfgState
*s
= opaque
;
604 return s
->dma_enabled
;
607 static bool fw_cfg_acpi_mr_restore(void *opaque
)
609 FWCfgState
*s
= opaque
;
612 mr_aligned
= QEMU_IS_ALIGNED(s
->table_mr_size
, qemu_real_host_page_size()) &&
613 QEMU_IS_ALIGNED(s
->linker_mr_size
, qemu_real_host_page_size()) &&
614 QEMU_IS_ALIGNED(s
->rsdp_mr_size
, qemu_real_host_page_size());
615 return s
->acpi_mr_restore
&& !mr_aligned
;
618 static void fw_cfg_update_mr(FWCfgState
*s
, uint16_t key
, size_t size
)
622 int arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
625 key
&= FW_CFG_ENTRY_MASK
;
626 assert(key
< fw_cfg_max_entry(s
));
628 ptr
= s
->entries
[arch
][key
].data
;
629 mr
= memory_region_from_host(ptr
, &offset
);
631 memory_region_ram_resize(mr
, size
, &error_abort
);
634 static int fw_cfg_acpi_mr_restore_post_load(void *opaque
, int version_id
)
636 FWCfgState
*s
= opaque
;
641 index
= be32_to_cpu(s
->files
->count
);
643 for (i
= 0; i
< index
; i
++) {
644 if (!strcmp(s
->files
->f
[i
].name
, ACPI_BUILD_TABLE_FILE
)) {
645 fw_cfg_update_mr(s
, FW_CFG_FILE_FIRST
+ i
, s
->table_mr_size
);
646 } else if (!strcmp(s
->files
->f
[i
].name
, ACPI_BUILD_LOADER_FILE
)) {
647 fw_cfg_update_mr(s
, FW_CFG_FILE_FIRST
+ i
, s
->linker_mr_size
);
648 } else if (!strcmp(s
->files
->f
[i
].name
, ACPI_BUILD_RSDP_FILE
)) {
649 fw_cfg_update_mr(s
, FW_CFG_FILE_FIRST
+ i
, s
->rsdp_mr_size
);
656 static const VMStateDescription vmstate_fw_cfg_dma
= {
657 .name
= "fw_cfg/dma",
658 .needed
= fw_cfg_dma_enabled
,
659 .fields
= (VMStateField
[]) {
660 VMSTATE_UINT64(dma_addr
, FWCfgState
),
661 VMSTATE_END_OF_LIST()
665 static const VMStateDescription vmstate_fw_cfg_acpi_mr
= {
666 .name
= "fw_cfg/acpi_mr",
668 .minimum_version_id
= 1,
669 .needed
= fw_cfg_acpi_mr_restore
,
670 .post_load
= fw_cfg_acpi_mr_restore_post_load
,
671 .fields
= (VMStateField
[]) {
672 VMSTATE_UINT64(table_mr_size
, FWCfgState
),
673 VMSTATE_UINT64(linker_mr_size
, FWCfgState
),
674 VMSTATE_UINT64(rsdp_mr_size
, FWCfgState
),
675 VMSTATE_END_OF_LIST()
679 static const VMStateDescription vmstate_fw_cfg
= {
682 .minimum_version_id
= 1,
683 .fields
= (VMStateField
[]) {
684 VMSTATE_UINT16(cur_entry
, FWCfgState
),
685 VMSTATE_UINT16_HACK(cur_offset
, FWCfgState
, is_version_1
),
686 VMSTATE_UINT32_V(cur_offset
, FWCfgState
, 2),
687 VMSTATE_END_OF_LIST()
689 .subsections
= (const VMStateDescription
*[]) {
691 &vmstate_fw_cfg_acpi_mr
,
696 static void fw_cfg_add_bytes_callback(FWCfgState
*s
, uint16_t key
,
697 FWCfgCallback select_cb
,
698 FWCfgWriteCallback write_cb
,
699 void *callback_opaque
,
700 void *data
, size_t len
,
703 int arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
705 key
&= FW_CFG_ENTRY_MASK
;
707 assert(key
< fw_cfg_max_entry(s
) && len
< UINT32_MAX
);
708 assert(s
->entries
[arch
][key
].data
== NULL
); /* avoid key conflict */
710 s
->entries
[arch
][key
].data
= data
;
711 s
->entries
[arch
][key
].len
= (uint32_t)len
;
712 s
->entries
[arch
][key
].select_cb
= select_cb
;
713 s
->entries
[arch
][key
].write_cb
= write_cb
;
714 s
->entries
[arch
][key
].callback_opaque
= callback_opaque
;
715 s
->entries
[arch
][key
].allow_write
= !read_only
;
718 static void *fw_cfg_modify_bytes_read(FWCfgState
*s
, uint16_t key
,
719 void *data
, size_t len
)
722 int arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
724 key
&= FW_CFG_ENTRY_MASK
;
726 assert(key
< fw_cfg_max_entry(s
) && len
< UINT32_MAX
);
728 /* return the old data to the function caller, avoid memory leak */
729 ptr
= s
->entries
[arch
][key
].data
;
730 s
->entries
[arch
][key
].data
= data
;
731 s
->entries
[arch
][key
].len
= len
;
732 s
->entries
[arch
][key
].callback_opaque
= NULL
;
733 s
->entries
[arch
][key
].allow_write
= false;
738 void fw_cfg_add_bytes(FWCfgState
*s
, uint16_t key
, void *data
, size_t len
)
740 trace_fw_cfg_add_bytes(key
, trace_key_name(key
), len
);
741 fw_cfg_add_bytes_callback(s
, key
, NULL
, NULL
, NULL
, data
, len
, true);
744 void fw_cfg_add_string(FWCfgState
*s
, uint16_t key
, const char *value
)
746 size_t sz
= strlen(value
) + 1;
748 trace_fw_cfg_add_string(key
, trace_key_name(key
), value
);
749 fw_cfg_add_bytes(s
, key
, g_memdup(value
, sz
), sz
);
752 void fw_cfg_modify_string(FWCfgState
*s
, uint16_t key
, const char *value
)
754 size_t sz
= strlen(value
) + 1;
757 old
= fw_cfg_modify_bytes_read(s
, key
, g_memdup(value
, sz
), sz
);
761 void fw_cfg_add_i16(FWCfgState
*s
, uint16_t key
, uint16_t value
)
765 copy
= g_malloc(sizeof(value
));
766 *copy
= cpu_to_le16(value
);
767 trace_fw_cfg_add_i16(key
, trace_key_name(key
), value
);
768 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
771 void fw_cfg_modify_i16(FWCfgState
*s
, uint16_t key
, uint16_t value
)
773 uint16_t *copy
, *old
;
775 copy
= g_malloc(sizeof(value
));
776 *copy
= cpu_to_le16(value
);
777 old
= fw_cfg_modify_bytes_read(s
, key
, copy
, sizeof(value
));
781 void fw_cfg_add_i32(FWCfgState
*s
, uint16_t key
, uint32_t value
)
785 copy
= g_malloc(sizeof(value
));
786 *copy
= cpu_to_le32(value
);
787 trace_fw_cfg_add_i32(key
, trace_key_name(key
), value
);
788 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
791 void fw_cfg_modify_i32(FWCfgState
*s
, uint16_t key
, uint32_t value
)
793 uint32_t *copy
, *old
;
795 copy
= g_malloc(sizeof(value
));
796 *copy
= cpu_to_le32(value
);
797 old
= fw_cfg_modify_bytes_read(s
, key
, copy
, sizeof(value
));
801 void fw_cfg_add_i64(FWCfgState
*s
, uint16_t key
, uint64_t value
)
805 copy
= g_malloc(sizeof(value
));
806 *copy
= cpu_to_le64(value
);
807 trace_fw_cfg_add_i64(key
, trace_key_name(key
), value
);
808 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
811 void fw_cfg_modify_i64(FWCfgState
*s
, uint16_t key
, uint64_t value
)
813 uint64_t *copy
, *old
;
815 copy
= g_malloc(sizeof(value
));
816 *copy
= cpu_to_le64(value
);
817 old
= fw_cfg_modify_bytes_read(s
, key
, copy
, sizeof(value
));
821 void fw_cfg_set_order_override(FWCfgState
*s
, int order
)
823 assert(s
->fw_cfg_order_override
== 0);
824 s
->fw_cfg_order_override
= order
;
827 void fw_cfg_reset_order_override(FWCfgState
*s
)
829 assert(s
->fw_cfg_order_override
!= 0);
830 s
->fw_cfg_order_override
= 0;
834 * This is the legacy order list. For legacy systems, files are in
835 * the fw_cfg in the order defined below, by the "order" value. Note
836 * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a
837 * specific area, but there may be more than one and they occur in the
838 * order that the user specifies them on the command line. Those are
839 * handled in a special manner, using the order override above.
841 * For non-legacy, the files are sorted by filename to avoid this kind
842 * of complexity in the future.
844 * This is only for x86, other arches don't implement versioning so
845 * they won't set legacy mode.
851 { "etc/boot-menu-wait", 10 },
852 { "bootsplash.jpg", 11 },
853 { "bootsplash.bmp", 12 },
854 { "etc/boot-fail-wait", 15 },
855 { "etc/smbios/smbios-tables", 20 },
856 { "etc/smbios/smbios-anchor", 30 },
858 { "etc/reserved-memory-end", 50 },
859 { "genroms/kvmvapic.bin", 55 },
860 { "genroms/linuxboot.bin", 60 },
861 { }, /* VGA ROMs from pc_vga_init come here, 70. */
862 { }, /* NIC option ROMs from pc_nic_init come here, 80. */
863 { "etc/system-states", 90 },
864 { }, /* User ROMs come here, 100. */
865 { }, /* Device FW comes here, 110. */
866 { "etc/extra-pci-roots", 120 },
867 { "etc/acpi/tables", 130 },
868 { "etc/table-loader", 140 },
869 { "etc/tpm/log", 150 },
870 { "etc/acpi/rsdp", 160 },
871 { "bootorder", 170 },
872 { "etc/msr_feature_control", 180 },
874 #define FW_CFG_ORDER_OVERRIDE_LAST 200
878 * Any sub-page size update to these table MRs will be lost during migration,
879 * as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path.
880 * In order to avoid the inconsistency in sizes save them seperately and
881 * migrate over in vmstate post_load().
883 static void fw_cfg_acpi_mr_save(FWCfgState
*s
, const char *filename
, size_t len
)
885 if (!strcmp(filename
, ACPI_BUILD_TABLE_FILE
)) {
886 s
->table_mr_size
= len
;
887 } else if (!strcmp(filename
, ACPI_BUILD_LOADER_FILE
)) {
888 s
->linker_mr_size
= len
;
889 } else if (!strcmp(filename
, ACPI_BUILD_RSDP_FILE
)) {
890 s
->rsdp_mr_size
= len
;
894 static int get_fw_cfg_order(FWCfgState
*s
, const char *name
)
898 if (s
->fw_cfg_order_override
> 0) {
899 return s
->fw_cfg_order_override
;
902 for (i
= 0; i
< ARRAY_SIZE(fw_cfg_order
); i
++) {
903 if (fw_cfg_order
[i
].name
== NULL
) {
907 if (strcmp(name
, fw_cfg_order
[i
].name
) == 0) {
908 return fw_cfg_order
[i
].order
;
912 /* Stick unknown stuff at the end. */
913 warn_report("Unknown firmware file in legacy mode: %s", name
);
914 return FW_CFG_ORDER_OVERRIDE_LAST
;
917 void fw_cfg_add_file_callback(FWCfgState
*s
, const char *filename
,
918 FWCfgCallback select_cb
,
919 FWCfgWriteCallback write_cb
,
920 void *callback_opaque
,
921 void *data
, size_t len
, bool read_only
)
925 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
929 dsize
= sizeof(uint32_t) + sizeof(FWCfgFile
) * fw_cfg_file_slots(s
);
930 s
->files
= g_malloc0(dsize
);
931 fw_cfg_add_bytes(s
, FW_CFG_FILE_DIR
, s
->files
, dsize
);
934 count
= be32_to_cpu(s
->files
->count
);
935 assert(count
< fw_cfg_file_slots(s
));
937 /* Find the insertion point. */
938 if (mc
->legacy_fw_cfg_order
) {
940 * Sort by order. For files with the same order, we keep them
941 * in the sequence in which they were added.
943 order
= get_fw_cfg_order(s
, filename
);
945 index
> 0 && order
< s
->entry_order
[index
- 1];
948 /* Sort by file name. */
950 index
> 0 && strcmp(filename
, s
->files
->f
[index
- 1].name
) < 0;
955 * Move all the entries from the index point and after down one
956 * to create a slot for the new entry. Because calculations are
957 * being done with the index, make it so that "i" is the current
958 * index and "i - 1" is the one being copied from, thus the
959 * unusual start and end in the for statement.
961 for (i
= count
; i
> index
; i
--) {
962 s
->files
->f
[i
] = s
->files
->f
[i
- 1];
963 s
->files
->f
[i
].select
= cpu_to_be16(FW_CFG_FILE_FIRST
+ i
);
964 s
->entries
[0][FW_CFG_FILE_FIRST
+ i
] =
965 s
->entries
[0][FW_CFG_FILE_FIRST
+ i
- 1];
966 s
->entry_order
[i
] = s
->entry_order
[i
- 1];
969 memset(&s
->files
->f
[index
], 0, sizeof(FWCfgFile
));
970 memset(&s
->entries
[0][FW_CFG_FILE_FIRST
+ index
], 0, sizeof(FWCfgEntry
));
972 pstrcpy(s
->files
->f
[index
].name
, sizeof(s
->files
->f
[index
].name
), filename
);
973 for (i
= 0; i
<= count
; i
++) {
975 strcmp(s
->files
->f
[index
].name
, s
->files
->f
[i
].name
) == 0) {
976 error_report("duplicate fw_cfg file name: %s",
977 s
->files
->f
[index
].name
);
982 fw_cfg_add_bytes_callback(s
, FW_CFG_FILE_FIRST
+ index
,
984 callback_opaque
, data
, len
,
987 s
->files
->f
[index
].size
= cpu_to_be32(len
);
988 s
->files
->f
[index
].select
= cpu_to_be16(FW_CFG_FILE_FIRST
+ index
);
989 s
->entry_order
[index
] = order
;
990 trace_fw_cfg_add_file(s
, index
, s
->files
->f
[index
].name
, len
);
992 s
->files
->count
= cpu_to_be32(count
+1);
993 fw_cfg_acpi_mr_save(s
, filename
, len
);
996 void fw_cfg_add_file(FWCfgState
*s
, const char *filename
,
997 void *data
, size_t len
)
999 fw_cfg_add_file_callback(s
, filename
, NULL
, NULL
, NULL
, data
, len
, true);
1002 void *fw_cfg_modify_file(FWCfgState
*s
, const char *filename
,
1003 void *data
, size_t len
)
1010 index
= be32_to_cpu(s
->files
->count
);
1012 for (i
= 0; i
< index
; i
++) {
1013 if (strcmp(filename
, s
->files
->f
[i
].name
) == 0) {
1014 ptr
= fw_cfg_modify_bytes_read(s
, FW_CFG_FILE_FIRST
+ i
,
1016 s
->files
->f
[i
].size
= cpu_to_be32(len
);
1017 fw_cfg_acpi_mr_save(s
, filename
, len
);
1022 assert(index
< fw_cfg_file_slots(s
));
1025 fw_cfg_add_file_callback(s
, filename
, NULL
, NULL
, NULL
, data
, len
, true);
1029 bool fw_cfg_add_from_generator(FWCfgState
*s
, const char *filename
,
1030 const char *gen_id
, Error
**errp
)
1032 FWCfgDataGeneratorClass
*klass
;
1037 obj
= object_resolve_path_component(object_get_objects_root(), gen_id
);
1039 error_setg(errp
, "Cannot find object ID '%s'", gen_id
);
1042 if (!object_dynamic_cast(obj
, TYPE_FW_CFG_DATA_GENERATOR_INTERFACE
)) {
1043 error_setg(errp
, "Object ID '%s' is not a '%s' subclass",
1044 gen_id
, TYPE_FW_CFG_DATA_GENERATOR_INTERFACE
);
1047 klass
= FW_CFG_DATA_GENERATOR_GET_CLASS(obj
);
1048 array
= klass
->get_data(obj
, errp
);
1053 fw_cfg_add_file(s
, filename
, g_byte_array_free(array
, FALSE
), size
);
1058 void fw_cfg_add_extra_pci_roots(PCIBus
*bus
, FWCfgState
*s
)
1060 int extra_hosts
= 0;
1066 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1067 /* look for expander root buses */
1068 if (pci_bus_is_root(bus
)) {
1073 if (extra_hosts
&& s
) {
1074 uint64_t *val
= g_malloc(sizeof(*val
));
1075 *val
= cpu_to_le64(extra_hosts
);
1076 fw_cfg_add_file(s
, "etc/extra-pci-roots", val
, sizeof(*val
));
1080 static void fw_cfg_machine_reset(void *opaque
)
1082 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
1083 FWCfgState
*s
= opaque
;
1088 buf
= get_boot_devices_list(&len
);
1089 ptr
= fw_cfg_modify_file(s
, "bootorder", (uint8_t *)buf
, len
);
1092 if (!mc
->legacy_fw_cfg_order
) {
1093 buf
= get_boot_devices_lchs_list(&len
);
1094 ptr
= fw_cfg_modify_file(s
, "bios-geometry", (uint8_t *)buf
, len
);
1099 static void fw_cfg_machine_ready(struct Notifier
*n
, void *data
)
1101 FWCfgState
*s
= container_of(n
, FWCfgState
, machine_ready
);
1102 qemu_register_reset(fw_cfg_machine_reset
, s
);
1105 static Property fw_cfg_properties
[] = {
1106 DEFINE_PROP_BOOL("acpi-mr-restore", FWCfgState
, acpi_mr_restore
, true),
1107 DEFINE_PROP_END_OF_LIST(),
1110 static void fw_cfg_common_realize(DeviceState
*dev
, Error
**errp
)
1112 FWCfgState
*s
= FW_CFG(dev
);
1113 MachineState
*machine
= MACHINE(qdev_get_machine());
1114 uint32_t version
= FW_CFG_VERSION
;
1116 if (!fw_cfg_find()) {
1117 error_setg(errp
, "at most one %s device is permitted", TYPE_FW_CFG
);
1121 fw_cfg_add_bytes(s
, FW_CFG_SIGNATURE
, (char *)"QEMU", 4);
1122 fw_cfg_add_bytes(s
, FW_CFG_UUID
, &qemu_uuid
, 16);
1123 fw_cfg_add_i16(s
, FW_CFG_NOGRAPHIC
, (uint16_t)!machine
->enable_graphics
);
1124 fw_cfg_add_i16(s
, FW_CFG_BOOT_MENU
, (uint16_t)(machine
->boot_config
.has_menu
&& machine
->boot_config
.menu
));
1125 fw_cfg_bootsplash(s
);
1128 if (s
->dma_enabled
) {
1129 version
|= FW_CFG_VERSION_DMA
;
1132 fw_cfg_add_i32(s
, FW_CFG_ID
, version
);
1134 s
->machine_ready
.notify
= fw_cfg_machine_ready
;
1135 qemu_add_machine_init_done_notifier(&s
->machine_ready
);
1138 FWCfgState
*fw_cfg_init_io_dma(uint32_t iobase
, uint32_t dma_iobase
,
1139 AddressSpace
*dma_as
)
1145 bool dma_requested
= dma_iobase
&& dma_as
;
1147 dev
= qdev_new(TYPE_FW_CFG_IO
);
1148 if (!dma_requested
) {
1149 qdev_prop_set_bit(dev
, "dma_enabled", false);
1152 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG
,
1155 sbd
= SYS_BUS_DEVICE(dev
);
1156 sysbus_realize_and_unref(sbd
, &error_fatal
);
1157 ios
= FW_CFG_IO(dev
);
1158 sysbus_add_io(sbd
, iobase
, &ios
->comb_iomem
);
1162 if (s
->dma_enabled
) {
1163 /* 64 bits for the address field */
1166 sysbus_add_io(sbd
, dma_iobase
, &s
->dma_iomem
);
1172 FWCfgState
*fw_cfg_init_io(uint32_t iobase
)
1174 return fw_cfg_init_io_dma(iobase
, 0, NULL
);
1177 FWCfgState
*fw_cfg_init_mem_wide(hwaddr ctl_addr
,
1178 hwaddr data_addr
, uint32_t data_width
,
1179 hwaddr dma_addr
, AddressSpace
*dma_as
)
1184 bool dma_requested
= dma_addr
&& dma_as
;
1186 dev
= qdev_new(TYPE_FW_CFG_MEM
);
1187 qdev_prop_set_uint32(dev
, "data_width", data_width
);
1188 if (!dma_requested
) {
1189 qdev_prop_set_bit(dev
, "dma_enabled", false);
1192 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG
,
1195 sbd
= SYS_BUS_DEVICE(dev
);
1196 sysbus_realize_and_unref(sbd
, &error_fatal
);
1197 sysbus_mmio_map(sbd
, 0, ctl_addr
);
1198 sysbus_mmio_map(sbd
, 1, data_addr
);
1202 if (s
->dma_enabled
) {
1205 sysbus_mmio_map(sbd
, 2, dma_addr
);
1211 FWCfgState
*fw_cfg_init_mem(hwaddr ctl_addr
, hwaddr data_addr
)
1213 return fw_cfg_init_mem_wide(ctl_addr
, data_addr
,
1214 fw_cfg_data_mem_ops
.valid
.max_access_size
,
1219 FWCfgState
*fw_cfg_find(void)
1221 /* Returns NULL unless there is exactly one fw_cfg device */
1222 return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG
, NULL
));
1225 void load_image_to_fw_cfg(FWCfgState
*fw_cfg
, uint16_t size_key
,
1226 uint16_t data_key
, const char *image_name
,
1227 bool try_decompress
)
1232 if (image_name
== NULL
) {
1236 if (try_decompress
) {
1237 size
= load_image_gzipped_buffer(image_name
,
1238 LOAD_IMAGE_MAX_GUNZIP_BYTES
, &data
);
1241 if (size
== (size_t)-1) {
1245 if (!g_file_get_contents(image_name
, &contents
, &length
, NULL
)) {
1246 error_report("failed to load \"%s\"", image_name
);
1250 data
= (uint8_t *)contents
;
1253 fw_cfg_add_i32(fw_cfg
, size_key
, size
);
1254 fw_cfg_add_bytes(fw_cfg
, data_key
, data
, size
);
1257 static void fw_cfg_class_init(ObjectClass
*klass
, void *data
)
1259 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1261 dc
->reset
= fw_cfg_reset
;
1262 dc
->vmsd
= &vmstate_fw_cfg
;
1264 device_class_set_props(dc
, fw_cfg_properties
);
1267 static const TypeInfo fw_cfg_info
= {
1268 .name
= TYPE_FW_CFG
,
1269 .parent
= TYPE_SYS_BUS_DEVICE
,
1271 .instance_size
= sizeof(FWCfgState
),
1272 .class_init
= fw_cfg_class_init
,
1275 static void fw_cfg_file_slots_allocate(FWCfgState
*s
, Error
**errp
)
1277 uint16_t file_slots_max
;
1279 if (fw_cfg_file_slots(s
) < FW_CFG_FILE_SLOTS_MIN
) {
1280 error_setg(errp
, "\"file_slots\" must be at least 0x%x",
1281 FW_CFG_FILE_SLOTS_MIN
);
1285 /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value
1286 * that we permit. The actual (exclusive) value coming from the
1287 * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */
1288 file_slots_max
= (UINT16_MAX
& FW_CFG_ENTRY_MASK
) - FW_CFG_FILE_FIRST
+ 1;
1289 if (fw_cfg_file_slots(s
) > file_slots_max
) {
1290 error_setg(errp
, "\"file_slots\" must not exceed 0x%" PRIx16
,
1295 s
->entries
[0] = g_new0(FWCfgEntry
, fw_cfg_max_entry(s
));
1296 s
->entries
[1] = g_new0(FWCfgEntry
, fw_cfg_max_entry(s
));
1297 s
->entry_order
= g_new0(int, fw_cfg_max_entry(s
));
1300 static Property fw_cfg_io_properties
[] = {
1301 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState
, parent_obj
.dma_enabled
,
1303 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState
, parent_obj
.file_slots
,
1304 FW_CFG_FILE_SLOTS_DFLT
),
1305 DEFINE_PROP_END_OF_LIST(),
1308 static void fw_cfg_io_realize(DeviceState
*dev
, Error
**errp
)
1311 FWCfgIoState
*s
= FW_CFG_IO(dev
);
1313 fw_cfg_file_slots_allocate(FW_CFG(s
), errp
);
1318 /* when using port i/o, the 8-bit data register ALWAYS overlaps
1319 * with half of the 16-bit control register. Hence, the total size
1320 * of the i/o region used is FW_CFG_CTL_SIZE */
1321 memory_region_init_io(&s
->comb_iomem
, OBJECT(s
), &fw_cfg_comb_mem_ops
,
1322 FW_CFG(s
), "fwcfg", FW_CFG_CTL_SIZE
);
1324 if (FW_CFG(s
)->dma_enabled
) {
1325 memory_region_init_io(&FW_CFG(s
)->dma_iomem
, OBJECT(s
),
1326 &fw_cfg_dma_mem_ops
, FW_CFG(s
), "fwcfg.dma",
1327 sizeof(dma_addr_t
));
1330 fw_cfg_common_realize(dev
, errp
);
1333 static void fw_cfg_io_class_init(ObjectClass
*klass
, void *data
)
1335 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1337 dc
->realize
= fw_cfg_io_realize
;
1338 device_class_set_props(dc
, fw_cfg_io_properties
);
1341 static const TypeInfo fw_cfg_io_info
= {
1342 .name
= TYPE_FW_CFG_IO
,
1343 .parent
= TYPE_FW_CFG
,
1344 .instance_size
= sizeof(FWCfgIoState
),
1345 .class_init
= fw_cfg_io_class_init
,
1349 static Property fw_cfg_mem_properties
[] = {
1350 DEFINE_PROP_UINT32("data_width", FWCfgMemState
, data_width
, -1),
1351 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState
, parent_obj
.dma_enabled
,
1353 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState
, parent_obj
.file_slots
,
1354 FW_CFG_FILE_SLOTS_DFLT
),
1355 DEFINE_PROP_END_OF_LIST(),
1358 static void fw_cfg_mem_realize(DeviceState
*dev
, Error
**errp
)
1361 FWCfgMemState
*s
= FW_CFG_MEM(dev
);
1362 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1363 const MemoryRegionOps
*data_ops
= &fw_cfg_data_mem_ops
;
1365 fw_cfg_file_slots_allocate(FW_CFG(s
), errp
);
1370 memory_region_init_io(&s
->ctl_iomem
, OBJECT(s
), &fw_cfg_ctl_mem_ops
,
1371 FW_CFG(s
), "fwcfg.ctl", FW_CFG_CTL_SIZE
);
1372 sysbus_init_mmio(sbd
, &s
->ctl_iomem
);
1374 if (s
->data_width
> data_ops
->valid
.max_access_size
) {
1375 s
->wide_data_ops
= *data_ops
;
1377 s
->wide_data_ops
.valid
.max_access_size
= s
->data_width
;
1378 s
->wide_data_ops
.impl
.max_access_size
= s
->data_width
;
1379 data_ops
= &s
->wide_data_ops
;
1381 memory_region_init_io(&s
->data_iomem
, OBJECT(s
), data_ops
, FW_CFG(s
),
1382 "fwcfg.data", data_ops
->valid
.max_access_size
);
1383 sysbus_init_mmio(sbd
, &s
->data_iomem
);
1385 if (FW_CFG(s
)->dma_enabled
) {
1386 memory_region_init_io(&FW_CFG(s
)->dma_iomem
, OBJECT(s
),
1387 &fw_cfg_dma_mem_ops
, FW_CFG(s
), "fwcfg.dma",
1388 sizeof(dma_addr_t
));
1389 sysbus_init_mmio(sbd
, &FW_CFG(s
)->dma_iomem
);
1392 fw_cfg_common_realize(dev
, errp
);
1395 static void fw_cfg_mem_class_init(ObjectClass
*klass
, void *data
)
1397 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1399 dc
->realize
= fw_cfg_mem_realize
;
1400 device_class_set_props(dc
, fw_cfg_mem_properties
);
1403 static const TypeInfo fw_cfg_mem_info
= {
1404 .name
= TYPE_FW_CFG_MEM
,
1405 .parent
= TYPE_FW_CFG
,
1406 .instance_size
= sizeof(FWCfgMemState
),
1407 .class_init
= fw_cfg_mem_class_init
,
1410 static void fw_cfg_register_types(void)
1412 type_register_static(&fw_cfg_info
);
1413 type_register_static(&fw_cfg_io_info
);
1414 type_register_static(&fw_cfg_mem_info
);
1417 type_init(fw_cfg_register_types
)