hw/pci-bridge/xio3130_downstream.c

   1 /*
   2  * x3130_downstream.c
   3  * TI X3130 pci express downstream port switch
   4  *
   5  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/pci/pci_ids.h"
  24 #include "hw/pci/msi.h"
  25 #include "hw/pci/pcie.h"
  26 #include "hw/pci/pcie_port.h"
  27 #include "hw/qdev-properties.h"
  28 #include "migration/vmstate.h"
  29 #include "qapi/error.h"
  30 #include "qemu/module.h"
  31 #include "hw/pci-bridge/xio3130_downstream.h"
  32
  33 #define PCI_DEVICE_ID_TI_XIO3130D       0x8233  /* downstream port */
  34 #define XIO3130_REVISION                0x1
  35 #define XIO3130_MSI_OFFSET              0x70
  36 #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  37 #define XIO3130_MSI_NR_VECTOR           1
  38 #define XIO3130_SSVID_OFFSET            0x80
  39 #define XIO3130_SSVID_SVID              0
  40 #define XIO3130_SSVID_SSID              0
  41 #define XIO3130_EXP_OFFSET              0x90
  42 #define XIO3130_AER_OFFSET              0x100
  43
  44 static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
  45                                          uint32_t val, int len)
  46 {
  47     uint16_t slt_ctl, slt_sta;
  48
  49     pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
  50     pci_bridge_write_config(d, address, val, len);
  51     pcie_cap_flr_write_config(d, address, val, len);
  52     pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
  53     pcie_aer_write_config(d, address, val, len);
  54 }
  55
  56 static void xio3130_downstream_reset(DeviceState *qdev)
  57 {
  58     PCIDevice *d = PCI_DEVICE(qdev);
  59
  60     pcie_cap_deverr_reset(d);
  61     pcie_cap_slot_reset(d);
  62     pcie_cap_arifwd_reset(d);
  63     pci_bridge_reset(qdev);
  64 }
  65
  66 static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
  67 {
  68     PCIEPort *p = PCIE_PORT(d);
  69     PCIESlot *s = PCIE_SLOT(d);
  70     int rc;
  71
  72     pci_bridge_initfn(d, TYPE_PCIE_BUS);
  73     pcie_port_init_reg(d);
  74
  75     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  76                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  77                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
  78                   errp);
  79     if (rc < 0) {
  80         assert(rc == -ENOTSUP);
  81         goto err_bridge;
  82     }
  83
  84     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  85                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
  86                                errp);
  87     if (rc < 0) {
  88         goto err_msi;
  89     }
  90
  91     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
  92                        p->port, errp);
  93     if (rc < 0) {
  94         goto err_msi;
  95     }
  96     pcie_cap_flr_init(d);
  97     pcie_cap_deverr_init(d);
  98     pcie_cap_slot_init(d, s);
  99     pcie_cap_arifwd_init(d);
 100
 101     pcie_chassis_create(s->chassis);
 102     rc = pcie_chassis_add_slot(s);
 103     if (rc < 0) {
 104         error_setg(errp, "Can't add chassis slot, error %d", rc);
 105         goto err_pcie_cap;
 106     }
 107
 108     rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
 109                        PCI_ERR_SIZEOF, errp);
 110     if (rc < 0) {
 111         goto err;
 112     }
 113
 114     return;
 115
 116 err:
 117     pcie_chassis_del_slot(s);
 118 err_pcie_cap:
 119     pcie_cap_exit(d);
 120 err_msi:
 121     msi_uninit(d);
 122 err_bridge:
 123     pci_bridge_exitfn(d);
 124 }
 125
 126 static void xio3130_downstream_exitfn(PCIDevice *d)
 127 {
 128     PCIESlot *s = PCIE_SLOT(d);
 129
 130     pcie_aer_exit(d);
 131     pcie_chassis_del_slot(s);
 132     pcie_cap_exit(d);
 133     msi_uninit(d);
 134     pci_bridge_exitfn(d);
 135 }
 136
 137 static Property xio3130_downstream_props[] = {
 138     DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
 139                     QEMU_PCIE_SLTCAP_PCP_BITNR, true),
 140     DEFINE_PROP_END_OF_LIST()
 141 };
 142
 143 static const VMStateDescription vmstate_xio3130_downstream = {
 144     .name = "xio3130-express-downstream-port",
 145     .priority = MIG_PRI_PCI_BUS,
 146     .version_id = 1,
 147     .minimum_version_id = 1,
 148     .post_load = pcie_cap_slot_post_load,
 149     .fields = (VMStateField[]) {
 150         VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
 151         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
 152                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
 153         VMSTATE_END_OF_LIST()
 154     }
 155 };
 156
 157 static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
 158 {
 159     DeviceClass *dc = DEVICE_CLASS(klass);
 160     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 161
 162     k->config_write = xio3130_downstream_write_config;
 163     k->realize = xio3130_downstream_realize;
 164     k->exit = xio3130_downstream_exitfn;
 165     k->vendor_id = PCI_VENDOR_ID_TI;
 166     k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
 167     k->revision = XIO3130_REVISION;
 168     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 169     dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
 170     dc->reset = xio3130_downstream_reset;
 171     dc->vmsd = &vmstate_xio3130_downstream;
 172     device_class_set_props(dc, xio3130_downstream_props);
 173 }
 174
 175 static const TypeInfo xio3130_downstream_info = {
 176     .name          = TYPE_XIO3130_DOWNSTREAM,
 177     .parent        = TYPE_PCIE_SLOT,
 178     .class_init    = xio3130_downstream_class_init,
 179     .interfaces = (InterfaceInfo[]) {
 180         { INTERFACE_PCIE_DEVICE },
 181         { }
 182     },
 183 };
 184
 185 static void xio3130_downstream_register_types(void)
 186 {
 187     type_register_static(&xio3130_downstream_info);
 188 }
 189
 190 type_init(xio3130_downstream_register_types)