hw/sh4/sh7750_regs.h

   1 /*
   2  * SH-7750 memory-mapped registers
   3  * This file based on information provided in the following document:
   4  * "Hitachi SuperH (tm) RISC engine. SH7750 Series (SH7750, SH7750S)
   5  *  Hardware Manual"
   6  *  Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
   7  *
   8  * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
   9  * Author: Alexandra Kossovsky <sasha@oktet.ru>
  10  *         Victor V. Vengerov <vvv@oktet.ru>
  11  *
  12  * The license and distribution terms for this file may be
  13  * found in this file hereafter or at http://www.rtems.com/license/LICENSE.
  14  *
  15  *                       LICENSE INFORMATION
  16  *
  17  * RTEMS is free software; you can redistribute it and/or modify it under
  18  * terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2, or (at your option) any
  20  * later version.  RTEMS is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  23  * General Public License for more details. You should have received
  24  * a copy of the GNU General Public License along with RTEMS; see
  25  * file COPYING. If not, see <https://www.gnu.org/licenses/>.
  26  *
  27  * As a special exception, including RTEMS header files in a file,
  28  * instantiating RTEMS generics or templates, or linking other files
  29  * with RTEMS objects to produce an executable application, does not
  30  * by itself cause the resulting executable application to be covered
  31  * by the GNU General Public License. This exception does not
  32  * however invalidate any other reasons why the executable file might be
  33  * covered by the GNU Public License.
  34  *
  35  * @(#) sh7750_regs.h,v 1.2.4.1 2003/09/04 18:46:00 joel Exp
  36  */
  37
  38 #ifndef SH7750_REGS_H
  39 #define SH7750_REGS_H
  40
  41 /*
  42  * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address)  and
  43  * in 0x1f000000 - 0x1fffffff (area 7 address)
  44  */
  45 #define SH7750_P4_BASE       0xff000000 /* Accessible only in privileged mode */
  46 #define SH7750_A7_BASE       0x1f000000 /* Accessible only using TLB */
  47
  48 #define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))
  49 #define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))
  50
  51 /*
  52  * MMU Registers
  53  */
  54
  55 /* Page Table Entry High register - PTEH */
  56 #define SH7750_PTEH_REGOFS    0x000000  /* offset */
  57 #define SH7750_PTEH           SH7750_P4_REG32(SH7750_PTEH_REGOFS)
  58 #define SH7750_PTEH_A7        SH7750_A7_REG32(SH7750_PTEH_REGOFS)
  59 #define SH7750_PTEH_VPN       0xfffffd00 /* Virtual page number */
  60 #define SH7750_PTEH_VPN_S     10
  61 #define SH7750_PTEH_ASID      0x000000ff /* Address space identifier */
  62 #define SH7750_PTEH_ASID_S    0
  63
  64 /* Page Table Entry Low register - PTEL */
  65 #define SH7750_PTEL_REGOFS    0x000004  /* offset */
  66 #define SH7750_PTEL           SH7750_P4_REG32(SH7750_PTEL_REGOFS)
  67 #define SH7750_PTEL_A7        SH7750_A7_REG32(SH7750_PTEL_REGOFS)
  68 #define SH7750_PTEL_PPN       0x1ffffc00 /* Physical page number */
  69 #define SH7750_PTEL_PPN_S     10
  70 #define SH7750_PTEL_V         0x00000100 /* Validity (0-entry is invalid) */
  71 #define SH7750_PTEL_SZ1       0x00000080 /* Page size bit 1 */
  72 #define SH7750_PTEL_SZ0       0x00000010 /* Page size bit 0 */
  73 #define SH7750_PTEL_SZ_1KB    0x00000000 /*   1-kbyte page */
  74 #define SH7750_PTEL_SZ_4KB    0x00000010 /*   4-kbyte page */
  75 #define SH7750_PTEL_SZ_64KB   0x00000080 /*   64-kbyte page */
  76 #define SH7750_PTEL_SZ_1MB    0x00000090 /*   1-Mbyte page */
  77 #define SH7750_PTEL_PR        0x00000060 /* Protection Key Data */
  78 #define SH7750_PTEL_PR_ROPO   0x00000000 /*   read-only in priv mode */
  79 #define SH7750_PTEL_PR_RWPO   0x00000020 /*   read-write in priv mode */
  80 #define SH7750_PTEL_PR_ROPU   0x00000040 /*   read-only in priv or user mode */
  81 #define SH7750_PTEL_PR_RWPU   0x00000060 /*   read-write in priv or user mode */
  82 #define SH7750_PTEL_C         0x00000008 /* Cacheability */
  83                                          /*   (0 - page not cacheable) */
  84 #define SH7750_PTEL_D         0x00000004 /* Dirty bit (1 - write has been */
  85                                          /*   performed to a page) */
  86 #define SH7750_PTEL_SH        0x00000002 /* Share Status bit (1 - page are */
  87                                          /*   shared by processes) */
  88 #define SH7750_PTEL_WT        0x00000001 /* Write-through bit, specifies the */
  89                                          /*   cache write mode: */
  90                                          /*     0 - Copy-back mode */
  91                                          /*     1 - Write-through mode */
  92
  93 /* Page Table Entry Assistance register - PTEA */
  94 #define SH7750_PTEA_REGOFS    0x000034 /* offset */
  95 #define SH7750_PTEA           SH7750_P4_REG32(SH7750_PTEA_REGOFS)
  96 #define SH7750_PTEA_A7        SH7750_A7_REG32(SH7750_PTEA_REGOFS)
  97 #define SH7750_PTEA_TC        0x00000008 /* Timing Control bit */
  98                                          /*   0 - use area 5 wait states */
  99                                          /*   1 - use area 6 wait states */
 100 #define SH7750_PTEA_SA        0x00000007 /* Space Attribute bits: */
 101 #define SH7750_PTEA_SA_UNDEF  0x00000000 /*   0 - undefined */
 102 #define SH7750_PTEA_SA_IOVAR  0x00000001 /*   1 - variable-size I/O space */
 103 #define SH7750_PTEA_SA_IO8    0x00000002 /*   2 - 8-bit I/O space */
 104 #define SH7750_PTEA_SA_IO16   0x00000003 /*   3 - 16-bit I/O space */
 105 #define SH7750_PTEA_SA_CMEM8  0x00000004 /*   4 - 8-bit common memory space */
 106 #define SH7750_PTEA_SA_CMEM16 0x00000005 /*   5 - 16-bit common memory space */
 107 #define SH7750_PTEA_SA_AMEM8  0x00000006 /*   6 - 8-bit attr memory space */
 108 #define SH7750_PTEA_SA_AMEM16 0x00000007 /*   7 - 16-bit attr memory space */
 109
 110
 111 /* Translation table base register */
 112 #define SH7750_TTB_REGOFS     0x000008 /* offset */
 113 #define SH7750_TTB            SH7750_P4_REG32(SH7750_TTB_REGOFS)
 114 #define SH7750_TTB_A7         SH7750_A7_REG32(SH7750_TTB_REGOFS)
 115
 116 /* TLB exeption address register - TEA */
 117 #define SH7750_TEA_REGOFS     0x00000c /* offset */
 118 #define SH7750_TEA            SH7750_P4_REG32(SH7750_TEA_REGOFS)
 119 #define SH7750_TEA_A7         SH7750_A7_REG32(SH7750_TEA_REGOFS)
 120
 121 /* MMU control register - MMUCR */
 122 #define SH7750_MMUCR_REGOFS   0x000010 /* offset */
 123 #define SH7750_MMUCR          SH7750_P4_REG32(SH7750_MMUCR_REGOFS)
 124 #define SH7750_MMUCR_A7       SH7750_A7_REG32(SH7750_MMUCR_REGOFS)
 125 #define SH7750_MMUCR_AT       0x00000001 /* Address translation bit */
 126 #define SH7750_MMUCR_TI       0x00000004 /* TLB invalidate */
 127 #define SH7750_MMUCR_SV       0x00000100 /* Single Virtual Mode bit */
 128 #define SH7750_MMUCR_SQMD     0x00000200 /* Store Queue Mode bit */
 129 #define SH7750_MMUCR_URC      0x0000FC00 /* UTLB Replace Counter */
 130 #define SH7750_MMUCR_URC_S    10
 131 #define SH7750_MMUCR_URB      0x00FC0000 /* UTLB Replace Boundary */
 132 #define SH7750_MMUCR_URB_S    18
 133 #define SH7750_MMUCR_LRUI     0xFC000000 /* Least Recently Used ITLB */
 134 #define SH7750_MMUCR_LRUI_S   26
 135
 136
 137
 138
 139 /*
 140  * Cache registers
 141  *   IC -- instructions cache
 142  *   OC -- operand cache
 143  */
 144
 145 /* Cache Control Register - CCR */
 146 #define SH7750_CCR_REGOFS     0x00001c /* offset */
 147 #define SH7750_CCR            SH7750_P4_REG32(SH7750_CCR_REGOFS)
 148 #define SH7750_CCR_A7         SH7750_A7_REG32(SH7750_CCR_REGOFS)
 149
 150 #define SH7750_CCR_IIX      0x00008000 /* IC index enable bit */
 151 #define SH7750_CCR_ICI      0x00000800 /* IC invalidation bit: */
 152                                        /*  set it to clear IC */
 153 #define SH7750_CCR_ICE      0x00000100 /* IC enable bit */
 154 #define SH7750_CCR_OIX      0x00000080 /* OC index enable bit */
 155 #define SH7750_CCR_ORA      0x00000020 /* OC RAM enable bit */
 156                                        /*  if you set OCE = 0, */
 157                                        /*  you should set ORA = 0 */
 158 #define SH7750_CCR_OCI      0x00000008 /* OC invalidation bit */
 159 #define SH7750_CCR_CB       0x00000004 /* Copy-back bit for P1 area */
 160 #define SH7750_CCR_WT       0x00000002 /* Write-through bit for P0,U0,P3 area */
 161 #define SH7750_CCR_OCE      0x00000001 /* OC enable bit */
 162
 163 /* Queue address control register 0 - QACR0 */
 164 #define SH7750_QACR0_REGOFS   0x000038  /* offset */
 165 #define SH7750_QACR0          SH7750_P4_REG32(SH7750_QACR0_REGOFS)
 166 #define SH7750_QACR0_A7       SH7750_A7_REG32(SH7750_QACR0_REGOFS)
 167
 168 /* Queue address control register 1 - QACR1 */
 169 #define SH7750_QACR1_REGOFS   0x00003c /* offset */
 170 #define SH7750_QACR1          SH7750_P4_REG32(SH7750_QACR1_REGOFS)
 171 #define SH7750_QACR1_A7       SH7750_A7_REG32(SH7750_QACR1_REGOFS)
 172
 173
 174 /*
 175  * Exeption-related registers
 176  */
 177
 178 /* Immediate data for TRAPA instruction - TRA */
 179 #define SH7750_TRA_REGOFS     0x000020 /* offset */
 180 #define SH7750_TRA            SH7750_P4_REG32(SH7750_TRA_REGOFS)
 181 #define SH7750_TRA_A7         SH7750_A7_REG32(SH7750_TRA_REGOFS)
 182
 183 #define SH7750_TRA_IMM      0x000003fd /* Immediate data operand */
 184 #define SH7750_TRA_IMM_S    2
 185
 186 /* Exeption event register - EXPEVT */
 187 #define SH7750_EXPEVT_REGOFS  0x000024
 188 #define SH7750_EXPEVT         SH7750_P4_REG32(SH7750_EXPEVT_REGOFS)
 189 #define SH7750_EXPEVT_A7      SH7750_A7_REG32(SH7750_EXPEVT_REGOFS)
 190
 191 #define SH7750_EXPEVT_EX      0x00000fff /* Exeption code */
 192 #define SH7750_EXPEVT_EX_S    0
 193
 194 /* Interrupt event register */
 195 #define SH7750_INTEVT_REGOFS  0x000028
 196 #define SH7750_INTEVT         SH7750_P4_REG32(SH7750_INTEVT_REGOFS)
 197 #define SH7750_INTEVT_A7      SH7750_A7_REG32(SH7750_INTEVT_REGOFS)
 198 #define SH7750_INTEVT_EX    0x00000fff /* Exeption code */
 199 #define SH7750_INTEVT_EX_S  0
 200
 201 /*
 202  * Exception/interrupt codes
 203  */
 204 #define SH7750_EVT_TO_NUM(evt)  ((evt) >> 5)
 205
 206 /* Reset exception category */
 207 #define SH7750_EVT_POWER_ON_RST        0x000 /* Power-on reset */
 208 #define SH7750_EVT_MANUAL_RST          0x020 /* Manual reset */
 209 #define SH7750_EVT_TLB_MULT_HIT        0x140 /* TLB multiple-hit exception */
 210
 211 /* General exception category */
 212 #define SH7750_EVT_USER_BREAK          0x1E0 /* User break */
 213 #define SH7750_EVT_IADDR_ERR           0x0E0 /* Instruction address error */
 214 #define SH7750_EVT_TLB_READ_MISS       0x040 /* ITLB miss exception / */
 215                                              /*    DTLB miss exception (read) */
 216 #define SH7750_EVT_TLB_READ_PROTV      0x0A0 /* ITLB protection violation, */
 217                                              /* DTLB protection violation */
 218                                              /*    (read) */
 219 #define SH7750_EVT_ILLEGAL_INSTR       0x180 /* General Illegal Instruction */
 220                                              /*    exception */
 221 #define SH7750_EVT_SLOT_ILLEGAL_INSTR  0x1A0 /* Slot Illegal Instruction */
 222                                              /*    exception */
 223 #define SH7750_EVT_FPU_DISABLE         0x800 /* General FPU disable exception */
 224 #define SH7750_EVT_SLOT_FPU_DISABLE    0x820 /* Slot FPU disable exception */
 225 #define SH7750_EVT_DATA_READ_ERR       0x0E0 /* Data address error (read) */
 226 #define SH7750_EVT_DATA_WRITE_ERR      0x100 /* Data address error (write) */
 227 #define SH7750_EVT_DTLB_WRITE_MISS     0x060 /* DTLB miss exception (write) */
 228 #define SH7750_EVT_DTLB_WRITE_PROTV    0x0C0 /* DTLB protection violation */
 229                                              /*    exception (write) */
 230 #define SH7750_EVT_FPU_EXCEPTION       0x120 /* FPU exception */
 231 #define SH7750_EVT_INITIAL_PGWRITE     0x080 /* Initial Page Write exception */
 232 #define SH7750_EVT_TRAPA               0x160 /* Unconditional trap (TRAPA) */
 233
 234 /* Interrupt exception category */
 235 #define SH7750_EVT_NMI                 0x1C0 /* Non-maskable interrupt */
 236 #define SH7750_EVT_IRQ0                0x200 /* External Interrupt 0 */
 237 #define SH7750_EVT_IRQ1                0x220 /* External Interrupt 1 */
 238 #define SH7750_EVT_IRQ2                0x240 /* External Interrupt 2 */
 239 #define SH7750_EVT_IRQ3                0x260 /* External Interrupt 3 */
 240 #define SH7750_EVT_IRQ4                0x280 /* External Interrupt 4 */
 241 #define SH7750_EVT_IRQ5                0x2A0 /* External Interrupt 5 */
 242 #define SH7750_EVT_IRQ6                0x2C0 /* External Interrupt 6 */
 243 #define SH7750_EVT_IRQ7                0x2E0 /* External Interrupt 7 */
 244 #define SH7750_EVT_IRQ8                0x300 /* External Interrupt 8 */
 245 #define SH7750_EVT_IRQ9                0x320 /* External Interrupt 9 */
 246 #define SH7750_EVT_IRQA                0x340 /* External Interrupt A */
 247 #define SH7750_EVT_IRQB                0x360 /* External Interrupt B */
 248 #define SH7750_EVT_IRQC                0x380 /* External Interrupt C */
 249 #define SH7750_EVT_IRQD                0x3A0 /* External Interrupt D */
 250 #define SH7750_EVT_IRQE                0x3C0 /* External Interrupt E */
 251
 252 /* Peripheral Module Interrupts - Timer Unit (TMU) */
 253 #define SH7750_EVT_TUNI0               0x400 /* TMU Underflow Interrupt 0 */
 254 #define SH7750_EVT_TUNI1               0x420 /* TMU Underflow Interrupt 1 */
 255 #define SH7750_EVT_TUNI2               0x440 /* TMU Underflow Interrupt 2 */
 256 #define SH7750_EVT_TICPI2              0x460 /* TMU Input Capture Interrupt 2 */
 257
 258 /* Peripheral Module Interrupts - Real-Time Clock (RTC) */
 259 #define SH7750_EVT_RTC_ATI             0x480 /* Alarm Interrupt Request */
 260 #define SH7750_EVT_RTC_PRI             0x4A0 /* Periodic Interrupt Request */
 261 #define SH7750_EVT_RTC_CUI             0x4C0 /* Carry Interrupt Request */
 262
 263 /* Peripheral Module Interrupts - Serial Communication Interface (SCI) */
 264 #define SH7750_EVT_SCI_ERI             0x4E0 /* Receive Error */
 265 #define SH7750_EVT_SCI_RXI             0x500 /* Receive Data Register Full */
 266 #define SH7750_EVT_SCI_TXI             0x520 /* Transmit Data Register Empty */
 267 #define SH7750_EVT_SCI_TEI             0x540 /* Transmit End */
 268
 269 /* Peripheral Module Interrupts - Watchdog Timer (WDT) */
 270 #define SH7750_EVT_WDT_ITI             0x560 /* Interval Timer Interrupt */
 271                                              /*    (used when WDT operates in */
 272                                              /*    interval timer mode) */
 273
 274 /* Peripheral Module Interrupts - Memory Refresh Unit (REF) */
 275 #define SH7750_EVT_REF_RCMI            0x580 /* Compare-match Interrupt */
 276 #define SH7750_EVT_REF_ROVI            0x5A0 /* Refresh Counter Overflow */
 277                                              /*    interrupt */
 278
 279 /* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */
 280 #define SH7750_EVT_HUDI                0x600 /* UDI interrupt */
 281
 282 /* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */
 283 #define SH7750_EVT_GPIO                0x620 /* GPIO Interrupt */
 284
 285 /* Peripheral Module Interrupts - DMA Controller (DMAC) */
 286 #define SH7750_EVT_DMAC_DMTE0          0x640 /* DMAC 0 Transfer End Interrupt */
 287 #define SH7750_EVT_DMAC_DMTE1          0x660 /* DMAC 1 Transfer End Interrupt */
 288 #define SH7750_EVT_DMAC_DMTE2          0x680 /* DMAC 2 Transfer End Interrupt */
 289 #define SH7750_EVT_DMAC_DMTE3          0x6A0 /* DMAC 3 Transfer End Interrupt */
 290 #define SH7750_EVT_DMAC_DMAE           0x6C0 /* DMAC Address Error Interrupt */
 291
 292 /* Peripheral Module Interrupts Serial Communication Interface w/ FIFO (SCIF) */
 293 #define SH7750_EVT_SCIF_ERI            0x700 /* Receive Error */
 294 #define SH7750_EVT_SCIF_RXI            0x720 /* Receive FIFO Data Full or */
 295                                              /* Receive Data ready interrupt */
 296 #define SH7750_EVT_SCIF_BRI            0x740 /* Break or overrun error */
 297 #define SH7750_EVT_SCIF_TXI            0x760 /* Transmit FIFO Data Empty */
 298
 299 /*
 300  * Power Management
 301  */
 302 #define SH7750_STBCR_REGOFS   0xC00004 /* offset */
 303 #define SH7750_STBCR          SH7750_P4_REG32(SH7750_STBCR_REGOFS)
 304 #define SH7750_STBCR_A7       SH7750_A7_REG32(SH7750_STBCR_REGOFS)
 305
 306 #define SH7750_STBCR_STBY     0x80 /* Specifies a transition to standby mode: */
 307                                    /*   0 Transition to SLEEP mode on SLEEP */
 308                                    /*   1 Transition to STANDBY mode on SLEEP */
 309 #define SH7750_STBCR_PHZ      0x40 /* State of peripheral module pins in */
 310                                    /* standby mode: */
 311                                    /*   0 normal state */
 312                                    /*   1 high-impendance state */
 313
 314 #define SH7750_STBCR_PPU      0x20 /* Peripheral module pins pull-up controls */
 315 #define SH7750_STBCR_MSTP4    0x10 /* Stopping the clock supply to DMAC */
 316 #define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4
 317 #define SH7750_STBCR_MSTP3    0x08 /* Stopping the clock supply to SCIF */
 318 #define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3
 319 #define SH7750_STBCR_MSTP2    0x04 /* Stopping the clock supply to TMU */
 320 #define SH7750_STBCR_TMU_STP  SH7750_STBCR_MSTP2
 321 #define SH7750_STBCR_MSTP1    0x02 /* Stopping the clock supply to RTC */
 322 #define SH7750_STBCR_RTC_STP  SH7750_STBCR_MSTP1
 323 #define SH7750_STBCR_MSPT0    0x01 /* Stopping the clock supply to SCI */
 324 #define SH7750_STBCR_SCI_STP  SH7750_STBCR_MSTP0
 325
 326 #define SH7750_STBCR_STBY     0x80
 327
 328
 329 #define SH7750_STBCR2_REGOFS  0xC00010 /* offset */
 330 #define SH7750_STBCR2         SH7750_P4_REG32(SH7750_STBCR2_REGOFS)
 331 #define SH7750_STBCR2_A7      SH7750_A7_REG32(SH7750_STBCR2_REGOFS)
 332
 333 #define SH7750_STBCR2_DSLP    0x80 /* Specifies transition to deep sleep mode */
 334                                    /*   0 transition to sleep or standby mode */
 335                                    /*     as it is specified in STBY bit */
 336                                    /*   1 transition to deep sleep mode on */
 337                                    /*     execution of SLEEP instruction */
 338 #define SH7750_STBCR2_MSTP6   0x02 /* Stopping the clock supply to the */
 339                                    /*   Store Queue in the cache controller */
 340 #define SH7750_STBCR2_SQ_STP  SH7750_STBCR2_MSTP6
 341 #define SH7750_STBCR2_MSTP5   0x01 /* Stopping the clock supply to the  */
 342                                    /*   User Break Controller (UBC) */
 343 #define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5
 344
 345 /*
 346  * Clock Pulse Generator (CPG)
 347  */
 348 #define SH7750_FRQCR_REGOFS   0xC00000 /* offset */
 349 #define SH7750_FRQCR          SH7750_P4_REG32(SH7750_FRQCR_REGOFS)
 350 #define SH7750_FRQCR_A7       SH7750_A7_REG32(SH7750_FRQCR_REGOFS)
 351
 352 #define SH7750_FRQCR_CKOEN    0x0800 /* Clock Output Enable */
 353                                      /*    0 - CKIO pin goes to HiZ/pullup */
 354                                      /*    1 - Clock is output from CKIO */
 355 #define SH7750_FRQCR_PLL1EN   0x0400 /* PLL circuit 1 enable */
 356 #define SH7750_FRQCR_PLL2EN   0x0200 /* PLL circuit 2 enable */
 357
 358 #define SH7750_FRQCR_IFC      0x01C0 /* CPU clock frequency division ratio: */
 359 #define SH7750_FRQCR_IFCDIV1  0x0000 /*    0 - * 1 */
 360 #define SH7750_FRQCR_IFCDIV2  0x0040 /*    1 - * 1/2 */
 361 #define SH7750_FRQCR_IFCDIV3  0x0080 /*    2 - * 1/3 */
 362 #define SH7750_FRQCR_IFCDIV4  0x00C0 /*    3 - * 1/4 */
 363 #define SH7750_FRQCR_IFCDIV6  0x0100 /*    4 - * 1/6 */
 364 #define SH7750_FRQCR_IFCDIV8  0x0140 /*    5 - * 1/8 */
 365
 366 #define SH7750_FRQCR_BFC      0x0038 /* Bus clock frequency division ratio: */
 367 #define SH7750_FRQCR_BFCDIV1  0x0000 /*    0 - * 1 */
 368 #define SH7750_FRQCR_BFCDIV2  0x0008 /*    1 - * 1/2 */
 369 #define SH7750_FRQCR_BFCDIV3  0x0010 /*    2 - * 1/3 */
 370 #define SH7750_FRQCR_BFCDIV4  0x0018 /*    3 - * 1/4 */
 371 #define SH7750_FRQCR_BFCDIV6  0x0020 /*    4 - * 1/6 */
 372 #define SH7750_FRQCR_BFCDIV8  0x0028 /*    5 - * 1/8 */
 373
 374 #define SH7750_FRQCR_PFC      0x0007 /* Peripheral module clock frequency */
 375                                      /*    division ratio: */
 376 #define SH7750_FRQCR_PFCDIV2  0x0000 /*    0 - * 1/2 */
 377 #define SH7750_FRQCR_PFCDIV3  0x0001 /*    1 - * 1/3 */
 378 #define SH7750_FRQCR_PFCDIV4  0x0002 /*    2 - * 1/4 */
 379 #define SH7750_FRQCR_PFCDIV6  0x0003 /*    3 - * 1/6 */
 380 #define SH7750_FRQCR_PFCDIV8  0x0004 /*    4 - * 1/8 */
 381
 382 /*
 383  * Watchdog Timer (WDT)
 384  */
 385
 386 /* Watchdog Timer Counter register - WTCNT */
 387 #define SH7750_WTCNT_REGOFS   0xC00008 /* offset */
 388 #define SH7750_WTCNT          SH7750_P4_REG32(SH7750_WTCNT_REGOFS)
 389 #define SH7750_WTCNT_A7       SH7750_A7_REG32(SH7750_WTCNT_REGOFS)
 390 #define SH7750_WTCNT_KEY      0x5A00 /* When WTCNT byte register written, you */
 391                                      /* have to set the upper byte to 0x5A */
 392
 393 /* Watchdog Timer Control/Status register - WTCSR */
 394 #define SH7750_WTCSR_REGOFS   0xC0000C /* offset */
 395 #define SH7750_WTCSR          SH7750_P4_REG32(SH7750_WTCSR_REGOFS)
 396 #define SH7750_WTCSR_A7       SH7750_A7_REG32(SH7750_WTCSR_REGOFS)
 397 #define SH7750_WTCSR_KEY      0xA500 /* When WTCSR byte register written, you */
 398                                      /* have to set the upper byte to 0xA5 */
 399 #define SH7750_WTCSR_TME      0x80 /* Timer enable (1-upcount start) */
 400 #define SH7750_WTCSR_MODE     0x40 /* Timer Mode Select: */
 401 #define SH7750_WTCSR_MODE_WT  0x40 /*    Watchdog Timer Mode */
 402 #define SH7750_WTCSR_MODE_IT  0x00 /*    Interval Timer Mode */
 403 #define SH7750_WTCSR_RSTS     0x20 /* Reset Select: */
 404 #define SH7750_WTCSR_RST_MAN  0x20 /*    Manual Reset */
 405 #define SH7750_WTCSR_RST_PWR  0x00 /*    Power-on Reset */
 406 #define SH7750_WTCSR_WOVF     0x10 /* Watchdog Timer Overflow Flag */
 407 #define SH7750_WTCSR_IOVF     0x08 /* Interval Timer Overflow Flag */
 408 #define SH7750_WTCSR_CKS      0x07 /* Clock Select: */
 409 #define SH7750_WTCSR_CKS_DIV32   0x00 /*   1/32 of frequency divider 2 input */
 410 #define SH7750_WTCSR_CKS_DIV64   0x01 /*   1/64 */
 411 #define SH7750_WTCSR_CKS_DIV128  0x02 /*   1/128 */
 412 #define SH7750_WTCSR_CKS_DIV256  0x03 /*   1/256 */
 413 #define SH7750_WTCSR_CKS_DIV512  0x04 /*   1/512 */
 414 #define SH7750_WTCSR_CKS_DIV1024 0x05 /*   1/1024 */
 415 #define SH7750_WTCSR_CKS_DIV2048 0x06 /*   1/2048 */
 416 #define SH7750_WTCSR_CKS_DIV4096 0x07 /*   1/4096 */
 417
 418 /*
 419  * Real-Time Clock (RTC)
 420  */
 421 /* 64-Hz Counter Register (byte, read-only) - R64CNT */
 422 #define SH7750_R64CNT_REGOFS  0xC80000 /* offset */
 423 #define SH7750_R64CNT         SH7750_P4_REG32(SH7750_R64CNT_REGOFS)
 424 #define SH7750_R64CNT_A7      SH7750_A7_REG32(SH7750_R64CNT_REGOFS)
 425
 426 /* Second Counter Register (byte, BCD-coded) - RSECCNT */
 427 #define SH7750_RSECCNT_REGOFS 0xC80004 /* offset */
 428 #define SH7750_RSECCNT        SH7750_P4_REG32(SH7750_RSECCNT_REGOFS)
 429 #define SH7750_RSECCNT_A7     SH7750_A7_REG32(SH7750_RSECCNT_REGOFS)
 430
 431 /* Minute Counter Register (byte, BCD-coded) - RMINCNT */
 432 #define SH7750_RMINCNT_REGOFS 0xC80008 /* offset */
 433 #define SH7750_RMINCNT        SH7750_P4_REG32(SH7750_RMINCNT_REGOFS)
 434 #define SH7750_RMINCNT_A7     SH7750_A7_REG32(SH7750_RMINCNT_REGOFS)
 435
 436 /* Hour Counter Register (byte, BCD-coded) - RHRCNT */
 437 #define SH7750_RHRCNT_REGOFS  0xC8000C /* offset */
 438 #define SH7750_RHRCNT         SH7750_P4_REG32(SH7750_RHRCNT_REGOFS)
 439 #define SH7750_RHRCNT_A7      SH7750_A7_REG32(SH7750_RHRCNT_REGOFS)
 440
 441 /* Day-of-Week Counter Register (byte) - RWKCNT */
 442 #define SH7750_RWKCNT_REGOFS  0xC80010 /* offset */
 443 #define SH7750_RWKCNT         SH7750_P4_REG32(SH7750_RWKCNT_REGOFS)
 444 #define SH7750_RWKCNT_A7      SH7750_A7_REG32(SH7750_RWKCNT_REGOFS)
 445
 446 #define SH7750_RWKCNT_SUN     0 /* Sunday */
 447 #define SH7750_RWKCNT_MON     1 /* Monday */
 448 #define SH7750_RWKCNT_TUE     2 /* Tuesday */
 449 #define SH7750_RWKCNT_WED     3 /* Wednesday */
 450 #define SH7750_RWKCNT_THU     4 /* Thursday */
 451 #define SH7750_RWKCNT_FRI     5 /* Friday */
 452 #define SH7750_RWKCNT_SAT     6 /* Saturday */
 453
 454 /* Day Counter Register (byte, BCD-coded) - RDAYCNT */
 455 #define SH7750_RDAYCNT_REGOFS 0xC80014 /* offset */
 456 #define SH7750_RDAYCNT        SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS)
 457 #define SH7750_RDAYCNT_A7     SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS)
 458
 459 /* Month Counter Register (byte, BCD-coded) - RMONCNT */
 460 #define SH7750_RMONCNT_REGOFS 0xC80018 /* offset */
 461 #define SH7750_RMONCNT        SH7750_P4_REG32(SH7750_RMONCNT_REGOFS)
 462 #define SH7750_RMONCNT_A7     SH7750_A7_REG32(SH7750_RMONCNT_REGOFS)
 463
 464 /* Year Counter Register (half, BCD-coded) - RYRCNT */
 465 #define SH7750_RYRCNT_REGOFS  0xC8001C /* offset */
 466 #define SH7750_RYRCNT         SH7750_P4_REG32(SH7750_RYRCNT_REGOFS)
 467 #define SH7750_RYRCNT_A7      SH7750_A7_REG32(SH7750_RYRCNT_REGOFS)
 468
 469 /* Second Alarm Register (byte, BCD-coded) - RSECAR */
 470 #define SH7750_RSECAR_REGOFS  0xC80020 /* offset */
 471 #define SH7750_RSECAR         SH7750_P4_REG32(SH7750_RSECAR_REGOFS)
 472 #define SH7750_RSECAR_A7      SH7750_A7_REG32(SH7750_RSECAR_REGOFS)
 473 #define SH7750_RSECAR_ENB     0x80 /* Second Alarm Enable */
 474
 475 /* Minute Alarm Register (byte, BCD-coded) - RMINAR */
 476 #define SH7750_RMINAR_REGOFS  0xC80024 /* offset */
 477 #define SH7750_RMINAR         SH7750_P4_REG32(SH7750_RMINAR_REGOFS)
 478 #define SH7750_RMINAR_A7      SH7750_A7_REG32(SH7750_RMINAR_REGOFS)
 479 #define SH7750_RMINAR_ENB     0x80 /* Minute Alarm Enable */
 480
 481 /* Hour Alarm Register (byte, BCD-coded) - RHRAR */
 482 #define SH7750_RHRAR_REGOFS   0xC80028 /* offset */
 483 #define SH7750_RHRAR          SH7750_P4_REG32(SH7750_RHRAR_REGOFS)
 484 #define SH7750_RHRAR_A7       SH7750_A7_REG32(SH7750_RHRAR_REGOFS)
 485 #define SH7750_RHRAR_ENB      0x80 /* Hour Alarm Enable */
 486
 487 /* Day-of-Week Alarm Register (byte) - RWKAR */
 488 #define SH7750_RWKAR_REGOFS   0xC8002C /* offset */
 489 #define SH7750_RWKAR          SH7750_P4_REG32(SH7750_RWKAR_REGOFS)
 490 #define SH7750_RWKAR_A7       SH7750_A7_REG32(SH7750_RWKAR_REGOFS)
 491 #define SH7750_RWKAR_ENB      0x80 /* Day-of-week Alarm Enable */
 492
 493 #define SH7750_RWKAR_SUN      0 /* Sunday */
 494 #define SH7750_RWKAR_MON      1 /* Monday */
 495 #define SH7750_RWKAR_TUE      2 /* Tuesday */
 496 #define SH7750_RWKAR_WED      3 /* Wednesday */
 497 #define SH7750_RWKAR_THU      4 /* Thursday */
 498 #define SH7750_RWKAR_FRI      5 /* Friday */
 499 #define SH7750_RWKAR_SAT      6 /* Saturday */
 500
 501 /* Day Alarm Register (byte, BCD-coded) - RDAYAR */
 502 #define SH7750_RDAYAR_REGOFS  0xC80030 /* offset */
 503 #define SH7750_RDAYAR         SH7750_P4_REG32(SH7750_RDAYAR_REGOFS)
 504 #define SH7750_RDAYAR_A7      SH7750_A7_REG32(SH7750_RDAYAR_REGOFS)
 505 #define SH7750_RDAYAR_ENB     0x80 /* Day Alarm Enable */
 506
 507 /* Month Counter Register (byte, BCD-coded) - RMONAR */
 508 #define SH7750_RMONAR_REGOFS  0xC80034 /* offset */
 509 #define SH7750_RMONAR         SH7750_P4_REG32(SH7750_RMONAR_REGOFS)
 510 #define SH7750_RMONAR_A7      SH7750_A7_REG32(SH7750_RMONAR_REGOFS)
 511 #define SH7750_RMONAR_ENB     0x80 /* Month Alarm Enable */
 512
 513 /* RTC Control Register 1 (byte) - RCR1 */
 514 #define SH7750_RCR1_REGOFS    0xC80038 /* offset */
 515 #define SH7750_RCR1           SH7750_P4_REG32(SH7750_RCR1_REGOFS)
 516 #define SH7750_RCR1_A7        SH7750_A7_REG32(SH7750_RCR1_REGOFS)
 517 #define SH7750_RCR1_CF        0x80 /* Carry Flag */
 518 #define SH7750_RCR1_CIE       0x10 /* Carry Interrupt Enable */
 519 #define SH7750_RCR1_AIE       0x08 /* Alarm Interrupt Enable */
 520 #define SH7750_RCR1_AF        0x01 /* Alarm Flag */
 521
 522 /* RTC Control Register 2 (byte) - RCR2 */
 523 #define SH7750_RCR2_REGOFS    0xC8003C /* offset */
 524 #define SH7750_RCR2           SH7750_P4_REG32(SH7750_RCR2_REGOFS)
 525 #define SH7750_RCR2_A7        SH7750_A7_REG32(SH7750_RCR2_REGOFS)
 526 #define SH7750_RCR2_PEF        0x80 /* Periodic Interrupt Flag */
 527 #define SH7750_RCR2_PES        0x70 /* Periodic Interrupt Enable: */
 528 #define SH7750_RCR2_PES_DIS    0x00 /*   Periodic Interrupt Disabled */
 529 #define SH7750_RCR2_PES_DIV256 0x10 /*   Generated at 1/256 sec interval */
 530 #define SH7750_RCR2_PES_DIV64  0x20 /*   Generated at 1/64 sec interval */
 531 #define SH7750_RCR2_PES_DIV16  0x30 /*   Generated at 1/16 sec interval */
 532 #define SH7750_RCR2_PES_DIV4   0x40 /*   Generated at 1/4 sec interval */
 533 #define SH7750_RCR2_PES_DIV2   0x50 /*   Generated at 1/2 sec interval */
 534 #define SH7750_RCR2_PES_x1     0x60 /*   Generated at 1 sec interval */
 535 #define SH7750_RCR2_PES_x2     0x70 /*   Generated at 2 sec interval */
 536 #define SH7750_RCR2_RTCEN      0x08 /* RTC Crystal Oscillator is Operated */
 537 #define SH7750_RCR2_ADJ        0x04 /* 30-Second Adjastment */
 538 #define SH7750_RCR2_RESET      0x02 /* Frequency divider circuits are reset */
 539 #define SH7750_RCR2_START      0x01 /* 0 - sec, min, hr, day-of-week, month, */
 540                                     /*     year counters are stopped */
 541                                     /* 1 - sec, min, hr, day-of-week, month, */
 542                                     /*     year counters operate normally */
 543 /*
 544  * Bus State Controller - BSC
 545  */
 546 /* Bus Control Register 1 - BCR1 */
 547 #define SH7750_BCR1_REGOFS    0x800000 /* offset */
 548 #define SH7750_BCR1           SH7750_P4_REG32(SH7750_BCR1_REGOFS)
 549 #define SH7750_BCR1_A7        SH7750_A7_REG32(SH7750_BCR1_REGOFS)
 550 #define SH7750_BCR1_ENDIAN    0x80000000 /* Endianness (1 - little endian) */
 551 #define SH7750_BCR1_MASTER    0x40000000 /* Master/Slave mode (1-master) */
 552 #define SH7750_BCR1_A0MPX     0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX) */
 553 #define SH7750_BCR1_IPUP      0x02000000 /* Input Pin Pull-up Control: */
 554                                          /*   0 - pull-up resistor is on for */
 555                                          /*       control input pins */
 556                                          /*   1 - pull-up resistor is off */
 557 #define SH7750_BCR1_OPUP      0x01000000 /* Output Pin Pull-up Control: */
 558                                          /*   0 - pull-up resistor is on for */
 559                                          /*       control output pins */
 560                                          /*   1 - pull-up resistor is off */
 561 #define SH7750_BCR1_A1MBC     0x00200000 /* Area 1 SRAM Byte Control Mode: */
 562                                          /*   0 - Area 1 SRAM is set to */
 563                                          /*       normal mode */
 564                                          /*   1 - Area 1 SRAM is set to byte */
 565                                          /*       control mode */
 566 #define SH7750_BCR1_A4MBC     0x00100000 /* Area 4 SRAM Byte Control Mode: */
 567                                          /*   0 - Area 4 SRAM is set to */
 568                                          /*       normal mode */
 569                                          /*   1 - Area 4 SRAM is set to byte */
 570                                          /*       control mode */
 571 #define SH7750_BCR1_BREQEN    0x00080000 /* BREQ Enable: */
 572                                          /*   0 - External requests are  not */
 573                                          /*       accepted */
 574                                          /*   1 - External requests are */
 575                                          /*       accepted */
 576 #define SH7750_BCR1_PSHR      0x00040000 /* Partial Sharing Bit: */
 577                                          /*   0 - Master Mode */
 578                                          /*   1 - Partial-sharing Mode */
 579 #define SH7750_BCR1_MEMMPX    0x00020000 /* Area 1 to 6 MPX Interface: */
 580                                          /*   0 - SRAM/burst ROM interface */
 581                                          /*   1 - MPX interface */
 582 #define SH7750_BCR1_HIZMEM    0x00008000 /* High Impendance Control. */
 583                                          /*   Specifies the state of A[25:0], */
 584                                          /*   BS\, CSn\, RD/WR\, CE2A\, CE2B\ */
 585                                          /*   in standby mode and when bus is */
 586                                          /*   released: */
 587                                          /*   0 - signals go to High-Z mode */
 588                                          /*   1 - signals driven */
 589 #define SH7750_BCR1_HIZCNT    0x00004000 /* High Impendance Control. */
 590                                          /*   Specifies the state of the */
 591                                          /*   RAS\, RAS2\, WEn\, CASn\, DQMn, */
 592                                          /*   RD\, CASS\, FRAME\, RD2\ */
 593                                          /*   signals in standby mode and */
 594                                          /* when bus is released: */
 595                                          /*   0 - signals go to High-Z mode */
 596                                          /*   1 - signals driven */
 597 #define SH7750_BCR1_A0BST     0x00003800 /* Area 0 Burst ROM Control */
 598 #define SH7750_BCR1_A0BST_SRAM    0x0000 /*   Area 0 accessed as SRAM i/f */
 599 #define SH7750_BCR1_A0BST_ROM4    0x0800 /*   Area 0 accessed as burst ROM */
 600                                          /*   interface, 4 cosequtive access */
 601 #define SH7750_BCR1_A0BST_ROM8    0x1000 /*   Area 0 accessed as burst ROM */
 602                                          /*   interface, 8 cosequtive access */
 603 #define SH7750_BCR1_A0BST_ROM16   0x1800 /*   Area 0 accessed as burst ROM */
 604                                          /*   interface, 16 cosequtive access */
 605 #define SH7750_BCR1_A0BST_ROM32   0x2000 /*   Area 0 accessed as burst ROM */
 606                                          /*   interface, 32 cosequtive access */
 607
 608 #define SH7750_BCR1_A5BST     0x00000700 /* Area 5 Burst ROM Control */
 609 #define SH7750_BCR1_A5BST_SRAM    0x0000 /*   Area 5 accessed as SRAM i/f */
 610 #define SH7750_BCR1_A5BST_ROM4    0x0100 /*   Area 5 accessed as burst ROM */
 611                                          /*   interface, 4 cosequtive access */
 612 #define SH7750_BCR1_A5BST_ROM8    0x0200 /*   Area 5 accessed as burst ROM */
 613                                          /*   interface, 8 cosequtive access */
 614 #define SH7750_BCR1_A5BST_ROM16   0x0300 /*   Area 5 accessed as burst ROM */
 615                                          /*   interface, 16 cosequtive access */
 616 #define SH7750_BCR1_A5BST_ROM32   0x0400 /*   Area 5 accessed as burst ROM */
 617                                          /*   interface, 32 cosequtive access */
 618
 619 #define SH7750_BCR1_A6BST     0x000000E0 /* Area 6 Burst ROM Control */
 620 #define SH7750_BCR1_A6BST_SRAM    0x0000 /*   Area 6 accessed as SRAM i/f */
 621 #define SH7750_BCR1_A6BST_ROM4    0x0020 /*   Area 6 accessed as burst ROM */
 622                                          /*   interface, 4 cosequtive access */
 623 #define SH7750_BCR1_A6BST_ROM8    0x0040 /*   Area 6 accessed as burst ROM */
 624                                          /*   interface, 8 cosequtive access */
 625 #define SH7750_BCR1_A6BST_ROM16   0x0060 /*   Area 6 accessed as burst ROM */
 626                                          /*   interface, 16 cosequtive access */
 627 #define SH7750_BCR1_A6BST_ROM32   0x0080 /*   Area 6 accessed as burst ROM */
 628                                          /*   interface, 32 cosequtive access */
 629
 630 #define SH7750_BCR1_DRAMTP        0x001C /* Area 2 and 3 Memory Type */
 631 #define SH7750_BCR1_DRAMTP_2SRAM_3SRAM   0x0000 /* Area 2 and 3 are SRAM or */
 632                                                 /* MPX interface. */
 633 #define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM  0x0008 /* Area 2 - SRAM/MPX, Area 3 */
 634                                                 /* synchronous DRAM */
 635 #define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C /* Area 2 and 3 are */
 636                                                 /* synchronous DRAM interface */
 637 #define SH7750_BCR1_DRAMTP_2SRAM_3DRAM   0x0010 /* Area 2 - SRAM/MPX, Area 3 */
 638                                                 /* DRAM interface */
 639 #define SH7750_BCR1_DRAMTP_2DRAM_3DRAM   0x0014 /* Area 2 and 3 are DRAM */
 640                                                 /* interface */
 641
 642 #define SH7750_BCR1_A56PCM    0x00000001 /* Area 5 and 6 Bus Type: */
 643                                          /*   0 - SRAM interface */
 644                                          /*   1 - PCMCIA interface */
 645
 646 /* Bus Control Register 2 (half) - BCR2 */
 647 #define SH7750_BCR2_REGOFS    0x800004 /* offset */
 648 #define SH7750_BCR2           SH7750_P4_REG32(SH7750_BCR2_REGOFS)
 649 #define SH7750_BCR2_A7        SH7750_A7_REG32(SH7750_BCR2_REGOFS)
 650
 651 #define SH7750_BCR2_A0SZ      0xC000 /* Area 0 Bus Width */
 652 #define SH7750_BCR2_A0SZ_S    14
 653 #define SH7750_BCR2_A6SZ      0x3000 /* Area 6 Bus Width */
 654 #define SH7750_BCR2_A6SZ_S    12
 655 #define SH7750_BCR2_A5SZ      0x0C00 /* Area 5 Bus Width */
 656 #define SH7750_BCR2_A5SZ_S    10
 657 #define SH7750_BCR2_A4SZ      0x0300 /* Area 4 Bus Width */
 658 #define SH7750_BCR2_A4SZ_S    8
 659 #define SH7750_BCR2_A3SZ      0x00C0 /* Area 3 Bus Width */
 660 #define SH7750_BCR2_A3SZ_S    6
 661 #define SH7750_BCR2_A2SZ      0x0030 /* Area 2 Bus Width */
 662 #define SH7750_BCR2_A2SZ_S    4
 663 #define SH7750_BCR2_A1SZ      0x000C /* Area 1 Bus Width */
 664 #define SH7750_BCR2_A1SZ_S    2
 665 #define SH7750_BCR2_SZ_64     0 /* 64 bits */
 666 #define SH7750_BCR2_SZ_8      1 /* 8 bits */
 667 #define SH7750_BCR2_SZ_16     2 /* 16 bits */
 668 #define SH7750_BCR2_SZ_32     3 /* 32 bits */
 669 #define SH7750_BCR2_PORTEN    0x0001 /* Port Function Enable */
 670                                      /* 0 - D51-D32 are not used as a port */
 671                                      /* 1 - D51-D32 are used as a port */
 672
 673 /* Wait Control Register 1 - WCR1 */
 674 #define SH7750_WCR1_REGOFS    0x800008 /* offset */
 675 #define SH7750_WCR1           SH7750_P4_REG32(SH7750_WCR1_REGOFS)
 676 #define SH7750_WCR1_A7        SH7750_A7_REG32(SH7750_WCR1_REGOFS)
 677 #define SH7750_WCR1_DMAIW     0x70000000 /* DACK Device Inter-Cycle Idle */
 678                                          /*   specification */
 679 #define SH7750_WCR1_DMAIW_S   28
 680 #define SH7750_WCR1_A6IW      0x07000000 /* Area 6 Inter-Cycle Idle spec. */
 681 #define SH7750_WCR1_A6IW_S    24
 682 #define SH7750_WCR1_A5IW      0x00700000 /* Area 5 Inter-Cycle Idle spec. */
 683 #define SH7750_WCR1_A5IW_S    20
 684 #define SH7750_WCR1_A4IW      0x00070000 /* Area 4 Inter-Cycle Idle spec. */
 685 #define SH7750_WCR1_A4IW_S    16
 686 #define SH7750_WCR1_A3IW      0x00007000 /* Area 3 Inter-Cycle Idle spec. */
 687 #define SH7750_WCR1_A3IW_S    12
 688 #define SH7750_WCR1_A2IW      0x00000700 /* Area 2 Inter-Cycle Idle spec. */
 689 #define SH7750_WCR1_A2IW_S    8
 690 #define SH7750_WCR1_A1IW      0x00000070 /* Area 1 Inter-Cycle Idle spec. */
 691 #define SH7750_WCR1_A1IW_S    4
 692 #define SH7750_WCR1_A0IW      0x00000007 /* Area 0 Inter-Cycle Idle spec. */
 693 #define SH7750_WCR1_A0IW_S    0
 694
 695 /* Wait Control Register 2 - WCR2 */
 696 #define SH7750_WCR2_REGOFS    0x80000C /* offset */
 697 #define SH7750_WCR2           SH7750_P4_REG32(SH7750_WCR2_REGOFS)
 698 #define SH7750_WCR2_A7        SH7750_A7_REG32(SH7750_WCR2_REGOFS)
 699
 700 #define SH7750_WCR2_A6W       0xE0000000 /* Area 6 Wait Control */
 701 #define SH7750_WCR2_A6W_S     29
 702 #define SH7750_WCR2_A6B       0x1C000000 /* Area 6 Burst Pitch */
 703 #define SH7750_WCR2_A6B_S     26
 704 #define SH7750_WCR2_A5W       0x03800000 /* Area 5 Wait Control */
 705 #define SH7750_WCR2_A5W_S     23
 706 #define SH7750_WCR2_A5B       0x00700000 /* Area 5 Burst Pitch */
 707 #define SH7750_WCR2_A5B_S     20
 708 #define SH7750_WCR2_A4W       0x000E0000 /* Area 4 Wait Control */
 709 #define SH7750_WCR2_A4W_S     17
 710 #define SH7750_WCR2_A3W       0x0000E000 /* Area 3 Wait Control */
 711 #define SH7750_WCR2_A3W_S     13
 712 #define SH7750_WCR2_A2W       0x00000E00 /* Area 2 Wait Control */
 713 #define SH7750_WCR2_A2W_S     9
 714 #define SH7750_WCR2_A1W       0x000001C0 /* Area 1 Wait Control */
 715 #define SH7750_WCR2_A1W_S     6
 716 #define SH7750_WCR2_A0W       0x00000038 /* Area 0 Wait Control */
 717 #define SH7750_WCR2_A0W_S     3
 718 #define SH7750_WCR2_A0B       0x00000007 /* Area 0 Burst Pitch */
 719 #define SH7750_WCR2_A0B_S     0
 720
 721 #define SH7750_WCR2_WS0       0 /* 0 wait states inserted */
 722 #define SH7750_WCR2_WS1       1 /* 1 wait states inserted */
 723 #define SH7750_WCR2_WS2       2 /* 2 wait states inserted */
 724 #define SH7750_WCR2_WS3       3 /* 3 wait states inserted */
 725 #define SH7750_WCR2_WS6       4 /* 6 wait states inserted */
 726 #define SH7750_WCR2_WS9       5 /* 9 wait states inserted */
 727 #define SH7750_WCR2_WS12      6 /* 12 wait states inserted */
 728 #define SH7750_WCR2_WS15      7 /* 15 wait states inserted */
 729
 730 #define SH7750_WCR2_BPWS0     0 /* 0 wait states inserted from 2nd access */
 731 #define SH7750_WCR2_BPWS1     1 /* 1 wait states inserted from 2nd access */
 732 #define SH7750_WCR2_BPWS2     2 /* 2 wait states inserted from 2nd access */
 733 #define SH7750_WCR2_BPWS3     3 /* 3 wait states inserted from 2nd access */
 734 #define SH7750_WCR2_BPWS4     4 /* 4 wait states inserted from 2nd access */
 735 #define SH7750_WCR2_BPWS5     5 /* 5 wait states inserted from 2nd access */
 736 #define SH7750_WCR2_BPWS6     6 /* 6 wait states inserted from 2nd access */
 737 #define SH7750_WCR2_BPWS7     7 /* 7 wait states inserted from 2nd access */
 738
 739 /* DRAM CAS\ Assertion Delay (area 3,2) */
 740 #define SH7750_WCR2_DRAM_CAS_ASW1   0 /* 1 cycle */
 741 #define SH7750_WCR2_DRAM_CAS_ASW2   1 /* 2 cycles */
 742 #define SH7750_WCR2_DRAM_CAS_ASW3   2 /* 3 cycles */
 743 #define SH7750_WCR2_DRAM_CAS_ASW4   3 /* 4 cycles */
 744 #define SH7750_WCR2_DRAM_CAS_ASW7   4 /* 7 cycles */
 745 #define SH7750_WCR2_DRAM_CAS_ASW10  5 /* 10 cycles */
 746 #define SH7750_WCR2_DRAM_CAS_ASW13  6 /* 13 cycles */
 747 #define SH7750_WCR2_DRAM_CAS_ASW16  7 /* 16 cycles */
 748
 749 /* SDRAM CAS\ Latency Cycles */
 750 #define SH7750_WCR2_SDRAM_CAS_LAT1  1 /* 1 cycle */
 751 #define SH7750_WCR2_SDRAM_CAS_LAT2  2 /* 2 cycles */
 752 #define SH7750_WCR2_SDRAM_CAS_LAT3  3 /* 3 cycles */
 753 #define SH7750_WCR2_SDRAM_CAS_LAT4  4 /* 4 cycles */
 754 #define SH7750_WCR2_SDRAM_CAS_LAT5  5 /* 5 cycles */
 755
 756 /* Wait Control Register 3 - WCR3 */
 757 #define SH7750_WCR3_REGOFS    0x800010 /* offset */
 758 #define SH7750_WCR3           SH7750_P4_REG32(SH7750_WCR3_REGOFS)
 759 #define SH7750_WCR3_A7        SH7750_A7_REG32(SH7750_WCR3_REGOFS)
 760
 761 #define SH7750_WCR3_A6S       0x04000000 /* Area 6 Write Strobe Setup time */
 762 #define SH7750_WCR3_A6H       0x03000000 /* Area 6 Data Hold Time */
 763 #define SH7750_WCR3_A6H_S     24
 764 #define SH7750_WCR3_A5S       0x00400000 /* Area 5 Write Strobe Setup time */
 765 #define SH7750_WCR3_A5H       0x00300000 /* Area 5 Data Hold Time */
 766 #define SH7750_WCR3_A5H_S     20
 767 #define SH7750_WCR3_A4S       0x00040000 /* Area 4 Write Strobe Setup time */
 768 #define SH7750_WCR3_A4H       0x00030000 /* Area 4 Data Hold Time */
 769 #define SH7750_WCR3_A4H_S     16
 770 #define SH7750_WCR3_A3S       0x00004000 /* Area 3 Write Strobe Setup time */
 771 #define SH7750_WCR3_A3H       0x00003000 /* Area 3 Data Hold Time */
 772 #define SH7750_WCR3_A3H_S     12
 773 #define SH7750_WCR3_A2S       0x00000400 /* Area 2 Write Strobe Setup time */
 774 #define SH7750_WCR3_A2H       0x00000300 /* Area 2 Data Hold Time */
 775 #define SH7750_WCR3_A2H_S     8
 776 #define SH7750_WCR3_A1S       0x00000040 /* Area 1 Write Strobe Setup time */
 777 #define SH7750_WCR3_A1H       0x00000030 /* Area 1 Data Hold Time */
 778 #define SH7750_WCR3_A1H_S     4
 779 #define SH7750_WCR3_A0S       0x00000004 /* Area 0 Write Strobe Setup time */
 780 #define SH7750_WCR3_A0H       0x00000003 /* Area 0 Data Hold Time */
 781 #define SH7750_WCR3_A0H_S     0
 782
 783 #define SH7750_WCR3_DHWS_0    0 /* 0 wait states data hold time */
 784 #define SH7750_WCR3_DHWS_1    1 /* 1 wait states data hold time */
 785 #define SH7750_WCR3_DHWS_2    2 /* 2 wait states data hold time */
 786 #define SH7750_WCR3_DHWS_3    3 /* 3 wait states data hold time */
 787
 788 #define SH7750_MCR_REGOFS     0x800014 /* offset */
 789 #define SH7750_MCR            SH7750_P4_REG32(SH7750_MCR_REGOFS)
 790 #define SH7750_MCR_A7         SH7750_A7_REG32(SH7750_MCR_REGOFS)
 791
 792 #define SH7750_MCR_RASD       0x80000000 /* RAS Down mode */
 793 #define SH7750_MCR_MRSET      0x40000000 /* SDRAM Mode Register Set */
 794 #define SH7750_MCR_PALL       0x00000000 /* SDRAM Precharge All cmd. Mode */
 795 #define SH7750_MCR_TRC        0x38000000 /* RAS Precharge Time at End of */
 796                                          /* Refresh: */
 797 #define SH7750_MCR_TRC_0      0x00000000 /*    0 */
 798 #define SH7750_MCR_TRC_3      0x08000000 /*    3 */
 799 #define SH7750_MCR_TRC_6      0x10000000 /*    6 */
 800 #define SH7750_MCR_TRC_9      0x18000000 /*    9 */
 801 #define SH7750_MCR_TRC_12     0x20000000 /*    12 */
 802 #define SH7750_MCR_TRC_15     0x28000000 /*    15 */
 803 #define SH7750_MCR_TRC_18     0x30000000 /*    18 */
 804 #define SH7750_MCR_TRC_21     0x38000000 /*    21 */
 805
 806 #define SH7750_MCR_TCAS       0x00800000 /* CAS Negation Period */
 807 #define SH7750_MCR_TCAS_1     0x00000000 /*    1 */
 808 #define SH7750_MCR_TCAS_2     0x00800000 /*    2 */
 809
 810 #define SH7750_MCR_TPC        0x00380000 /* DRAM: RAS Precharge Period */
 811                                          /* SDRAM: minimum number of cycles */
 812                                          /* until the next bank active cmd */
 813                                          /* is output after precharging */
 814 #define SH7750_MCR_TPC_S      19
 815 #define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */
 816 #define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */
 817 #define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */
 818 #define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */
 819 #define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */
 820 #define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */
 821 #define SH7750_MCR_TPC_SDRAM_7 0x00300000 /* 7 cycles */
 822 #define SH7750_MCR_TPC_SDRAM_8 0x00380000 /* 8 cycles */
 823
 824 #define SH7750_MCR_RCD         0x00030000 /* DRAM: RAS-CAS Assertion Delay */
 825                                           /*   time */
 826                                           /* SDRAM: bank active-read/write */
 827                                           /*   command delay time */
 828 #define SH7750_MCR_RCD_DRAM_2  0x00000000 /* DRAM delay 2 clocks */
 829 #define SH7750_MCR_RCD_DRAM_3  0x00010000 /* DRAM delay 3 clocks */
 830 #define SH7750_MCR_RCD_DRAM_4  0x00020000 /* DRAM delay 4 clocks */
 831 #define SH7750_MCR_RCD_DRAM_5  0x00030000 /* DRAM delay 5 clocks */
 832 #define SH7750_MCR_RCD_SDRAM_2 0x00010000 /* DRAM delay 2 clocks */
 833 #define SH7750_MCR_RCD_SDRAM_3 0x00020000 /* DRAM delay 3 clocks */
 834 #define SH7750_MCR_RCD_SDRAM_4 0x00030000 /* DRAM delay 4 clocks */
 835
 836 #define SH7750_MCR_TRWL       0x0000E000 /* SDRAM Write Precharge Delay */
 837 #define SH7750_MCR_TRWL_1     0x00000000 /* 1 */
 838 #define SH7750_MCR_TRWL_2     0x00002000 /* 2 */
 839 #define SH7750_MCR_TRWL_3     0x00004000 /* 3 */
 840 #define SH7750_MCR_TRWL_4     0x00006000 /* 4 */
 841 #define SH7750_MCR_TRWL_5     0x00008000 /* 5 */
 842
 843 #define SH7750_MCR_TRAS       0x00001C00 /* DRAM: CAS-Before-RAS Refresh RAS */
 844                                          /* asserting period */
 845                                          /* SDRAM: Command interval after */
 846                                          /* synchronous DRAM refresh */
 847 #define SH7750_MCR_TRAS_DRAM_2         0x00000000 /* 2 */
 848 #define SH7750_MCR_TRAS_DRAM_3         0x00000400 /* 3 */
 849 #define SH7750_MCR_TRAS_DRAM_4         0x00000800 /* 4 */
 850 #define SH7750_MCR_TRAS_DRAM_5         0x00000C00 /* 5 */
 851 #define SH7750_MCR_TRAS_DRAM_6         0x00001000 /* 6 */
 852 #define SH7750_MCR_TRAS_DRAM_7         0x00001400 /* 7 */
 853 #define SH7750_MCR_TRAS_DRAM_8         0x00001800 /* 8 */
 854 #define SH7750_MCR_TRAS_DRAM_9         0x00001C00 /* 9 */
 855
 856 #define SH7750_MCR_TRAS_SDRAM_TRC_4    0x00000000 /* 4 + TRC */
 857 #define SH7750_MCR_TRAS_SDRAM_TRC_5    0x00000400 /* 5 + TRC */
 858 #define SH7750_MCR_TRAS_SDRAM_TRC_6    0x00000800 /* 6 + TRC */
 859 #define SH7750_MCR_TRAS_SDRAM_TRC_7    0x00000C00 /* 7 + TRC */
 860 #define SH7750_MCR_TRAS_SDRAM_TRC_8    0x00001000 /* 8 + TRC */
 861 #define SH7750_MCR_TRAS_SDRAM_TRC_9    0x00001400 /* 9 + TRC */
 862 #define SH7750_MCR_TRAS_SDRAM_TRC_10   0x00001800 /* 10 + TRC */
 863 #define SH7750_MCR_TRAS_SDRAM_TRC_11   0x00001C00 /* 11 + TRC */
 864
 865 #define SH7750_MCR_BE         0x00000200 /* Burst Enable */
 866 #define SH7750_MCR_SZ         0x00000180 /* Memory Data Size */
 867 #define SH7750_MCR_SZ_64      0x00000000 /* 64 bits */
 868 #define SH7750_MCR_SZ_16      0x00000100 /* 16 bits */
 869 #define SH7750_MCR_SZ_32      0x00000180 /* 32 bits */
 870
 871 #define SH7750_MCR_AMX        0x00000078 /* Address Multiplexing */
 872 #define SH7750_MCR_AMX_S      3
 873 #define SH7750_MCR_AMX_DRAM_8BIT_COL    0x00000000 /* 8-bit column addr */
 874 #define SH7750_MCR_AMX_DRAM_9BIT_COL    0x00000008 /* 9-bit column addr */
 875 #define SH7750_MCR_AMX_DRAM_10BIT_COL   0x00000010 /* 10-bit column addr */
 876 #define SH7750_MCR_AMX_DRAM_11BIT_COL   0x00000018 /* 11-bit column addr */
 877 #define SH7750_MCR_AMX_DRAM_12BIT_COL   0x00000020 /* 12-bit column addr */
 878 /* See SH7750 Hardware Manual for SDRAM address multiplexor selection */
 879
 880 #define SH7750_MCR_RFSH       0x00000004 /* Refresh Control */
 881 #define SH7750_MCR_RMODE      0x00000002 /* Refresh Mode: */
 882 #define SH7750_MCR_RMODE_NORMAL 0x00000000 /* Normal Refresh Mode */
 883 #define SH7750_MCR_RMODE_SELF   0x00000002 /* Self-Refresh Mode */
 884 #define SH7750_MCR_RMODE_EDO    0x00000001 /* EDO Mode */
 885
 886 /* SDRAM Mode Set address */
 887 #define SH7750_SDRAM_MODE_A2_BASE  0xFF900000
 888 #define SH7750_SDRAM_MODE_A3_BASE  0xFF940000
 889 #define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2))
 890 #define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2))
 891 #define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3))
 892 #define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3))
 893
 894
 895 /* PCMCIA Control Register (half) - PCR */
 896 #define SH7750_PCR_REGOFS     0x800018 /* offset */
 897 #define SH7750_PCR            SH7750_P4_REG32(SH7750_PCR_REGOFS)
 898 #define SH7750_PCR_A7         SH7750_A7_REG32(SH7750_PCR_REGOFS)
 899
 900 #define SH7750_PCR_A5PCW      0xC000 /* Area 5 PCMCIA Wait - Number of wait */
 901                                      /* states to be added to the number of */
 902                                      /* waits specified by WCR2 in a */
 903                                      /* low-speed PCMCIA wait cycle */
 904 #define SH7750_PCR_A5PCW_0    0x0000 /*    0 waits inserted */
 905 #define SH7750_PCR_A5PCW_15   0x4000 /*    15 waits inserted */
 906 #define SH7750_PCR_A5PCW_30   0x8000 /*    30 waits inserted */
 907 #define SH7750_PCR_A5PCW_50   0xC000 /*    50 waits inserted */
 908
 909 #define SH7750_PCR_A6PCW      0x3000 /* Area 6 PCMCIA Wait - Number of wait */
 910                                      /* states to be added to the number of */
 911                                      /* waits specified by WCR2 in a */
 912                                      /* low-speed PCMCIA wait cycle */
 913 #define SH7750_PCR_A6PCW_0    0x0000 /*    0 waits inserted */
 914 #define SH7750_PCR_A6PCW_15   0x1000 /*    15 waits inserted */
 915 #define SH7750_PCR_A6PCW_30   0x2000 /*    30 waits inserted */
 916 #define SH7750_PCR_A6PCW_50   0x3000 /*    50 waits inserted */
 917
 918 #define SH7750_PCR_A5TED      0x0E00 /* Area 5 Addr-OE\/WE\ Assertion Delay */
 919                                      /* delay time from address output to */
 920                                      /* OE\/WE\ assertion on the connected */
 921                                      /* PCMCIA interface */
 922 #define SH7750_PCR_A5TED_S    9
 923 #define SH7750_PCR_A6TED      0x01C0 /* Area 6 Addr-OE\/WE\ Assertion Delay */
 924 #define SH7750_PCR_A6TED_S    6
 925
 926 #define SH7750_PCR_TED_0WS    0 /* 0 Waits inserted */
 927 #define SH7750_PCR_TED_1WS    1 /* 1 Waits inserted */
 928 #define SH7750_PCR_TED_2WS    2 /* 2 Waits inserted */
 929 #define SH7750_PCR_TED_3WS    3 /* 3 Waits inserted */
 930 #define SH7750_PCR_TED_6WS    4 /* 6 Waits inserted */
 931 #define SH7750_PCR_TED_9WS    5 /* 9 Waits inserted */
 932 #define SH7750_PCR_TED_12WS   6 /* 12 Waits inserted */
 933 #define SH7750_PCR_TED_15WS   7 /* 15 Waits inserted */
 934
 935 #define SH7750_PCR_A5TEH      0x0038 /* Area 5 OE\/WE\ Negation Addr delay, */
 936                                      /* address hold delay time from OE\/WE\ */
 937                                      /* negation in a write on the connected */
 938                                      /* PCMCIA interface */
 939 #define SH7750_PCR_A5TEH_S    3
 940
 941 #define SH7750_PCR_A6TEH      0x0007 /* Area 6 OE\/WE\ Negation Address delay */
 942 #define SH7750_PCR_A6TEH_S    0
 943
 944 #define SH7750_PCR_TEH_0WS    0 /* 0 Waits inserted */
 945 #define SH7750_PCR_TEH_1WS    1 /* 1 Waits inserted */
 946 #define SH7750_PCR_TEH_2WS    2 /* 2 Waits inserted */
 947 #define SH7750_PCR_TEH_3WS    3 /* 3 Waits inserted */
 948 #define SH7750_PCR_TEH_6WS    4 /* 6 Waits inserted */
 949 #define SH7750_PCR_TEH_9WS    5 /* 9 Waits inserted */
 950 #define SH7750_PCR_TEH_12WS   6 /* 12 Waits inserted */
 951 #define SH7750_PCR_TEH_15WS   7 /* 15 Waits inserted */
 952
 953 /* Refresh Timer Control/Status Register (half) - RTSCR */
 954 #define SH7750_RTCSR_REGOFS   0x80001C /* offset */
 955 #define SH7750_RTCSR          SH7750_P4_REG32(SH7750_RTCSR_REGOFS)
 956 #define SH7750_RTCSR_A7       SH7750_A7_REG32(SH7750_RTCSR_REGOFS)
 957
 958 #define SH7750_RTCSR_KEY      0xA500 /* RTCSR write key */
 959 #define SH7750_RTCSR_CMF      0x0080 /* Compare-Match Flag (indicates a */
 960                                      /* match between the refresh timer */
 961                                      /* counter and refresh time constant) */
 962 #define SH7750_RTCSR_CMIE     0x0040 /* Compare-Match Interrupt Enable */
 963 #define SH7750_RTCSR_CKS      0x0038 /* Refresh Counter Clock Selects */
 964 #define SH7750_RTCSR_CKS_DIS          0x0000 /* Clock Input Disabled */
 965 #define SH7750_RTCSR_CKS_CKIO_DIV4    0x0008 /* Bus Clock / 4 */
 966 #define SH7750_RTCSR_CKS_CKIO_DIV16   0x0010 /* Bus Clock / 16 */
 967 #define SH7750_RTCSR_CKS_CKIO_DIV64   0x0018 /* Bus Clock / 64 */
 968 #define SH7750_RTCSR_CKS_CKIO_DIV256  0x0020 /* Bus Clock / 256 */
 969 #define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028 /* Bus Clock / 1024 */
 970 #define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030 /* Bus Clock / 2048 */
 971 #define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038 /* Bus Clock / 4096 */
 972
 973 #define SH7750_RTCSR_OVF      0x0004 /* Refresh Count Overflow Flag */
 974 #define SH7750_RTCSR_OVIE     0x0002 /* Refresh Count Overflow Interrupt */
 975                                      /*   Enable */
 976 #define SH7750_RTCSR_LMTS     0x0001 /* Refresh Count Overflow Limit Select */
 977 #define SH7750_RTCSR_LMTS_1024 0x0000 /* Count Limit is 1024 */
 978 #define SH7750_RTCSR_LMTS_512  0x0001 /* Count Limit is 512 */
 979
 980 /* Refresh Timer Counter (half) - RTCNT */
 981 #define SH7750_RTCNT_REGOFS   0x800020 /* offset */
 982 #define SH7750_RTCNT          SH7750_P4_REG32(SH7750_RTCNT_REGOFS)
 983 #define SH7750_RTCNT_A7       SH7750_A7_REG32(SH7750_RTCNT_REGOFS)
 984
 985 #define SH7750_RTCNT_KEY      0xA500 /* RTCNT write key */
 986
 987 /* Refresh Time Constant Register (half) - RTCOR */
 988 #define SH7750_RTCOR_REGOFS   0x800024 /* offset */
 989 #define SH7750_RTCOR          SH7750_P4_REG32(SH7750_RTCOR_REGOFS)
 990 #define SH7750_RTCOR_A7       SH7750_A7_REG32(SH7750_RTCOR_REGOFS)
 991
 992 #define SH7750_RTCOR_KEY      0xA500 /* RTCOR write key */
 993
 994 /* Refresh Count Register (half) - RFCR */
 995 #define SH7750_RFCR_REGOFS    0x800028 /* offset */
 996 #define SH7750_RFCR           SH7750_P4_REG32(SH7750_RFCR_REGOFS)
 997 #define SH7750_RFCR_A7        SH7750_A7_REG32(SH7750_RFCR_REGOFS)
 998
 999 #define SH7750_RFCR_KEY       0xA400 /* RFCR write key */
1000
1001 /* Synchronous DRAM mode registers - SDMR */
1002 #define SH7750_SDMR2_REGOFS   0x900000 /* base offset */
1003 #define SH7750_SDMR2_REGNB    0x0FFC /* nb of register */
1004 #define SH7750_SDMR2          SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
1005 #define SH7750_SDMR2_A7       SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
1006
1007 #define SH7750_SDMR3_REGOFS   0x940000 /* offset */
1008 #define SH7750_SDMR3_REGNB    0x0FFC /* nb of register */
1009 #define SH7750_SDMR3          SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
1010 #define SH7750_SDMR3_A7       SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
1011
1012 /*
1013  * Direct Memory Access Controller (DMAC)
1014  */
1015
1016 /* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */
1017 #define SH7750_SAR_REGOFS(n)  (0xA00000 + ((n) * 16)) /* offset */
1018 #define SH7750_SAR(n)         SH7750_P4_REG32(SH7750_SAR_REGOFS(n))
1019 #define SH7750_SAR_A7(n)      SH7750_A7_REG32(SH7750_SAR_REGOFS(n))
1020 #define SH7750_SAR0           SH7750_SAR(0)
1021 #define SH7750_SAR1           SH7750_SAR(1)
1022 #define SH7750_SAR2           SH7750_SAR(2)
1023 #define SH7750_SAR3           SH7750_SAR(3)
1024 #define SH7750_SAR0_A7        SH7750_SAR_A7(0)
1025 #define SH7750_SAR1_A7        SH7750_SAR_A7(1)
1026 #define SH7750_SAR2_A7        SH7750_SAR_A7(2)
1027 #define SH7750_SAR3_A7        SH7750_SAR_A7(3)
1028
1029 /* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */
1030 #define SH7750_DAR_REGOFS(n)  (0xA00004 + ((n) * 16)) /* offset */
1031 #define SH7750_DAR(n)         SH7750_P4_REG32(SH7750_DAR_REGOFS(n))
1032 #define SH7750_DAR_A7(n)      SH7750_A7_REG32(SH7750_DAR_REGOFS(n))
1033 #define SH7750_DAR0           SH7750_DAR(0)
1034 #define SH7750_DAR1           SH7750_DAR(1)
1035 #define SH7750_DAR2           SH7750_DAR(2)
1036 #define SH7750_DAR3           SH7750_DAR(3)
1037 #define SH7750_DAR0_A7        SH7750_DAR_A7(0)
1038 #define SH7750_DAR1_A7        SH7750_DAR_A7(1)
1039 #define SH7750_DAR2_A7        SH7750_DAR_A7(2)
1040 #define SH7750_DAR3_A7        SH7750_DAR_A7(3)
1041
1042 /* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */
1043 #define SH7750_DMATCR_REGOFS(n)  (0xA00008 + ((n) * 16)) /* offset */
1044 #define SH7750_DMATCR(n)      SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n))
1045 #define SH7750_DMATCR_A7(n)   SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n))
1046 #define SH7750_DMATCR0_P4     SH7750_DMATCR(0)
1047 #define SH7750_DMATCR1_P4     SH7750_DMATCR(1)
1048 #define SH7750_DMATCR2_P4     SH7750_DMATCR(2)
1049 #define SH7750_DMATCR3_P4     SH7750_DMATCR(3)
1050 #define SH7750_DMATCR0_A7     SH7750_DMATCR_A7(0)
1051 #define SH7750_DMATCR1_A7     SH7750_DMATCR_A7(1)
1052 #define SH7750_DMATCR2_A7     SH7750_DMATCR_A7(2)
1053 #define SH7750_DMATCR3_A7     SH7750_DMATCR_A7(3)
1054
1055 /* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */
1056 #define SH7750_CHCR_REGOFS(n)  (0xA0000C + ((n) * 16)) /* offset */
1057 #define SH7750_CHCR(n)        SH7750_P4_REG32(SH7750_CHCR_REGOFS(n))
1058 #define SH7750_CHCR_A7(n)     SH7750_A7_REG32(SH7750_CHCR_REGOFS(n))
1059 #define SH7750_CHCR0          SH7750_CHCR(0)
1060 #define SH7750_CHCR1          SH7750_CHCR(1)
1061 #define SH7750_CHCR2          SH7750_CHCR(2)
1062 #define SH7750_CHCR3          SH7750_CHCR(3)
1063 #define SH7750_CHCR0_A7       SH7750_CHCR_A7(0)
1064 #define SH7750_CHCR1_A7       SH7750_CHCR_A7(1)
1065 #define SH7750_CHCR2_A7       SH7750_CHCR_A7(2)
1066 #define SH7750_CHCR3_A7       SH7750_CHCR_A7(3)
1067
1068 #define SH7750_CHCR_SSA       0xE0000000 /* Source Address Space Attribute */
1069 #define SH7750_CHCR_SSA_PCMCIA  0x00000000 /* Reserved in PCMCIA access */
1070 #define SH7750_CHCR_SSA_DYNBSZ  0x20000000 /* Dynamic Bus Sizing I/O space */
1071 #define SH7750_CHCR_SSA_IO8     0x40000000 /* 8-bit I/O space */
1072 #define SH7750_CHCR_SSA_IO16    0x60000000 /* 16-bit I/O space */
1073 #define SH7750_CHCR_SSA_CMEM8   0x80000000 /* 8-bit common memory space */
1074 #define SH7750_CHCR_SSA_CMEM16  0xA0000000 /* 16-bit common memory space */
1075 #define SH7750_CHCR_SSA_AMEM8   0xC0000000 /* 8-bit attribute memory space */
1076 #define SH7750_CHCR_SSA_AMEM16  0xE0000000 /* 16-bit attribute memory space */
1077
1078 #define SH7750_CHCR_STC       0x10000000 /* Source Addr Wait Control Select */
1079                                          /*   specifies CS5 or CS6 space wait */
1080                                          /*   control for PCMCIA access */
1081
1082 #define SH7750_CHCR_DSA       0x0E000000 /* Source Address Space Attribute */
1083 #define SH7750_CHCR_DSA_PCMCIA  0x00000000 /* Reserved in PCMCIA access */
1084 #define SH7750_CHCR_DSA_DYNBSZ  0x02000000 /* Dynamic Bus Sizing I/O space */
1085 #define SH7750_CHCR_DSA_IO8     0x04000000 /* 8-bit I/O space */
1086 #define SH7750_CHCR_DSA_IO16    0x06000000 /* 16-bit I/O space */
1087 #define SH7750_CHCR_DSA_CMEM8   0x08000000 /* 8-bit common memory space */
1088 #define SH7750_CHCR_DSA_CMEM16  0x0A000000 /* 16-bit common memory space */
1089 #define SH7750_CHCR_DSA_AMEM8   0x0C000000 /* 8-bit attribute memory space */
1090 #define SH7750_CHCR_DSA_AMEM16  0x0E000000 /* 16-bit attribute memory space */
1091
1092 #define SH7750_CHCR_DTC       0x01000000 /* Destination Address Wait Control */
1093                                          /*   Select, specifies CS5 or CS6 */
1094                                          /*   space wait control for PCMCIA */
1095                                          /*   access */
1096
1097 #define SH7750_CHCR_DS        0x00080000 /* DREQ\ Select : */
1098 #define SH7750_CHCR_DS_LOWLVL 0x00000000 /*   Low Level Detection */
1099 #define SH7750_CHCR_DS_FALL   0x00080000 /*   Falling Edge Detection */
1100
1101 #define SH7750_CHCR_RL        0x00040000 /* Request Check Level: */
1102 #define SH7750_CHCR_RL_ACTH   0x00000000 /*   DRAK is an active high out */
1103 #define SH7750_CHCR_RL_ACTL   0x00040000 /*   DRAK is an active low out */
1104
1105 #define SH7750_CHCR_AM        0x00020000 /* Acknowledge Mode: */
1106 #define SH7750_CHCR_AM_RD     0x00000000 /*   DACK is output in read cycle */
1107 #define SH7750_CHCR_AM_WR     0x00020000 /*   DACK is output in write cycle */
1108
1109 #define SH7750_CHCR_AL        0x00010000 /* Acknowledge Level: */
1110 #define SH7750_CHCR_AL_ACTH   0x00000000 /*   DACK is an active high out */
1111 #define SH7750_CHCR_AL_ACTL   0x00010000 /*   DACK is an active low out */
1112
1113 #define SH7750_CHCR_DM        0x0000C000 /* Destination Address Mode: */
1114 #define SH7750_CHCR_DM_FIX    0x00000000 /*   Destination Addr Fixed */
1115 #define SH7750_CHCR_DM_INC    0x00004000 /*   Destination Addr Incremented */
1116 #define SH7750_CHCR_DM_DEC    0x00008000 /*   Destination Addr Decremented */
1117
1118 #define SH7750_CHCR_SM        0x00003000 /* Source Address Mode: */
1119 #define SH7750_CHCR_SM_FIX    0x00000000 /*   Source Addr Fixed */
1120 #define SH7750_CHCR_SM_INC    0x00001000 /*   Source Addr Incremented */
1121 #define SH7750_CHCR_SM_DEC    0x00002000 /*   Source Addr Decremented */
1122
1123 #define SH7750_CHCR_RS        0x00000F00 /* Request Source Select: */
1124 #define SH7750_CHCR_RS_ER_DA_EA_TO_EA   0x000 /* External Request, Dual Addr */
1125                                               /*   Mode, External Addr Space */
1126                                               /*   -> External Addr Space) */
1127 #define SH7750_CHCR_RS_ER_SA_EA_TO_ED   0x200 /* External Request, Single */
1128                                               /*   Address Mode (Ext. Addr */
1129                                               /*   Space -> External Device) */
1130 #define SH7750_CHCR_RS_ER_SA_ED_TO_EA   0x300 /* External Request, Single */
1131                                               /*   Address Mode, (External */
1132                                               /*   Device -> External Addr */
1133                                               /*   Space) */
1134 #define SH7750_CHCR_RS_AR_EA_TO_EA      0x400 /* Auto-Request (External Addr */
1135                                               /*   Space -> Ext. Addr Space) */
1136
1137 #define SH7750_CHCR_RS_AR_EA_TO_OCP     0x500 /* Auto-Request (External Addr */
1138                                               /*   Space -> On-chip */
1139                                               /*   Peripheral Module) */
1140 #define SH7750_CHCR_RS_AR_OCP_TO_EA     0x600 /* Auto-Request (On-chip */
1141                                               /*   Peripheral Module -> */
1142                                               /*   External Addr Space */
1143 #define SH7750_CHCR_RS_SCITX_EA_TO_SC   0x800 /* SCI Transmit-Data-Empty intr */
1144                                               /*   transfer request (external */
1145                                               /*   address space -> SCTDR1) */
1146 #define SH7750_CHCR_RS_SCIRX_SC_TO_EA   0x900 /* SCI Receive-Data-Full intr */
1147                                               /*   transfer request (SCRDR1 */
1148                                               /*   -> External Addr Space) */
1149 #define SH7750_CHCR_RS_SCIFTX_EA_TO_SC  0xA00 /* SCIF TX-Data-Empty intr */
1150                                               /*   transfer request (external */
1151                                               /*   address space -> SCFTDR1) */
1152 #define SH7750_CHCR_RS_SCIFRX_SC_TO_EA  0xB00 /* SCIF Receive-Data-Full intr */
1153                                               /*   transfer request (SCFRDR2 */
1154                                               /*   -> External Addr Space) */
1155 #define SH7750_CHCR_RS_TMU2_EA_TO_EA    0xC00 /* TMU Channel 2 (input capture */
1156                                               /*   interrupt), (external */
1157                                               /*   address space -> external */
1158                                               /*   address space) */
1159 #define SH7750_CHCR_RS_TMU2_EA_TO_OCP   0xD00 /* TMU Channel 2 (input capture */
1160                                               /*   interrupt), (external */
1161                                               /*   address space -> on-chip */
1162                                               /*   peripheral module) */
1163 #define SH7750_CHCR_RS_TMU2_OCP_TO_EA   0xE00 /* TMU Channel 2 (input capture */
1164                                               /*   interrupt), (on-chip */
1165                                               /*   peripheral module -> */
1166                                               /*   external address space) */
1167
1168 #define SH7750_CHCR_TM        0x00000080 /* Transmit mode: */
1169 #define SH7750_CHCR_TM_CSTEAL 0x00000000 /*     Cycle Steal Mode */
1170 #define SH7750_CHCR_TM_BURST  0x00000080 /*     Burst Mode */
1171
1172 #define SH7750_CHCR_TS        0x00000070 /* Transmit Size: */
1173 #define SH7750_CHCR_TS_QUAD   0x00000000 /*     Quadword Size (64 bits) */
1174 #define SH7750_CHCR_TS_BYTE   0x00000010 /*     Byte Size (8 bit) */
1175 #define SH7750_CHCR_TS_WORD   0x00000020 /*     Word Size (16 bit) */
1176 #define SH7750_CHCR_TS_LONG   0x00000030 /*     Longword Size (32 bit) */
1177 #define SH7750_CHCR_TS_BLOCK  0x00000040 /*     32-byte block transfer */
1178
1179 #define SH7750_CHCR_IE        0x00000004 /* Interrupt Enable */
1180 #define SH7750_CHCR_TE        0x00000002 /* Transfer End */
1181 #define SH7750_CHCR_DE        0x00000001 /* DMAC Enable */
1182
1183 /* DMA Operation Register - DMAOR */
1184 #define SH7750_DMAOR_REGOFS   0xA00040 /* offset */
1185 #define SH7750_DMAOR          SH7750_P4_REG32(SH7750_DMAOR_REGOFS)
1186 #define SH7750_DMAOR_A7       SH7750_A7_REG32(SH7750_DMAOR_REGOFS)
1187
1188 #define SH7750_DMAOR_DDT      0x00008000 /* On-Demand Data Transfer Mode */
1189
1190 #define SH7750_DMAOR_PR       0x00000300 /* Priority Mode: */
1191 #define SH7750_DMAOR_PR_0123  0x00000000 /*     CH0 > CH1 > CH2 > CH3 */
1192 #define SH7750_DMAOR_PR_0231  0x00000100 /*     CH0 > CH2 > CH3 > CH1 */
1193 #define SH7750_DMAOR_PR_2013  0x00000200 /*     CH2 > CH0 > CH1 > CH3 */
1194 #define SH7750_DMAOR_PR_RR    0x00000300 /*     Round-robin mode */
1195
1196 #define SH7750_DMAOR_COD      0x00000010 /* Check Overrun for DREQ\ */
1197 #define SH7750_DMAOR_AE       0x00000004 /* Address Error flag */
1198 #define SH7750_DMAOR_NMIF     0x00000002 /* NMI Flag */
1199 #define SH7750_DMAOR_DME      0x00000001 /* DMAC Master Enable */
1200
1201 /*
1202  * I/O Ports
1203  */
1204 /* Port Control Register A - PCTRA */
1205 #define SH7750_PCTRA_REGOFS   0x80002C /* offset */
1206 #define SH7750_PCTRA          SH7750_P4_REG32(SH7750_PCTRA_REGOFS)
1207 #define SH7750_PCTRA_A7       SH7750_A7_REG32(SH7750_PCTRA_REGOFS)
1208
1209 #define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */
1210 #define SH7750_PCTRA_PBNPUP(n) (1 << ((n) * 2 + 1)) /* Bit n is not pulled up */
1211 #define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */
1212 #define SH7750_PCTRA_PBOUT(n) (1 << ((n) * 2)) /* Bit n is an output */
1213
1214 /* Port Data Register A - PDTRA(half) */
1215 #define SH7750_PDTRA_REGOFS   0x800030 /* offset */
1216 #define SH7750_PDTRA          SH7750_P4_REG32(SH7750_PDTRA_REGOFS)
1217 #define SH7750_PDTRA_A7       SH7750_A7_REG32(SH7750_PDTRA_REGOFS)
1218
1219 #define SH7750_PDTRA_BIT(n) (1 << (n))
1220
1221 /* Port Control Register B - PCTRB */
1222 #define SH7750_PCTRB_REGOFS   0x800040 /* offset */
1223 #define SH7750_PCTRB          SH7750_P4_REG32(SH7750_PCTRB_REGOFS)
1224 #define SH7750_PCTRB_A7       SH7750_A7_REG32(SH7750_PCTRB_REGOFS)
1225
1226 #define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */
1227 #define SH7750_PCTRB_PBNPUP(n) (1 << ((n - 16) * 2 + 1)) /* Bit n is not pulled up */
1228 #define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */
1229 #define SH7750_PCTRB_PBOUT(n) (1 << ((n - 16) * 2)) /* Bit n is an output */
1230
1231 /* Port Data Register B - PDTRB(half) */
1232 #define SH7750_PDTRB_REGOFS   0x800044 /* offset */
1233 #define SH7750_PDTRB          SH7750_P4_REG32(SH7750_PDTRB_REGOFS)
1234 #define SH7750_PDTRB_A7       SH7750_A7_REG32(SH7750_PDTRB_REGOFS)
1235
1236 #define SH7750_PDTRB_BIT(n) (1 << ((n) - 16))
1237
1238 /* GPIO Interrupt Control Register - GPIOIC(half) */
1239 #define SH7750_GPIOIC_REGOFS  0x800048 /* offset */
1240 #define SH7750_GPIOIC         SH7750_P4_REG32(SH7750_GPIOIC_REGOFS)
1241 #define SH7750_GPIOIC_A7      SH7750_A7_REG32(SH7750_GPIOIC_REGOFS)
1242
1243 #define SH7750_GPIOIC_PTIREN(n) (1 << (n)) /* Port n is used as a GPIO int */
1244
1245 /*
1246  * Interrupt Controller - INTC
1247  */
1248 /* Interrupt Control Register - ICR (half) */
1249 #define SH7750_ICR_REGOFS     0xD00000 /* offset */
1250 #define SH7750_ICR            SH7750_P4_REG32(SH7750_ICR_REGOFS)
1251 #define SH7750_ICR_A7         SH7750_A7_REG32(SH7750_ICR_REGOFS)
1252
1253 #define SH7750_ICR_NMIL       0x8000 /* NMI Input Level */
1254 #define SH7750_ICR_MAI        0x4000 /* NMI Interrupt Mask */
1255
1256 #define SH7750_ICR_NMIB       0x0200 /* NMI Block Mode: */
1257 #define SH7750_ICR_NMIB_BLK   0x0000 /*   NMI requests held pending while */
1258                                      /*     SR.BL bit is set to 1 */
1259 #define SH7750_ICR_NMIB_NBLK  0x0200 /*   NMI requests detected when SR.BL */
1260                                      /*     bit set to 1 */
1261
1262 #define SH7750_ICR_NMIE       0x0100 /* NMI Edge Select: */
1263 #define SH7750_ICR_NMIE_FALL  0x0000 /*   Interrupt request detected on */
1264                                      /*     falling edge of NMI input */
1265 #define SH7750_ICR_NMIE_RISE  0x0100 /*   Interrupt request detected on */
1266                                      /*     rising edge of NMI input */
1267
1268 #define SH7750_ICR_IRLM       0x0080 /* IRL Pin Mode: */
1269 #define SH7750_ICR_IRLM_ENC   0x0000 /*   IRL\ pins used as a level-encoded */
1270                                      /*     interrupt requests */
1271 #define SH7750_ICR_IRLM_RAW   0x0080 /*   IRL\ pins used as a four */
1272                                      /*     independent interrupt requests */
1273
1274 /*
1275  * User Break Controller registers
1276  */
1277 #define SH7750_BARA           0x200000 /* Break address regiser A */
1278 #define SH7750_BAMRA          0x200004 /* Break address mask regiser A */
1279 #define SH7750_BBRA           0x200008 /* Break bus cycle regiser A */
1280 #define SH7750_BARB           0x20000c /* Break address regiser B */
1281 #define SH7750_BAMRB          0x200010 /* Break address mask regiser B */
1282 #define SH7750_BBRB           0x200014 /* Break bus cycle regiser B */
1283 #define SH7750_BASRB          0x000018 /* Break ASID regiser B */
1284 #define SH7750_BDRB           0x200018 /* Break data regiser B */
1285 #define SH7750_BDMRB          0x20001c /* Break data mask regiser B */
1286 #define SH7750_BRCR           0x200020 /* Break control register */
1287
1288 #define SH7750_BRCR_UDBE        0x0001 /* User break debug enable bit */
1289
1290 /*
1291  * Missing in RTEMS, added for QEMU
1292  */
1293 #define SH7750_BCR3_A7       0x1f800050
1294 #define SH7750_BCR4_A7       0x1e0a00f0
1295
1296 #endif