| blob | d45f245a6718daf02ea6c8a34395aaa77450e6e3 |
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
21 /* CPU / CPU family specific config register values. */
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1U << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1U << CP0C2_M))
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
48 #define MIPS_CONFIG4 \
49 ((0 << CP0C4_M))
51 #define MIPS_CONFIG5 \
52 ((0 << CP0C5_M))
54 /*****************************************************************************/
55 /* MIPS CPU definitions */
56 const mips_def_t mips_defs[] =
57 {
58 {
59 .name = "4Kc",
60 .CP0_PRid = 0x00018000,
61 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
62 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
63 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
64 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
65 (0 << CP0C1_CA),
66 .CP0_Config2 = MIPS_CONFIG2,
67 .CP0_Config3 = MIPS_CONFIG3,
68 .CP0_LLAddr_rw_bitmask = 0,
69 .CP0_LLAddr_shift = 4,
70 .SYNCI_Step = 32,
71 .CCRes = 2,
72 .CP0_Status_rw_bitmask = 0x1278FF17,
73 .SEGBITS = 32,
74 .PABITS = 32,
75 .insn_flags = CPU_MIPS32R1,
76 .mmu_type = MMU_TYPE_R4000,
77 },
78 {
79 .name = "4Km",
80 .CP0_PRid = 0x00018300,
81 /* Config1 implemented, fixed mapping MMU,
82 no virtual icache, uncached coherency. */
83 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
84 .CP0_Config1 = MIPS_CONFIG1 |
85 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
86 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
87 (1 << CP0C1_CA),
88 .CP0_Config2 = MIPS_CONFIG2,
89 .CP0_Config3 = MIPS_CONFIG3,
90 .CP0_LLAddr_rw_bitmask = 0,
91 .CP0_LLAddr_shift = 4,
92 .SYNCI_Step = 32,
93 .CCRes = 2,
94 .CP0_Status_rw_bitmask = 0x1258FF17,
95 .SEGBITS = 32,
96 .PABITS = 32,
97 .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
98 .mmu_type = MMU_TYPE_FMT,
99 },
100 {
101 .name = "4KEcR1",
102 .CP0_PRid = 0x00018400,
103 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
104 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
105 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
106 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
107 (0 << CP0C1_CA),
108 .CP0_Config2 = MIPS_CONFIG2,
109 .CP0_Config3 = MIPS_CONFIG3,
110 .CP0_LLAddr_rw_bitmask = 0,
111 .CP0_LLAddr_shift = 4,
112 .SYNCI_Step = 32,
113 .CCRes = 2,
114 .CP0_Status_rw_bitmask = 0x1278FF17,
115 .SEGBITS = 32,
116 .PABITS = 32,
117 .insn_flags = CPU_MIPS32R1,
118 .mmu_type = MMU_TYPE_R4000,
119 },
120 {
121 .name = "4KEmR1",
122 .CP0_PRid = 0x00018500,
123 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
124 .CP0_Config1 = MIPS_CONFIG1 |
125 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
126 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
127 (1 << CP0C1_CA),
128 .CP0_Config2 = MIPS_CONFIG2,
129 .CP0_Config3 = MIPS_CONFIG3,
130 .CP0_LLAddr_rw_bitmask = 0,
131 .CP0_LLAddr_shift = 4,
132 .SYNCI_Step = 32,
133 .CCRes = 2,
134 .CP0_Status_rw_bitmask = 0x1258FF17,
135 .SEGBITS = 32,
136 .PABITS = 32,
137 .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
138 .mmu_type = MMU_TYPE_FMT,
139 },
140 {
141 .name = "4KEc",
142 .CP0_PRid = 0x00019000,
143 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
144 (MMU_TYPE_R4000 << CP0C0_MT),
145 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
146 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
147 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
148 (0 << CP0C1_CA),
149 .CP0_Config2 = MIPS_CONFIG2,
150 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
151 .CP0_LLAddr_rw_bitmask = 0,
152 .CP0_LLAddr_shift = 4,
153 .SYNCI_Step = 32,
154 .CCRes = 2,
155 .CP0_Status_rw_bitmask = 0x1278FF17,
156 .SEGBITS = 32,
157 .PABITS = 32,
158 .insn_flags = CPU_MIPS32R2,
159 .mmu_type = MMU_TYPE_R4000,
160 },
161 {
162 .name = "4KEm",
163 .CP0_PRid = 0x00019100,
164 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
165 (MMU_TYPE_FMT << CP0C0_MT),
166 .CP0_Config1 = MIPS_CONFIG1 |
167 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
168 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
169 (1 << CP0C1_CA),
170 .CP0_Config2 = MIPS_CONFIG2,
171 .CP0_Config3 = MIPS_CONFIG3,
172 .CP0_LLAddr_rw_bitmask = 0,
173 .CP0_LLAddr_shift = 4,
174 .SYNCI_Step = 32,
175 .CCRes = 2,
176 .CP0_Status_rw_bitmask = 0x1258FF17,
177 .SEGBITS = 32,
178 .PABITS = 32,
179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
180 .mmu_type = MMU_TYPE_FMT,
181 },
182 {
183 .name = "24Kc",
184 .CP0_PRid = 0x00019300,
185 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
186 (MMU_TYPE_R4000 << CP0C0_MT),
187 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
188 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
189 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
190 (1 << CP0C1_CA),
191 .CP0_Config2 = MIPS_CONFIG2,
192 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
193 .CP0_LLAddr_rw_bitmask = 0,
194 .CP0_LLAddr_shift = 4,
195 .SYNCI_Step = 32,
196 .CCRes = 2,
197 /* No DSP implemented. */
198 .CP0_Status_rw_bitmask = 0x1278FF1F,
199 .SEGBITS = 32,
200 .PABITS = 32,
201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
202 .mmu_type = MMU_TYPE_R4000,
203 },
204 {
205 .name = "24KEc",
206 .CP0_PRid = 0x00019600,
207 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
208 (MMU_TYPE_R4000 << CP0C0_MT),
209 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
210 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
211 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
212 (1 << CP0C1_CA),
213 .CP0_Config2 = MIPS_CONFIG2,
214 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
215 .CP0_LLAddr_rw_bitmask = 0,
216 .CP0_LLAddr_shift = 4,
217 .SYNCI_Step = 32,
218 .CCRes = 2,
219 /* we have a DSP, but no FPU */
220 .CP0_Status_rw_bitmask = 0x1378FF1F,
221 .SEGBITS = 32,
222 .PABITS = 32,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
224 .mmu_type = MMU_TYPE_R4000,
225 },
226 {
227 .name = "24Kf",
228 .CP0_PRid = 0x00019300,
229 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
230 (MMU_TYPE_R4000 << CP0C0_MT),
231 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
232 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
233 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
234 (1 << CP0C1_CA),
235 .CP0_Config2 = MIPS_CONFIG2,
236 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
237 .CP0_LLAddr_rw_bitmask = 0,
238 .CP0_LLAddr_shift = 4,
239 .SYNCI_Step = 32,
240 .CCRes = 2,
241 /* No DSP implemented. */
242 .CP0_Status_rw_bitmask = 0x3678FF1F,
243 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
245 .CP1_fcr31 = 0,
246 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
247 .SEGBITS = 32,
248 .PABITS = 32,
249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
250 .mmu_type = MMU_TYPE_R4000,
251 },
252 {
253 .name = "34Kf",
254 .CP0_PRid = 0x00019500,
255 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
256 (MMU_TYPE_R4000 << CP0C0_MT),
257 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
258 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
259 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
260 (1 << CP0C1_CA),
261 .CP0_Config2 = MIPS_CONFIG2,
262 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
263 (1 << CP0C3_DSPP),
264 .CP0_LLAddr_rw_bitmask = 0,
265 .CP0_LLAddr_shift = 0,
266 .SYNCI_Step = 32,
267 .CCRes = 2,
268 .CP0_Status_rw_bitmask = 0x3778FF1F,
269 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
270 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
271 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
272 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
273 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
274 (0xff << CP0TCSt_TASID),
275 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
277 .CP1_fcr31 = 0,
278 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
279 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
280 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
281 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
282 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
283 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
284 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
285 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
286 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
288 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
289 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
290 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
291 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
292 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
293 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
294 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
295 .SEGBITS = 32,
296 .PABITS = 32,
297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
298 .mmu_type = MMU_TYPE_R4000,
299 },
300 {
301 .name = "74Kf",
302 .CP0_PRid = 0x00019700,
303 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
304 (MMU_TYPE_R4000 << CP0C0_MT),
305 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
306 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
307 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
308 (1 << CP0C1_CA),
309 .CP0_Config2 = MIPS_CONFIG2,
310 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
311 (1 << CP0C3_VInt),
312 .CP0_LLAddr_rw_bitmask = 0,
313 .CP0_LLAddr_shift = 4,
314 .SYNCI_Step = 32,
315 .CCRes = 2,
316 .CP0_Status_rw_bitmask = 0x3778FF1F,
317 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
319 .CP1_fcr31 = 0,
320 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
321 .SEGBITS = 32,
322 .PABITS = 32,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
324 .mmu_type = MMU_TYPE_R4000,
325 },
326 {
327 .name = "M14K",
328 .CP0_PRid = 0x00019b00,
329 /* Config1 implemented, fixed mapping MMU,
330 no virtual icache, uncached coherency. */
331 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
332 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
333 .CP0_Config1 = MIPS_CONFIG1,
334 .CP0_Config2 = MIPS_CONFIG2,
335 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt) |
336 (1 << CP0C3_M),
337 .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
338 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
339 .CP0_Config7 = 1 << CP0C7_WII,
340 .CP0_LLAddr_rw_bitmask = 0,
341 .CP0_LLAddr_shift = 4,
342 .SYNCI_Step = 32,
343 .CCRes = 2,
344 .CP0_Status_rw_bitmask = 0x1258FF17,
345 .SEGBITS = 32,
346 .PABITS = 32,
347 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
348 .mmu_type = MMU_TYPE_FMT,
349 },
350 {
351 .name = "M14Kc",
352 /* This is the TLB-based MMU core. */
353 .CP0_PRid = 0x00019c00,
354 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
355 (MMU_TYPE_R4000 << CP0C0_MT),
356 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
357 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
358 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
359 .CP0_Config2 = MIPS_CONFIG2,
360 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt) |
361 (1 << CP0C3_M),
362 .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
363 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
364 .CP0_Config7 = 1 << CP0C7_WII,
365 .CP0_LLAddr_rw_bitmask = 0,
366 .CP0_LLAddr_shift = 4,
367 .SYNCI_Step = 32,
368 .CCRes = 2,
369 .CP0_Status_rw_bitmask = 0x1278FF17,
370 .SEGBITS = 32,
371 .PABITS = 32,
372 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
373 .mmu_type = MMU_TYPE_R4000,
374 },
375 {
376 /* FIXME:
377 * Config3: VZ, CTXTC, CDMM, TL
378 * Config4: MMUExtDef
379 * Config5: MRP
380 * */
381 .name = "P5600",
382 .CP0_PRid = 0x0001A800,
383 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
384 (MMU_TYPE_R4000 << CP0C0_MT),
385 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
386 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
387 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
388 (1 << CP0C1_PC) | (1 << CP0C1_FP),
389 .CP0_Config2 = MIPS_CONFIG2,
390 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
391 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
392 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
393 (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
394 (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
395 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
396 (0x1c << CP0C4_KScrExist),
397 .CP0_Config4_rw_bitmask = 0,
398 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
399 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
400 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
401 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
402 (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
403 .CP0_Config7 = 1 << CP0C7_WII,
404 .CP0_LLAddr_rw_bitmask = 0,
405 .CP0_LLAddr_shift = 0,
406 .SYNCI_Step = 32,
407 .CCRes = 2,
408 .CP0_Status_rw_bitmask = 0x3C68FF1F,
409 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
410 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
411 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
412 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
413 (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
414 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
415 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
416 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
417 .SEGBITS = 32,
418 .PABITS = 40,
419 .insn_flags = CPU_MIPS32R5,
420 .mmu_type = MMU_TYPE_R4000,
421 },
422 {
423 /* A generic CPU supporting MIPS32 Release 6 ISA.
424 FIXME: Support IEEE 754-2008 FP.
425 Eventually this should be replaced by a real CPU model. */
426 .name = "mips32r6-generic",
427 .CP0_PRid = 0x00010000,
428 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
429 (MMU_TYPE_R4000 << CP0C0_MT),
430 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
431 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
432 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
433 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
434 .CP0_Config2 = MIPS_CONFIG2,
435 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
436 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
437 (1 << CP0C3_RXI) | (1U << CP0C3_M),
438 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
439 (3 << CP0C4_IE) | (1U << CP0C4_M),
440 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
441 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
442 (1 << CP0C5_UFE),
443 .CP0_LLAddr_rw_bitmask = 0,
444 .CP0_LLAddr_shift = 0,
445 .SYNCI_Step = 32,
446 .CCRes = 2,
447 .CP0_Status_rw_bitmask = 0x3058FF1F,
448 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
449 (1U << CP0PG_RIE),
450 .CP0_PageGrain_rw_bitmask = 0,
451 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
452 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
453 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
454 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
455 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
456 .SEGBITS = 32,
457 .PABITS = 32,
458 .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
459 .mmu_type = MMU_TYPE_R4000,
460 },
461 {
462 .name = "I7200",
463 .CP0_PRid = 0x00010000,
464 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
465 (MMU_TYPE_R4000 << CP0C0_MT),
466 .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
467 (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
468 (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
469 (1 << CP0C1_EP),
470 .CP0_Config2 = MIPS_CONFIG2,
471 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
472 (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |
473 (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
474 (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
475 (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
476 (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |
477 (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),
478 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
479 (2 << CP0C4_IE) | (1U << CP0C4_M),
480 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
481 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
482 (1 << CP0C5_UFE),
483 .CP0_LLAddr_rw_bitmask = 0,
484 .CP0_LLAddr_shift = 0,
485 .SYNCI_Step = 32,
486 .CCRes = 2,
487 .CP0_Status_rw_bitmask = 0x3158FF1F,
488 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
489 (1U << CP0PG_RIE),
490 .CP0_PageGrain_rw_bitmask = 0,
491 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
492 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
493 (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
494 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
495 .SEGBITS = 32,
496 .PABITS = 32,
497 .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 |
498 ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT,
499 .mmu_type = MMU_TYPE_R4000,
500 },
501 #if defined(TARGET_MIPS64)
502 {
503 .name = "R4000",
504 .CP0_PRid = 0x00000400,
505 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
506 .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
507 (2 << CP0C0_K0),
508 /* Note: Config1 is only used internally, the R4000 has only Config0. */
509 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
510 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
511 .CP0_LLAddr_shift = 4,
512 .SYNCI_Step = 16,
513 .CCRes = 2,
514 .CP0_Status_rw_bitmask = 0x3678FFFF,
515 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
516 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
517 .CP1_fcr31 = 0,
518 .CP1_fcr31_rw_bitmask = 0x0183FFFF,
519 .SEGBITS = 40,
520 .PABITS = 36,
521 .insn_flags = CPU_MIPS3,
522 .mmu_type = MMU_TYPE_R4000,
523 },
524 {
525 .name = "VR5432",
526 .CP0_PRid = 0x00005400,
527 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
528 .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
529 (2 << CP0C0_K0),
530 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
531 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
532 .CP0_LLAddr_shift = 4,
533 .SYNCI_Step = 16,
534 .CCRes = 2,
535 .CP0_Status_rw_bitmask = 0x3678FFFF,
536 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
537 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
538 .CP1_fcr31 = 0,
539 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
540 .SEGBITS = 40,
541 .PABITS = 32,
542 .insn_flags = CPU_MIPS4 | INSN_VR54XX,
543 .mmu_type = MMU_TYPE_R4000,
544 },
545 {
546 .name = "5Kc",
547 .CP0_PRid = 0x00018100,
548 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
549 (MMU_TYPE_R4000 << CP0C0_MT),
550 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
551 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
552 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
553 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
554 .CP0_Config2 = MIPS_CONFIG2,
555 .CP0_Config3 = MIPS_CONFIG3,
556 .CP0_LLAddr_rw_bitmask = 0,
557 .CP0_LLAddr_shift = 4,
558 .SYNCI_Step = 32,
559 .CCRes = 2,
560 .CP0_Status_rw_bitmask = 0x12F8FFFF,
561 .SEGBITS = 42,
562 .PABITS = 36,
563 .insn_flags = CPU_MIPS64R1,
564 .mmu_type = MMU_TYPE_R4000,
565 },
566 {
567 .name = "5Kf",
568 .CP0_PRid = 0x00018100,
569 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
570 (MMU_TYPE_R4000 << CP0C0_MT),
571 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
572 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
573 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
574 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
575 .CP0_Config2 = MIPS_CONFIG2,
576 .CP0_Config3 = MIPS_CONFIG3,
577 .CP0_LLAddr_rw_bitmask = 0,
578 .CP0_LLAddr_shift = 4,
579 .SYNCI_Step = 32,
580 .CCRes = 2,
581 .CP0_Status_rw_bitmask = 0x36F8FFFF,
582 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
583 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
584 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
585 .CP1_fcr31 = 0,
586 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
587 .SEGBITS = 42,
588 .PABITS = 36,
589 .insn_flags = CPU_MIPS64R1,
590 .mmu_type = MMU_TYPE_R4000,
591 },
592 {
593 .name = "20Kc",
594 /* We emulate a later version of the 20Kc, earlier ones had a broken
595 WAIT instruction. */
596 .CP0_PRid = 0x000182a0,
597 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
598 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
599 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
600 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
601 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
602 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
603 .CP0_Config2 = MIPS_CONFIG2,
604 .CP0_Config3 = MIPS_CONFIG3,
605 .CP0_LLAddr_rw_bitmask = 0,
606 .CP0_LLAddr_shift = 0,
607 .SYNCI_Step = 32,
608 .CCRes = 1,
609 .CP0_Status_rw_bitmask = 0x36FBFFFF,
610 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
611 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
612 (1 << FCR0_D) | (1 << FCR0_S) |
613 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
614 .CP1_fcr31 = 0,
615 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
616 .SEGBITS = 40,
617 .PABITS = 36,
618 .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D,
619 .mmu_type = MMU_TYPE_R4000,
620 },
621 {
622 /* A generic CPU providing MIPS64 Release 2 features.
623 FIXME: Eventually this should be replaced by a real CPU model. */
624 .name = "MIPS64R2-generic",
625 .CP0_PRid = 0x00010000,
626 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
627 (MMU_TYPE_R4000 << CP0C0_MT),
628 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
629 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
630 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
631 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
632 .CP0_Config2 = MIPS_CONFIG2,
633 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
634 .CP0_LLAddr_rw_bitmask = 0,
635 .CP0_LLAddr_shift = 0,
636 .SYNCI_Step = 32,
637 .CCRes = 2,
638 .CP0_Status_rw_bitmask = 0x36FBFFFF,
639 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
640 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
641 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
642 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
643 .CP1_fcr31 = 0,
644 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
645 .SEGBITS = 42,
646 .PABITS = 36,
647 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
648 .mmu_type = MMU_TYPE_R4000,
649 },
650 {
651 .name = "5KEc",
652 .CP0_PRid = 0x00018900,
653 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
654 (MMU_TYPE_R4000 << CP0C0_MT),
655 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
656 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
657 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
658 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
659 .CP0_Config2 = MIPS_CONFIG2,
660 .CP0_Config3 = MIPS_CONFIG3,
661 .CP0_LLAddr_rw_bitmask = 0,
662 .CP0_LLAddr_shift = 4,
663 .SYNCI_Step = 32,
664 .CCRes = 2,
665 .CP0_Status_rw_bitmask = 0x12F8FFFF,
666 .SEGBITS = 42,
667 .PABITS = 36,
668 .insn_flags = CPU_MIPS64R2,
669 .mmu_type = MMU_TYPE_R4000,
670 },
671 {
672 .name = "5KEf",
673 .CP0_PRid = 0x00018900,
674 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
675 (MMU_TYPE_R4000 << CP0C0_MT),
676 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
677 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
678 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
679 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
680 .CP0_Config2 = MIPS_CONFIG2,
681 .CP0_Config3 = MIPS_CONFIG3,
682 .CP0_LLAddr_rw_bitmask = 0,
683 .CP0_LLAddr_shift = 4,
684 .SYNCI_Step = 32,
685 .CCRes = 2,
686 .CP0_Status_rw_bitmask = 0x36F8FFFF,
687 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
688 (1 << FCR0_D) | (1 << FCR0_S) |
689 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
690 .SEGBITS = 42,
691 .PABITS = 36,
692 .insn_flags = CPU_MIPS64R2,
693 .mmu_type = MMU_TYPE_R4000,
694 },
695 {
696 .name = "I6400",
697 .CP0_PRid = 0x1A900,
698 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
699 (MMU_TYPE_R4000 << CP0C0_MT),
700 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
701 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
702 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
703 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
704 .CP0_Config2 = MIPS_CONFIG2,
705 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
706 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
707 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
708 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
709 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
710 (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
711 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
712 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
713 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
714 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
715 .CP0_LLAddr_rw_bitmask = 0,
716 .CP0_LLAddr_shift = 0,
717 .SYNCI_Step = 32,
718 .CCRes = 2,
719 .CP0_Status_rw_bitmask = 0x30D8FFFF,
720 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
721 (1U << CP0PG_RIE),
722 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
723 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
724 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
725 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
726 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
727 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
728 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
729 .MSAIR = 0x03 << MSAIR_ProcID,
730 .SEGBITS = 48,
731 .PABITS = 48,
732 .insn_flags = CPU_MIPS64R6,
733 .mmu_type = MMU_TYPE_R4000,
734 },
735 {
736 .name = "I6500",
737 .CP0_PRid = 0x1B000,
738 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
739 (MMU_TYPE_R4000 << CP0C0_MT),
740 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
741 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
742 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
743 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
744 .CP0_Config2 = MIPS_CONFIG2,
745 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
746 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
747 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
748 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
749 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
750 (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
751 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
752 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
753 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
754 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
755 .CP0_LLAddr_rw_bitmask = 0,
756 .CP0_LLAddr_shift = 0,
757 .SYNCI_Step = 64,
758 .CCRes = 2,
759 .CP0_Status_rw_bitmask = 0x30D8FFFF,
760 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
761 (1U << CP0PG_RIE),
762 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
763 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
764 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
765 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
766 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
767 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
768 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
769 .MSAIR = 0x03 << MSAIR_ProcID,
770 .SEGBITS = 48,
771 .PABITS = 48,
772 .insn_flags = CPU_MIPS64R6,
773 .mmu_type = MMU_TYPE_R4000,
774 },
775 {
776 .name = "Loongson-2E",
777 .CP0_PRid = 0x6302,
778 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
779 .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
780 (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
781 /* Note: Config1 is only used internally,
782 Loongson-2E has only Config0. */
783 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
784 .SYNCI_Step = 16,
785 .CCRes = 2,
786 .CP0_Status_rw_bitmask = 0x35D0FFFF,
787 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
788 .CP1_fcr31 = 0,
789 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
790 .SEGBITS = 40,
791 .PABITS = 40,
792 .insn_flags = CPU_MIPS3 | INSN_LOONGSON2E,
793 .mmu_type = MMU_TYPE_R4000,
794 },
795 {
796 .name = "Loongson-2F",
797 .CP0_PRid = 0x6303,
798 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
799 .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
800 (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
801 /* Note: Config1 is only used internally,
802 Loongson-2F has only Config0. */
803 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
804 .SYNCI_Step = 16,
805 .CCRes = 2,
806 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
807 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
808 .CP1_fcr31 = 0,
809 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
810 .SEGBITS = 40,
811 .PABITS = 40,
812 .insn_flags = CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI,
813 .mmu_type = MMU_TYPE_R4000,
814 },
815 {
816 .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */
817 .CP0_PRid = 0x6305,
818 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
819 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
820 (MMU_TYPE_R4000 << CP0C0_MT),
821 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
822 (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
823 (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
824 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
825 .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
826 (3 << CP0C2_SA),
827 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
828 .CP0_LLAddr_rw_bitmask = 0,
829 .SYNCI_Step = 32,
830 .CCRes = 2,
831 .CP0_Status_rw_bitmask = 0x74D8FFFF,
832 .CP0_PageGrain = (1 << CP0PG_ELPA),
833 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
834 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
835 (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
836 (0x1 << FCR0_D) | (0x1 << FCR0_S),
837 .CP1_fcr31 = 0,
838 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
839 .SEGBITS = 48,
840 .PABITS = 48,
841 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
842 ASE_LMMI | ASE_LEXT,
843 .mmu_type = MMU_TYPE_R4000,
844 },
845 {
846 .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */
847 .CP0_PRid = 0x14C000,
848 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
849 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
850 (MMU_TYPE_R4000 << CP0C0_MT),
851 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
852 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
853 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
854 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
855 .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
856 (15 << CP0C2_SA),
857 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
858 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
859 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
860 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
861 (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
862 .CP0_Config4_rw_bitmask = 0,
863 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
864 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
865 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
866 (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
867 .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
868 (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
869 (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
870 .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
871 (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
872 (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
873 (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
874 (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
875 (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
876 (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
877 (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
878 (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
879 (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
880 (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
881 (1 << CP0C6_DATAPREF),
882 .CP0_Config7 = 0,
883 .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
884 (1 << CP0C7_VFPUCGEN),
885 .CP0_LLAddr_rw_bitmask = 1,
886 .SYNCI_Step = 16,
887 .CCRes = 2,
888 .CP0_Status_rw_bitmask = 0x7DDBFFFF,
889 .CP0_PageGrain = (1 << CP0PG_ELPA),
890 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
891 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
892 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
893 (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
894 (0x1 << FCR0_D) | (0x1 << FCR0_S),
895 .CP1_fcr31 = 0,
896 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
897 .MSAIR = (0x01 << MSAIR_ProcID) | (0x40 << MSAIR_Rev),
898 .SEGBITS = 48,
899 .PABITS = 48,
900 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
901 ASE_LMMI | ASE_LEXT,
902 .mmu_type = MMU_TYPE_R4000,
903 },
904 {
905 /* A generic CPU providing MIPS64 DSP R2 ASE features.
906 FIXME: Eventually this should be replaced by a real CPU model. */
907 .name = "mips64dspr2",
908 .CP0_PRid = 0x00010000,
909 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
910 (MMU_TYPE_R4000 << CP0C0_MT),
911 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
912 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
913 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
914 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
915 .CP0_Config2 = MIPS_CONFIG2,
916 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
917 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
918 .CP0_LLAddr_rw_bitmask = 0,
919 .CP0_LLAddr_shift = 0,
920 .SYNCI_Step = 32,
921 .CCRes = 2,
922 .CP0_Status_rw_bitmask = 0x37FBFFFF,
923 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
924 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
925 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
926 .CP1_fcr31 = 0,
927 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
928 .SEGBITS = 42,
929 .PABITS = 36,
930 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
931 .mmu_type = MMU_TYPE_R4000,
932 },
933 {
934 /*
935 * Octeon 68xx with MIPS64 Cavium Octeon features.
936 */
937 .name = "Octeon68XX",
938 .CP0_PRid = 0x000D9100,
939 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
940 (MMU_TYPE_R4000 << CP0C0_MT),
941 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
942 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
943 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
944 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
945 .CP0_Config2 = MIPS_CONFIG2,
946 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
947 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
948 (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
949 (3U << CP0C4_MMUSizeExt),
950 .CP0_LLAddr_rw_bitmask = 0,
951 .CP0_LLAddr_shift = 4,
952 .CP0_PageGrain = (1 << CP0PG_ELPA),
953 .SYNCI_Step = 32,
954 .CCRes = 2,
955 .CP0_Status_rw_bitmask = 0x12F8FFFF,
956 .SEGBITS = 42,
957 .PABITS = 49,
958 .insn_flags = CPU_MIPS64R2 | INSN_OCTEON,
959 .mmu_type = MMU_TYPE_R4000,
960 },
962 #endif
963 };
964 const int mips_defs_number = ARRAY_SIZE(mips_defs);
966 void mips_cpu_list(void)
967 {
968 int i;
970 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
971 qemu_printf("MIPS '%s'\n", mips_defs[i].name);
972 }
973 }
975 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
976 {
977 int i;
979 for (i = 0; i < MIPS_FPU_MAX; i++)
980 env->fpus[i].fcr0 = def->CP1_fcr0;
982 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
983 }
985 static void mvp_init(CPUMIPSState *env)
986 {
987 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
989 if (!ase_mt_available(env)) {
990 return;
991 }
993 /* MVPConf1 implemented, TLB sharable, no gating storage support,
994 programmable cache partitioning implemented, number of allocatable
995 and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
996 implemented, 5 TCs implemented. */
997 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
998 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
999 // TODO: actually do 2 VPEs.
1000 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
1001 // (0x04 << CP0MVPC0_PTC);
1002 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
1003 (0x00 << CP0MVPC0_PTC);
1004 #if !defined(CONFIG_USER_ONLY)
1005 /* Usermode has no TLB support */
1006 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
1007 #endif
1009 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
1010 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
1011 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
1012 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
1013 (0x1 << CP0MVPC1_PCP1);
1014 }