target/mips/mips-defs.h

   1 #ifndef QEMU_MIPS_DEFS_H
   2 #define QEMU_MIPS_DEFS_H
   3
   4 /* Real pages are variable size... */
   5 #define MIPS_TLB_MAX 128
   6
   7 /*
   8  * bit definitions for insn_flags (ISAs/ASEs flags)
   9  * ------------------------------------------------
  10  */
  11 /*
  12  *   bits 0-23: MIPS base instruction sets
  13  */
  14 #define ISA_MIPS1         0x0000000000000001ULL
  15 #define ISA_MIPS2         0x0000000000000002ULL
  16 #define ISA_MIPS3         0x0000000000000004ULL /* 64-bit */
  17 #define ISA_MIPS4         0x0000000000000008ULL
  18 #define ISA_MIPS5         0x0000000000000010ULL
  19 #define ISA_MIPS_R1       0x0000000000000020ULL
  20 #define ISA_MIPS_R2       0x0000000000000040ULL
  21 #define ISA_MIPS_R3       0x0000000000000080ULL
  22 #define ISA_MIPS_R5       0x0000000000000100ULL
  23 #define ISA_MIPS_R6       0x0000000000000200ULL
  24 #define ISA_NANOMIPS32    0x0000000000008000ULL
  25 /*
  26  *   bits 24-39: MIPS ASEs
  27  */
  28 #define ASE_MIPS16        0x0000000001000000ULL
  29 #define ASE_MIPS3D        0x0000000002000000ULL
  30 #define ASE_MDMX          0x0000000004000000ULL
  31 #define ASE_DSP           0x0000000008000000ULL
  32 #define ASE_DSP_R2        0x0000000010000000ULL
  33 #define ASE_DSP_R3        0x0000000020000000ULL
  34 #define ASE_MT            0x0000000040000000ULL
  35 #define ASE_SMARTMIPS     0x0000000080000000ULL
  36 #define ASE_MICROMIPS     0x0000000100000000ULL
  37 /*
  38  *   bits 40-51: vendor-specific base instruction sets
  39  */
  40 #define INSN_VR54XX       0x0000010000000000ULL
  41 #define INSN_R5900        0x0000020000000000ULL
  42 #define INSN_LOONGSON2E   0x0000040000000000ULL
  43 #define INSN_LOONGSON2F   0x0000080000000000ULL
  44 #define INSN_LOONGSON3A   0x0000100000000000ULL
  45 #define INSN_OCTEON       0x0000200000000000ULL
  46 /*
  47  *   bits 52-63: vendor-specific ASEs
  48  */
  49 /* MultiMedia Instructions defined by R5900 */
  50 #define ASE_MMI           0x0010000000000000ULL
  51 /* MIPS eXtension/enhanced Unit defined by Ingenic */
  52 #define ASE_MXU           0x0020000000000000ULL
  53 /* Loongson MultiMedia Instructions */
  54 #define ASE_LMMI          0x0040000000000000ULL
  55 /* Loongson EXTensions */
  56 #define ASE_LEXT          0x0080000000000000ULL
  57
  58 /* MIPS CPU defines. */
  59 #define CPU_MIPS1       (ISA_MIPS1)
  60 #define CPU_MIPS2       (CPU_MIPS1 | ISA_MIPS2)
  61 #define CPU_MIPS3       (CPU_MIPS2 | ISA_MIPS3)
  62 #define CPU_MIPS4       (CPU_MIPS3 | ISA_MIPS4)
  63 #define CPU_MIPS5       (CPU_MIPS4 | ISA_MIPS5)
  64
  65 #define CPU_MIPS64      (ISA_MIPS3)
  66
  67 /* MIPS Technologies "Release 1" */
  68 #define CPU_MIPS32R1    (CPU_MIPS2 | ISA_MIPS_R1)
  69 #define CPU_MIPS64R1    (CPU_MIPS5 | CPU_MIPS32R1)
  70
  71 /* MIPS Technologies "Release 2" */
  72 #define CPU_MIPS32R2    (CPU_MIPS32R1 | ISA_MIPS_R2)
  73 #define CPU_MIPS64R2    (CPU_MIPS64R1 | CPU_MIPS32R2)
  74
  75 /* MIPS Technologies "Release 3" */
  76 #define CPU_MIPS32R3    (CPU_MIPS32R2 | ISA_MIPS_R3)
  77 #define CPU_MIPS64R3    (CPU_MIPS64R2 | CPU_MIPS32R3)
  78
  79 /* MIPS Technologies "Release 5" */
  80 #define CPU_MIPS32R5    (CPU_MIPS32R3 | ISA_MIPS_R5)
  81 #define CPU_MIPS64R5    (CPU_MIPS64R3 | CPU_MIPS32R5)
  82
  83 /* MIPS Technologies "Release 6" */
  84 #define CPU_MIPS32R6    (CPU_MIPS32R5 | ISA_MIPS_R6)
  85 #define CPU_MIPS64R6    (CPU_MIPS64R5 | CPU_MIPS32R6)
  86
  87 /*
  88  * Strictly follow the architecture standard:
  89  * - Disallow "special" instruction handling for PMON/SPIM.
  90  * Note that we still maintain Count/Compare to match the host clock.
  91  *
  92  * #define MIPS_STRICT_STANDARD 1
  93  */
  94
  95 #endif /* QEMU_MIPS_DEFS_H */