target/mips/sysemu/cp0_timer.c

   1 /*
   2  * QEMU MIPS timer support
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "hw/irq.h"
  25 #include "hw/mips/cpudevs.h"
  26 #include "qemu/timer.h"
  27 #include "sysemu/kvm.h"
  28 #include "internal.h"
  29
  30 /* MIPS R4K timer */
  31 static void cpu_mips_timer_update(CPUMIPSState *env)
  32 {
  33     uint64_t now_ns, next_ns;
  34     uint32_t wait;
  35
  36     now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  37     wait = env->CP0_Compare - env->CP0_Count -
  38            (uint32_t)(now_ns / env->cp0_count_ns);
  39     next_ns = now_ns + (uint64_t)wait * env->cp0_count_ns;
  40     timer_mod(env->timer, next_ns);
  41 }
  42
  43 /* Expire the timer.  */
  44 static void cpu_mips_timer_expire(CPUMIPSState *env)
  45 {
  46     cpu_mips_timer_update(env);
  47     if (env->insn_flags & ISA_MIPS_R2) {
  48         env->CP0_Cause |= 1 << CP0Ca_TI;
  49     }
  50     qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
  51 }
  52
  53 uint32_t cpu_mips_get_count(CPUMIPSState *env)
  54 {
  55     if (env->CP0_Cause & (1 << CP0Ca_DC)) {
  56         return env->CP0_Count;
  57     } else {
  58         uint64_t now_ns;
  59
  60         now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  61         if (timer_pending(env->timer)
  62             && timer_expired(env->timer, now_ns)) {
  63             /* The timer has already expired.  */
  64             cpu_mips_timer_expire(env);
  65         }
  66
  67         return env->CP0_Count + (uint32_t)(now_ns / env->cp0_count_ns);
  68     }
  69 }
  70
  71 void cpu_mips_store_count(CPUMIPSState *env, uint32_t count)
  72 {
  73     /*
  74      * This gets called from cpu_state_reset(), potentially before timer init.
  75      * So env->timer may be NULL, which is also the case with KVM enabled so
  76      * treat timer as disabled in that case.
  77      */
  78     if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) {
  79         env->CP0_Count = count;
  80     } else {
  81         /* Store new count register */
  82         env->CP0_Count = count -
  83                (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
  84                           env->cp0_count_ns);
  85         /* Update timer timer */
  86         cpu_mips_timer_update(env);
  87     }
  88 }
  89
  90 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
  91 {
  92     env->CP0_Compare = value;
  93     if (!(env->CP0_Cause & (1 << CP0Ca_DC))) {
  94         cpu_mips_timer_update(env);
  95     }
  96     if (env->insn_flags & ISA_MIPS_R2) {
  97         env->CP0_Cause &= ~(1 << CP0Ca_TI);
  98     }
  99     qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
 100 }
 101
 102 void cpu_mips_start_count(CPUMIPSState *env)
 103 {
 104     cpu_mips_store_count(env, env->CP0_Count);
 105 }
 106
 107 void cpu_mips_stop_count(CPUMIPSState *env)
 108 {
 109     /* Store the current value */
 110     env->CP0_Count += (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
 111                                  env->cp0_count_ns);
 112 }
 113
 114 static void mips_timer_cb(void *opaque)
 115 {
 116     CPUMIPSState *env;
 117
 118     env = opaque;
 119
 120     if (env->CP0_Cause & (1 << CP0Ca_DC)) {
 121         return;
 122     }
 123
 124     /*
 125      * ??? This callback should occur when the counter is exactly equal to
 126      * the comparator value.  Offset the count by one to avoid immediately
 127      * retriggering the callback before any virtual time has passed.
 128      */
 129     env->CP0_Count++;
 130     cpu_mips_timer_expire(env);
 131     env->CP0_Count--;
 132 }
 133
 134 void cpu_mips_clock_init(MIPSCPU *cpu)
 135 {
 136     CPUMIPSState *env = &cpu->env;
 137
 138     /*
 139      * If we're in KVM mode, don't create the periodic timer, that is handled in
 140      * kernel.
 141      */
 142     if (!kvm_enabled()) {
 143         env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
 144     }
 145 }