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qapi: Improve specificity of type/member descriptions
[qemu/armbru.git] / target / ppc / cpu_init.c
blob0ce2e3c91d99fb0035e9c516522ed00319146013
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "gdbstub/helpers.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43
44 #include "helper_regs.h"
45 #include "internal.h"
46 #include "spr_common.h"
47 #include "power8-pmu.h"
48
49 #ifndef CONFIG_USER_ONLY
50 #include "hw/boards.h"
51 #endif
52
53 /* #define PPC_DEBUG_SPR */
54 /* #define USE_APPLE_GDB */
55
56 static inline void vscr_init(CPUPPCState *env, uint32_t val)
57 {
58 /* Altivec always uses round-to-nearest */
59 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
60 ppc_store_vscr(env, val);
61 }
62
63 static void register_745_sprs(CPUPPCState *env)
64 {
65 /* SGPRs */
66 spr_register(env, SPR_SPRG4, "SPRG4",
67 SPR_NOACCESS, SPR_NOACCESS,
68 &spr_read_generic, &spr_write_generic,
69 0x00000000);
70 spr_register(env, SPR_SPRG5, "SPRG5",
71 SPR_NOACCESS, SPR_NOACCESS,
72 &spr_read_generic, &spr_write_generic,
73 0x00000000);
74 spr_register(env, SPR_SPRG6, "SPRG6",
75 SPR_NOACCESS, SPR_NOACCESS,
76 &spr_read_generic, &spr_write_generic,
77 0x00000000);
78 spr_register(env, SPR_SPRG7, "SPRG7",
79 SPR_NOACCESS, SPR_NOACCESS,
80 &spr_read_generic, &spr_write_generic,
81 0x00000000);
82
83 /* Hardware implementation registers */
84 spr_register(env, SPR_HID0, "HID0",
85 SPR_NOACCESS, SPR_NOACCESS,
86 &spr_read_generic, &spr_write_generic,
87 0x00000000);
88
89 spr_register(env, SPR_HID1, "HID1",
90 SPR_NOACCESS, SPR_NOACCESS,
91 &spr_read_generic, &spr_write_generic,
92 0x00000000);
93
94 spr_register(env, SPR_HID2, "HID2",
95 SPR_NOACCESS, SPR_NOACCESS,
96 &spr_read_generic, &spr_write_generic,
97 0x00000000);
98 }
99
100 static void register_755_sprs(CPUPPCState *env)
101 {
102 /* L2 cache control */
103 spr_register(env, SPR_L2CR, "L2CR",
104 SPR_NOACCESS, SPR_NOACCESS,
105 &spr_read_generic, spr_access_nop,
106 0x00000000);
107
108 spr_register(env, SPR_L2PMCR, "L2PMCR",
109 SPR_NOACCESS, SPR_NOACCESS,
110 &spr_read_generic, &spr_write_generic,
111 0x00000000);
112 }
113
114 /* SPR common to all 7xx PowerPC implementations */
115 static void register_7xx_sprs(CPUPPCState *env)
116 {
117 /* Breakpoints */
118 spr_register_kvm(env, SPR_DABR, "DABR",
119 SPR_NOACCESS, SPR_NOACCESS,
120 &spr_read_generic, &spr_write_generic,
121 KVM_REG_PPC_DABR, 0x00000000);
122
123 spr_register(env, SPR_IABR, "IABR",
124 SPR_NOACCESS, SPR_NOACCESS,
125 &spr_read_generic, &spr_write_generic,
126 0x00000000);
127 /* Cache management */
128 spr_register(env, SPR_ICTC, "ICTC",
129 SPR_NOACCESS, SPR_NOACCESS,
130 &spr_read_generic, &spr_write_generic,
131 0x00000000);
132 /* Performance monitors */
133 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
134 SPR_NOACCESS, SPR_NOACCESS,
135 &spr_read_generic, &spr_write_generic,
136 0x00000000);
137
138 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
139 SPR_NOACCESS, SPR_NOACCESS,
140 &spr_read_generic, &spr_write_generic,
141 0x00000000);
142
143 spr_register(env, SPR_7XX_PMC1, "PMC1",
144 SPR_NOACCESS, SPR_NOACCESS,
145 &spr_read_generic, &spr_write_generic,
146 0x00000000);
147
148 spr_register(env, SPR_7XX_PMC2, "PMC2",
149 SPR_NOACCESS, SPR_NOACCESS,
150 &spr_read_generic, &spr_write_generic,
151 0x00000000);
152
153 spr_register(env, SPR_7XX_PMC3, "PMC3",
154 SPR_NOACCESS, SPR_NOACCESS,
155 &spr_read_generic, &spr_write_generic,
156 0x00000000);
157
158 spr_register(env, SPR_7XX_PMC4, "PMC4",
159 SPR_NOACCESS, SPR_NOACCESS,
160 &spr_read_generic, &spr_write_generic,
161 0x00000000);
162
163 spr_register(env, SPR_7XX_SIAR, "SIAR",
164 SPR_NOACCESS, SPR_NOACCESS,
165 &spr_read_generic, SPR_NOACCESS,
166 0x00000000);
167
168 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
169 &spr_read_ureg, SPR_NOACCESS,
170 &spr_read_ureg, SPR_NOACCESS,
171 0x00000000);
172
173 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
174 &spr_read_ureg, SPR_NOACCESS,
175 &spr_read_ureg, SPR_NOACCESS,
176 0x00000000);
177
178 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
179 &spr_read_ureg, SPR_NOACCESS,
180 &spr_read_ureg, SPR_NOACCESS,
181 0x00000000);
182
183 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
184 &spr_read_ureg, SPR_NOACCESS,
185 &spr_read_ureg, SPR_NOACCESS,
186 0x00000000);
187
188 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
189 &spr_read_ureg, SPR_NOACCESS,
190 &spr_read_ureg, SPR_NOACCESS,
191 0x00000000);
192
193 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
194 &spr_read_ureg, SPR_NOACCESS,
195 &spr_read_ureg, SPR_NOACCESS,
196 0x00000000);
197
198 spr_register(env, SPR_7XX_USIAR, "USIAR",
199 &spr_read_ureg, SPR_NOACCESS,
200 &spr_read_ureg, SPR_NOACCESS,
201 0x00000000);
202 /* External access control */
203 spr_register(env, SPR_EAR, "EAR",
204 SPR_NOACCESS, SPR_NOACCESS,
205 &spr_read_generic, &spr_write_generic,
206 0x00000000);
207
208 /* Hardware implementation registers */
209 spr_register(env, SPR_HID0, "HID0",
210 SPR_NOACCESS, SPR_NOACCESS,
211 &spr_read_generic, &spr_write_generic,
212 0x00000000);
213
214 spr_register(env, SPR_HID1, "HID1",
215 SPR_NOACCESS, SPR_NOACCESS,
216 &spr_read_generic, &spr_write_generic,
217 0x00000000);
218 }
219
220 #ifdef TARGET_PPC64
221 static void register_amr_sprs(CPUPPCState *env)
222 {
223 #ifndef CONFIG_USER_ONLY
224 /*
225 * Virtual Page Class Key protection
226 *
227 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
228 * userspace accessible, 29 is privileged. So we only need to set
229 * the kvm ONE_REG id on one of them, we use 29
230 */
231 spr_register(env, SPR_UAMR, "UAMR",
232 &spr_read_generic, &spr_write_amr,
233 &spr_read_generic, &spr_write_amr,
234 0);
235 spr_register_kvm_hv(env, SPR_AMR, "AMR",
236 SPR_NOACCESS, SPR_NOACCESS,
237 &spr_read_generic, &spr_write_amr,
238 &spr_read_generic, &spr_write_generic,
239 KVM_REG_PPC_AMR, 0);
240 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
241 SPR_NOACCESS, SPR_NOACCESS,
242 &spr_read_generic, &spr_write_uamor,
243 &spr_read_generic, &spr_write_generic,
244 KVM_REG_PPC_UAMOR, 0);
245 spr_register_hv(env, SPR_AMOR, "AMOR",
246 SPR_NOACCESS, SPR_NOACCESS,
247 SPR_NOACCESS, SPR_NOACCESS,
248 &spr_read_generic, &spr_write_generic,
249 0);
250 #endif /* !CONFIG_USER_ONLY */
251 }
252
253 static void register_iamr_sprs(CPUPPCState *env)
254 {
255 #ifndef CONFIG_USER_ONLY
256 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
257 SPR_NOACCESS, SPR_NOACCESS,
258 &spr_read_generic, &spr_write_iamr,
259 &spr_read_generic, &spr_write_generic,
260 KVM_REG_PPC_IAMR, 0);
261 #endif /* !CONFIG_USER_ONLY */
262 }
263 #endif /* TARGET_PPC64 */
264
265 /* SPR specific to PowerPC 604 implementation */
266 static void register_604_sprs(CPUPPCState *env)
267 {
268 /* Processor identification */
269 spr_register(env, SPR_PIR, "PIR",
270 SPR_NOACCESS, SPR_NOACCESS,
271 &spr_read_generic, &spr_write_pir,
272 0x00000000);
273 /* Breakpoints */
274 spr_register(env, SPR_IABR, "IABR",
275 SPR_NOACCESS, SPR_NOACCESS,
276 &spr_read_generic, &spr_write_generic,
277 0x00000000);
278
279 spr_register_kvm(env, SPR_DABR, "DABR",
280 SPR_NOACCESS, SPR_NOACCESS,
281 &spr_read_generic, &spr_write_generic,
282 KVM_REG_PPC_DABR, 0x00000000);
283 /* Performance counters */
284 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
285 SPR_NOACCESS, SPR_NOACCESS,
286 &spr_read_generic, &spr_write_generic,
287 0x00000000);
288
289 spr_register(env, SPR_7XX_PMC1, "PMC1",
290 SPR_NOACCESS, SPR_NOACCESS,
291 &spr_read_generic, &spr_write_generic,
292 0x00000000);
293
294 spr_register(env, SPR_7XX_PMC2, "PMC2",
295 SPR_NOACCESS, SPR_NOACCESS,
296 &spr_read_generic, &spr_write_generic,
297 0x00000000);
298
299 spr_register(env, SPR_7XX_SIAR, "SIAR",
300 SPR_NOACCESS, SPR_NOACCESS,
301 &spr_read_generic, SPR_NOACCESS,
302 0x00000000);
303
304 spr_register(env, SPR_SDA, "SDA",
305 SPR_NOACCESS, SPR_NOACCESS,
306 &spr_read_generic, SPR_NOACCESS,
307 0x00000000);
308 /* External access control */
309 spr_register(env, SPR_EAR, "EAR",
310 SPR_NOACCESS, SPR_NOACCESS,
311 &spr_read_generic, &spr_write_generic,
312 0x00000000);
313
314 /* Hardware implementation registers */
315 spr_register(env, SPR_HID0, "HID0",
316 SPR_NOACCESS, SPR_NOACCESS,
317 &spr_read_generic, &spr_write_generic,
318 0x00000000);
319 }
320
321 static void register_604e_sprs(CPUPPCState *env)
322 {
323 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
324 SPR_NOACCESS, SPR_NOACCESS,
325 &spr_read_generic, &spr_write_generic,
326 0x00000000);
327
328 spr_register(env, SPR_7XX_PMC3, "PMC3",
329 SPR_NOACCESS, SPR_NOACCESS,
330 &spr_read_generic, &spr_write_generic,
331 0x00000000);
332
333 spr_register(env, SPR_7XX_PMC4, "PMC4",
334 SPR_NOACCESS, SPR_NOACCESS,
335 &spr_read_generic, &spr_write_generic,
336 0x00000000);
337 /* Hardware implementation registers */
338 spr_register(env, SPR_HID1, "HID1",
339 SPR_NOACCESS, SPR_NOACCESS,
340 &spr_read_generic, &spr_write_generic,
341 0x00000000);
342 }
343
344 /* SPR specific to PowerPC 603 implementation */
345 static void register_603_sprs(CPUPPCState *env)
346 {
347 /* External access control */
348 spr_register(env, SPR_EAR, "EAR",
349 SPR_NOACCESS, SPR_NOACCESS,
350 &spr_read_generic, &spr_write_generic,
351 0x00000000);
352 /* Breakpoints */
353 spr_register(env, SPR_IABR, "IABR",
354 SPR_NOACCESS, SPR_NOACCESS,
355 &spr_read_generic, &spr_write_generic,
356 0x00000000);
357
358 spr_register(env, SPR_HID0, "HID0",
359 SPR_NOACCESS, SPR_NOACCESS,
360 &spr_read_generic, &spr_write_generic,
361 0x00000000);
362
363 spr_register(env, SPR_HID1, "HID1",
364 SPR_NOACCESS, SPR_NOACCESS,
365 &spr_read_generic, &spr_write_generic,
366 0x00000000);
367 }
368
369 static void register_e300_sprs(CPUPPCState *env)
370 {
371 /* hardware implementation registers */
372 spr_register(env, SPR_HID2, "HID2",
373 SPR_NOACCESS, SPR_NOACCESS,
374 &spr_read_generic, &spr_write_generic,
375 0x00000000);
376 /* Breakpoints */
377 spr_register(env, SPR_DABR, "DABR",
378 SPR_NOACCESS, SPR_NOACCESS,
379 &spr_read_generic, &spr_write_generic,
380 0x00000000);
381
382 spr_register(env, SPR_DABR2, "DABR2",
383 SPR_NOACCESS, SPR_NOACCESS,
384 &spr_read_generic, &spr_write_generic,
385 0x00000000);
386
387 spr_register(env, SPR_IABR2, "IABR2",
388 SPR_NOACCESS, SPR_NOACCESS,
389 &spr_read_generic, &spr_write_generic,
390 0x00000000);
391
392 spr_register(env, SPR_IBCR, "IBCR",
393 SPR_NOACCESS, SPR_NOACCESS,
394 &spr_read_generic, &spr_write_generic,
395 0x00000000);
396
397 spr_register(env, SPR_DBCR, "DBCR",
398 SPR_NOACCESS, SPR_NOACCESS,
399 &spr_read_generic, &spr_write_generic,
400 0x00000000);
401 }
402
403 /* SPR specific to PowerPC G2 implementation */
404 static void register_G2_sprs(CPUPPCState *env)
405 {
406 /* Memory base address */
407 /* MBAR */
408 spr_register(env, SPR_MBAR, "MBAR",
409 SPR_NOACCESS, SPR_NOACCESS,
410 &spr_read_generic, &spr_write_generic,
411 0x00000000);
412 /* Exception processing */
413 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
414 SPR_NOACCESS, SPR_NOACCESS,
415 &spr_read_generic, &spr_write_generic,
416 0x00000000);
417 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
418 SPR_NOACCESS, SPR_NOACCESS,
419 &spr_read_generic, &spr_write_generic,
420 0x00000000);
421 /* Breakpoints */
422 spr_register(env, SPR_DABR, "DABR",
423 SPR_NOACCESS, SPR_NOACCESS,
424 &spr_read_generic, &spr_write_generic,
425 0x00000000);
426
427 spr_register(env, SPR_DABR2, "DABR2",
428 SPR_NOACCESS, SPR_NOACCESS,
429 &spr_read_generic, &spr_write_generic,
430 0x00000000);
431
432 spr_register(env, SPR_IABR, "IABR",
433 SPR_NOACCESS, SPR_NOACCESS,
434 &spr_read_generic, &spr_write_generic,
435 0x00000000);
436
437 spr_register(env, SPR_IABR2, "IABR2",
438 SPR_NOACCESS, SPR_NOACCESS,
439 &spr_read_generic, &spr_write_generic,
440 0x00000000);
441
442 spr_register(env, SPR_IBCR, "IBCR",
443 SPR_NOACCESS, SPR_NOACCESS,
444 &spr_read_generic, &spr_write_generic,
445 0x00000000);
446
447 spr_register(env, SPR_DBCR, "DBCR",
448 SPR_NOACCESS, SPR_NOACCESS,
449 &spr_read_generic, &spr_write_generic,
450 0x00000000);
451
452 /* External access control */
453 spr_register(env, SPR_EAR, "EAR",
454 SPR_NOACCESS, SPR_NOACCESS,
455 &spr_read_generic, &spr_write_generic,
456 0x00000000);
457 /* Hardware implementation register */
458 spr_register(env, SPR_HID0, "HID0",
459 SPR_NOACCESS, SPR_NOACCESS,
460 &spr_read_generic, &spr_write_generic,
461 0x00000000);
462
463 spr_register(env, SPR_HID1, "HID1",
464 SPR_NOACCESS, SPR_NOACCESS,
465 &spr_read_generic, &spr_write_generic,
466 0x00000000);
467
468 spr_register(env, SPR_HID2, "HID2",
469 SPR_NOACCESS, SPR_NOACCESS,
470 &spr_read_generic, &spr_write_generic,
471 0x00000000);
472
473 /* SGPRs */
474 spr_register(env, SPR_SPRG4, "SPRG4",
475 SPR_NOACCESS, SPR_NOACCESS,
476 &spr_read_generic, &spr_write_generic,
477 0x00000000);
478 spr_register(env, SPR_SPRG5, "SPRG5",
479 SPR_NOACCESS, SPR_NOACCESS,
480 &spr_read_generic, &spr_write_generic,
481 0x00000000);
482 spr_register(env, SPR_SPRG6, "SPRG6",
483 SPR_NOACCESS, SPR_NOACCESS,
484 &spr_read_generic, &spr_write_generic,
485 0x00000000);
486 spr_register(env, SPR_SPRG7, "SPRG7",
487 SPR_NOACCESS, SPR_NOACCESS,
488 &spr_read_generic, &spr_write_generic,
489 0x00000000);
490 }
491
492 static void register_74xx_sprs(CPUPPCState *env)
493 {
494 /* Breakpoints */
495 spr_register_kvm(env, SPR_DABR, "DABR",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_generic, &spr_write_generic,
498 KVM_REG_PPC_DABR, 0x00000000);
499
500 spr_register(env, SPR_IABR, "IABR",
501 SPR_NOACCESS, SPR_NOACCESS,
502 &spr_read_generic, &spr_write_generic,
503 0x00000000);
504 /* Cache management */
505 spr_register(env, SPR_ICTC, "ICTC",
506 SPR_NOACCESS, SPR_NOACCESS,
507 &spr_read_generic, &spr_write_generic,
508 0x00000000);
509 /* Performance monitors */
510 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
511 SPR_NOACCESS, SPR_NOACCESS,
512 &spr_read_generic, &spr_write_generic,
513 0x00000000);
514
515 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
516 SPR_NOACCESS, SPR_NOACCESS,
517 &spr_read_generic, &spr_write_generic,
518 0x00000000);
519
520 spr_register(env, SPR_7XX_PMC1, "PMC1",
521 SPR_NOACCESS, SPR_NOACCESS,
522 &spr_read_generic, &spr_write_generic,
523 0x00000000);
524
525 spr_register(env, SPR_7XX_PMC2, "PMC2",
526 SPR_NOACCESS, SPR_NOACCESS,
527 &spr_read_generic, &spr_write_generic,
528 0x00000000);
529
530 spr_register(env, SPR_7XX_PMC3, "PMC3",
531 SPR_NOACCESS, SPR_NOACCESS,
532 &spr_read_generic, &spr_write_generic,
533 0x00000000);
534
535 spr_register(env, SPR_7XX_PMC4, "PMC4",
536 SPR_NOACCESS, SPR_NOACCESS,
537 &spr_read_generic, &spr_write_generic,
538 0x00000000);
539
540 spr_register(env, SPR_7XX_SIAR, "SIAR",
541 SPR_NOACCESS, SPR_NOACCESS,
542 &spr_read_generic, SPR_NOACCESS,
543 0x00000000);
544
545 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
546 &spr_read_ureg, SPR_NOACCESS,
547 &spr_read_ureg, SPR_NOACCESS,
548 0x00000000);
549
550 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
551 &spr_read_ureg, SPR_NOACCESS,
552 &spr_read_ureg, SPR_NOACCESS,
553 0x00000000);
554
555 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
556 &spr_read_ureg, SPR_NOACCESS,
557 &spr_read_ureg, SPR_NOACCESS,
558 0x00000000);
559
560 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
561 &spr_read_ureg, SPR_NOACCESS,
562 &spr_read_ureg, SPR_NOACCESS,
563 0x00000000);
564
565 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
566 &spr_read_ureg, SPR_NOACCESS,
567 &spr_read_ureg, SPR_NOACCESS,
568 0x00000000);
569
570 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
571 &spr_read_ureg, SPR_NOACCESS,
572 &spr_read_ureg, SPR_NOACCESS,
573 0x00000000);
574
575 spr_register(env, SPR_7XX_USIAR, "USIAR",
576 &spr_read_ureg, SPR_NOACCESS,
577 &spr_read_ureg, SPR_NOACCESS,
578 0x00000000);
579 /* External access control */
580 spr_register(env, SPR_EAR, "EAR",
581 SPR_NOACCESS, SPR_NOACCESS,
582 &spr_read_generic, &spr_write_generic,
583 0x00000000);
584
585 /* Processor identification */
586 spr_register(env, SPR_PIR, "PIR",
587 SPR_NOACCESS, SPR_NOACCESS,
588 &spr_read_generic, &spr_write_pir,
589 0x00000000);
590
591 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
592 SPR_NOACCESS, SPR_NOACCESS,
593 &spr_read_generic, &spr_write_generic,
594 0x00000000);
595
596 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
597 &spr_read_ureg, SPR_NOACCESS,
598 &spr_read_ureg, SPR_NOACCESS,
599 0x00000000);
600
601 spr_register(env, SPR_BAMR, "BAMR",
602 SPR_NOACCESS, SPR_NOACCESS,
603 &spr_read_generic, &spr_write_generic,
604 0x00000000);
605
606 spr_register(env, SPR_MSSCR0, "MSSCR0",
607 SPR_NOACCESS, SPR_NOACCESS,
608 &spr_read_generic, &spr_write_generic,
609 0x00000000);
610 /* Hardware implementation registers */
611 spr_register(env, SPR_HID0, "HID0",
612 SPR_NOACCESS, SPR_NOACCESS,
613 &spr_read_generic, &spr_write_generic,
614 0x00000000);
615
616 spr_register(env, SPR_HID1, "HID1",
617 SPR_NOACCESS, SPR_NOACCESS,
618 &spr_read_generic, &spr_write_generic,
619 0x00000000);
620 /* Altivec */
621 spr_register(env, SPR_VRSAVE, "VRSAVE",
622 &spr_read_generic, &spr_write_generic,
623 &spr_read_generic, &spr_write_generic,
624 0x00000000);
625
626 spr_register(env, SPR_L2CR, "L2CR",
627 SPR_NOACCESS, SPR_NOACCESS,
628 &spr_read_generic, spr_access_nop,
629 0x00000000);
630 }
631
632 static void register_l3_ctrl(CPUPPCState *env)
633 {
634 /* L3CR */
635 spr_register(env, SPR_L3CR, "L3CR",
636 SPR_NOACCESS, SPR_NOACCESS,
637 &spr_read_generic, &spr_write_generic,
638 0x00000000);
639 /* L3ITCR0 */
640 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
641 SPR_NOACCESS, SPR_NOACCESS,
642 &spr_read_generic, &spr_write_generic,
643 0x00000000);
644 /* L3PM */
645 spr_register(env, SPR_L3PM, "L3PM",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_generic, &spr_write_generic,
648 0x00000000);
649 }
650
651 /* PowerPC BookE SPR */
652 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
653 {
654 const char *ivor_names[64] = {
655 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
656 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
657 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
658 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
659 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
660 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
661 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
662 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
663 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
664 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
665 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
666 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
667 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
668 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
669 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
670 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
671 };
672 #define SPR_BOOKE_IVORxx (-1)
673 int ivor_sprn[64] = {
674 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
675 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
676 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
677 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
678 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
679 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
680 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
682 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
683 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
684 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
685 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
686 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
687 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
690 };
691 int i;
692
693 /* Interrupt processing */
694 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
695 SPR_NOACCESS, SPR_NOACCESS,
696 &spr_read_generic, &spr_write_generic,
697 0x00000000);
698 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
699 SPR_NOACCESS, SPR_NOACCESS,
700 &spr_read_generic, &spr_write_generic,
701 0x00000000);
702 /* Debug */
703 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_generic, &spr_write_generic,
706 0x00000000);
707
708 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_generic, &spr_write_generic,
711 0x00000000);
712
713 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_generic, &spr_write_generic,
716 0x00000000);
717
718 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_generic, &spr_write_generic,
721 0x00000000);
722
723 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_generic, &spr_write_40x_dbcr0,
726 0x00000000);
727
728 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_generic, &spr_write_generic,
731 0x00000000);
732
733 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_generic, &spr_write_generic,
736 0x00000000);
737 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_generic, &spr_write_generic,
740 0x00000000);
741 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_generic, &spr_write_generic,
744 0x00000000);
745
746 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_generic, &spr_write_clear,
749 0x00000000);
750 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_generic, &spr_write_generic,
753 0x00000000);
754 spr_register(env, SPR_BOOKE_ESR, "ESR",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_generic, &spr_write_generic,
757 0x00000000);
758 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_generic, &spr_write_excp_prefix,
761 0x00000000);
762 /* Exception vectors */
763 for (i = 0; i < 64; i++) {
764 if (ivor_mask & (1ULL << i)) {
765 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
766 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
767 exit(1);
768 }
769 spr_register(env, ivor_sprn[i], ivor_names[i],
770 SPR_NOACCESS, SPR_NOACCESS,
771 &spr_read_generic, &spr_write_excp_vector,
772 0x00000000);
773 }
774 }
775 spr_register(env, SPR_BOOKE_PID, "PID",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_booke_pid,
778 0x00000000);
779 spr_register(env, SPR_BOOKE_TCR, "TCR",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_generic, &spr_write_booke_tcr,
782 0x00000000);
783 spr_register(env, SPR_BOOKE_TSR, "TSR",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_generic, &spr_write_booke_tsr,
786 0x00000000);
787 /* Timer */
788 spr_register(env, SPR_DECR, "DECR",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_decr, &spr_write_decr,
791 0x00000000);
792 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
793 SPR_NOACCESS, SPR_NOACCESS,
794 SPR_NOACCESS, &spr_write_generic,
795 0x00000000);
796 /* SPRGs */
797 spr_register(env, SPR_USPRG0, "USPRG0",
798 &spr_read_generic, &spr_write_generic,
799 &spr_read_generic, &spr_write_generic,
800 0x00000000);
801 spr_register(env, SPR_SPRG4, "SPRG4",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_generic, &spr_write_generic,
804 0x00000000);
805 spr_register(env, SPR_SPRG5, "SPRG5",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_generic, &spr_write_generic,
808 0x00000000);
809 spr_register(env, SPR_SPRG6, "SPRG6",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_generic, &spr_write_generic,
812 0x00000000);
813 spr_register(env, SPR_SPRG7, "SPRG7",
814 SPR_NOACCESS, SPR_NOACCESS,
815 &spr_read_generic, &spr_write_generic,
816 0x00000000);
817 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_generic, &spr_write_generic,
820 0x00000000);
821 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_generic, &spr_write_generic,
824 0x00000000);
825 }
826
827 #if !defined(CONFIG_USER_ONLY)
828 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
829 uint32_t maxsize, uint32_t flags,
830 uint32_t nentries)
831 {
832 return (assoc << TLBnCFG_ASSOC_SHIFT) |
833 (minsize << TLBnCFG_MINSIZE_SHIFT) |
834 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
835 flags | nentries;
836 }
837 #endif /* !CONFIG_USER_ONLY */
838
839 /* BookE 2.06 storage control registers */
840 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
841 uint32_t *tlbncfg, uint32_t mmucfg)
842 {
843 #if !defined(CONFIG_USER_ONLY)
844 const char *mas_names[8] = {
845 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
846 };
847 int mas_sprn[8] = {
848 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
849 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
850 };
851 int i;
852
853 /* TLB assist registers */
854 for (i = 0; i < 8; i++) {
855 if (mas_mask & (1 << i)) {
856 spr_register(env, mas_sprn[i], mas_names[i],
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_generic,
859 (i == 2 && (env->insns_flags & PPC_64B))
860 ? &spr_write_generic : &spr_write_generic32,
861 0x00000000);
862 }
863 }
864 if (env->nb_pids > 1) {
865 spr_register(env, SPR_BOOKE_PID1, "PID1",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, &spr_write_booke_pid,
868 0x00000000);
869 }
870 if (env->nb_pids > 2) {
871 spr_register(env, SPR_BOOKE_PID2, "PID2",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, &spr_write_booke_pid,
874 0x00000000);
875 }
876
877 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_generic, &spr_write_eplc,
880 0x00000000);
881 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
882 SPR_NOACCESS, SPR_NOACCESS,
883 &spr_read_generic, &spr_write_epsc,
884 0x00000000);
885
886 spr_register(env, SPR_MMUCFG, "MMUCFG",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, SPR_NOACCESS,
889 mmucfg);
890 switch (env->nb_ways) {
891 case 4:
892 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, SPR_NOACCESS,
895 tlbncfg[3]);
896 /* Fallthru */
897 case 3:
898 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
899 SPR_NOACCESS, SPR_NOACCESS,
900 &spr_read_generic, SPR_NOACCESS,
901 tlbncfg[2]);
902 /* Fallthru */
903 case 2:
904 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, SPR_NOACCESS,
907 tlbncfg[1]);
908 /* Fallthru */
909 case 1:
910 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_generic, SPR_NOACCESS,
913 tlbncfg[0]);
914 /* Fallthru */
915 case 0:
916 default:
917 break;
918 }
919 #endif
920 }
921
922 /* SPR specific to PowerPC 440 implementation */
923 static void register_440_sprs(CPUPPCState *env)
924 {
925 /* Cache control */
926 spr_register(env, SPR_440_DNV0, "DNV0",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 0x00000000);
930
931 spr_register(env, SPR_440_DNV1, "DNV1",
932 SPR_NOACCESS, SPR_NOACCESS,
933 &spr_read_generic, &spr_write_generic,
934 0x00000000);
935
936 spr_register(env, SPR_440_DNV2, "DNV2",
937 SPR_NOACCESS, SPR_NOACCESS,
938 &spr_read_generic, &spr_write_generic,
939 0x00000000);
940
941 spr_register(env, SPR_440_DNV3, "DNV3",
942 SPR_NOACCESS, SPR_NOACCESS,
943 &spr_read_generic, &spr_write_generic,
944 0x00000000);
945
946 spr_register(env, SPR_440_DTV0, "DTV0",
947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, &spr_write_generic,
949 0x00000000);
950
951 spr_register(env, SPR_440_DTV1, "DTV1",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, &spr_write_generic,
954 0x00000000);
955
956 spr_register(env, SPR_440_DTV2, "DTV2",
957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_generic, &spr_write_generic,
959 0x00000000);
960
961 spr_register(env, SPR_440_DTV3, "DTV3",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965
966 spr_register(env, SPR_440_DVLIM, "DVLIM",
967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, &spr_write_generic,
969 0x00000000);
970
971 spr_register(env, SPR_440_INV0, "INV0",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975
976 spr_register(env, SPR_440_INV1, "INV1",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
979 0x00000000);
980
981 spr_register(env, SPR_440_INV2, "INV2",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
984 0x00000000);
985
986 spr_register(env, SPR_440_INV3, "INV3",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
990
991 spr_register(env, SPR_440_ITV0, "ITV0",
992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, &spr_write_generic,
994 0x00000000);
995
996 spr_register(env, SPR_440_ITV1, "ITV1",
997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, &spr_write_generic,
999 0x00000000);
1000
1001 spr_register(env, SPR_440_ITV2, "ITV2",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, &spr_write_generic,
1004 0x00000000);
1005
1006 spr_register(env, SPR_440_ITV3, "ITV3",
1007 SPR_NOACCESS, SPR_NOACCESS,
1008 &spr_read_generic, &spr_write_generic,
1009 0x00000000);
1010
1011 spr_register(env, SPR_440_IVLIM, "IVLIM",
1012 SPR_NOACCESS, SPR_NOACCESS,
1013 &spr_read_generic, &spr_write_generic,
1014 0x00000000);
1015 /* Cache debug */
1016 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, SPR_NOACCESS,
1019 0x00000000);
1020
1021 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1022 SPR_NOACCESS, SPR_NOACCESS,
1023 &spr_read_generic, SPR_NOACCESS,
1024 0x00000000);
1025
1026 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1027 SPR_NOACCESS, SPR_NOACCESS,
1028 &spr_read_generic, SPR_NOACCESS,
1029 0x00000000);
1030
1031 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, SPR_NOACCESS,
1034 0x00000000);
1035
1036 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, SPR_NOACCESS,
1039 0x00000000);
1040
1041 spr_register(env, SPR_440_DBDR, "DBDR",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* Processor control */
1046 spr_register(env, SPR_4xx_CCR0, "CCR0",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, SPR_NOACCESS,
1053 0x00000000);
1054 /* Storage control */
1055 spr_register(env, SPR_440_MMUCR, "MMUCR",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, &spr_write_generic,
1058 0x00000000);
1059
1060 /* Processor identification */
1061 spr_register(env, SPR_BOOKE_PIR, "PIR",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, &spr_write_pir,
1064 0x00000000);
1065
1066 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_generic,
1069 0x00000000);
1070
1071 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_generic, &spr_write_generic,
1074 0x00000000);
1075
1076 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1077 SPR_NOACCESS, SPR_NOACCESS,
1078 &spr_read_generic, &spr_write_generic,
1079 0x00000000);
1080
1081 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1082 SPR_NOACCESS, SPR_NOACCESS,
1083 &spr_read_generic, &spr_write_generic,
1084 0x00000000);
1085 }
1086
1087 /* SPR shared between PowerPC 40x implementations */
1088 static void register_40x_sprs(CPUPPCState *env)
1089 {
1090 /* Cache */
1091 /* not emulated, as QEMU do not emulate caches */
1092 spr_register(env, SPR_40x_DCCR, "DCCR",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, &spr_write_generic,
1095 0x00000000);
1096 /* not emulated, as QEMU do not emulate caches */
1097 spr_register(env, SPR_40x_ICCR, "ICCR",
1098 SPR_NOACCESS, SPR_NOACCESS,
1099 &spr_read_generic, &spr_write_generic,
1100 0x00000000);
1101 /* not emulated, as QEMU do not emulate caches */
1102 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 &spr_read_generic, SPR_NOACCESS,
1105 0x00000000);
1106 /* Exception */
1107 spr_register(env, SPR_40x_DEAR, "DEAR",
1108 SPR_NOACCESS, SPR_NOACCESS,
1109 &spr_read_generic, &spr_write_generic,
1110 0x00000000);
1111 spr_register(env, SPR_40x_ESR, "ESR",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 spr_register(env, SPR_40x_EVPR, "EVPR",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_generic, &spr_write_excp_prefix,
1118 0x00000000);
1119 spr_register(env, SPR_40x_SRR2, "SRR2",
1120 &spr_read_generic, &spr_write_generic,
1121 &spr_read_generic, &spr_write_generic,
1122 0x00000000);
1123 spr_register(env, SPR_40x_SRR3, "SRR3",
1124 &spr_read_generic, &spr_write_generic,
1125 &spr_read_generic, &spr_write_generic,
1126 0x00000000);
1127 /* Timers */
1128 spr_register(env, SPR_40x_PIT, "PIT",
1129 SPR_NOACCESS, SPR_NOACCESS,
1130 &spr_read_40x_pit, &spr_write_40x_pit,
1131 0x00000000);
1132 spr_register(env, SPR_40x_TCR, "TCR",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, &spr_write_40x_tcr,
1135 0x00000000);
1136 spr_register(env, SPR_40x_TSR, "TSR",
1137 SPR_NOACCESS, SPR_NOACCESS,
1138 &spr_read_generic, &spr_write_40x_tsr,
1139 0x00000000);
1140 }
1141
1142 /* SPR specific to PowerPC 405 implementation */
1143 static void register_405_sprs(CPUPPCState *env)
1144 {
1145 /* MMU */
1146 spr_register(env, SPR_40x_PID, "PID",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_40x_pid,
1149 0x00000000);
1150 spr_register(env, SPR_4xx_CCR0, "CCR0",
1151 SPR_NOACCESS, SPR_NOACCESS,
1152 &spr_read_generic, &spr_write_generic,
1153 0x00700000);
1154 /* Debug interface */
1155 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1156 SPR_NOACCESS, SPR_NOACCESS,
1157 &spr_read_generic, &spr_write_40x_dbcr0,
1158 0x00000000);
1159
1160 spr_register(env, SPR_405_DBCR1, "DBCR1",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_generic,
1163 0x00000000);
1164
1165 spr_register(env, SPR_40x_DBSR, "DBSR",
1166 SPR_NOACCESS, SPR_NOACCESS,
1167 &spr_read_generic, &spr_write_clear,
1168 /* Last reset was system reset */
1169 0x00000300);
1170
1171 spr_register(env, SPR_40x_DAC1, "DAC1",
1172 SPR_NOACCESS, SPR_NOACCESS,
1173 &spr_read_generic, &spr_write_generic,
1174 0x00000000);
1175 spr_register(env, SPR_40x_DAC2, "DAC2",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
1179
1180 spr_register(env, SPR_405_DVC1, "DVC1",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_generic, &spr_write_generic,
1183 0x00000000);
1184
1185 spr_register(env, SPR_405_DVC2, "DVC2",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189
1190 spr_register(env, SPR_40x_IAC1, "IAC1",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 spr_register(env, SPR_40x_IAC2, "IAC2",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
1198
1199 spr_register(env, SPR_405_IAC3, "IAC3",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_generic,
1202 0x00000000);
1203
1204 spr_register(env, SPR_405_IAC4, "IAC4",
1205 SPR_NOACCESS, SPR_NOACCESS,
1206 &spr_read_generic, &spr_write_generic,
1207 0x00000000);
1208 /* Storage control */
1209 spr_register(env, SPR_405_SLER, "SLER",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 &spr_read_generic, &spr_write_40x_sler,
1212 0x00000000);
1213 spr_register(env, SPR_40x_ZPR, "ZPR",
1214 SPR_NOACCESS, SPR_NOACCESS,
1215 &spr_read_generic, &spr_write_generic,
1216 0x00000000);
1217
1218 spr_register(env, SPR_405_SU0R, "SU0R",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 /* SPRG */
1223 spr_register(env, SPR_USPRG0, "USPRG0",
1224 &spr_read_ureg, SPR_NOACCESS,
1225 &spr_read_ureg, SPR_NOACCESS,
1226 0x00000000);
1227 spr_register(env, SPR_SPRG4, "SPRG4",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231 spr_register(env, SPR_SPRG5, "SPRG5",
1232 SPR_NOACCESS, SPR_NOACCESS,
1233 spr_read_generic, &spr_write_generic,
1234 0x00000000);
1235 spr_register(env, SPR_SPRG6, "SPRG6",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 spr_read_generic, &spr_write_generic,
1238 0x00000000);
1239 spr_register(env, SPR_SPRG7, "SPRG7",
1240 SPR_NOACCESS, SPR_NOACCESS,
1241 spr_read_generic, &spr_write_generic,
1242 0x00000000);
1243
1244 /* Bus access control */
1245 /* not emulated, as QEMU never does speculative access */
1246 spr_register(env, SPR_40x_SGR, "SGR",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_generic, &spr_write_generic,
1249 0xFFFFFFFF);
1250 /* not emulated, as QEMU do not emulate caches */
1251 spr_register(env, SPR_40x_DCWR, "DCWR",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_generic, &spr_write_generic,
1254 0x00000000);
1255 }
1256
1257
1258 static void register_5xx_8xx_sprs(CPUPPCState *env)
1259 {
1260 /* Exception processing */
1261 spr_register_kvm(env, SPR_DSISR, "DSISR",
1262 SPR_NOACCESS, SPR_NOACCESS,
1263 &spr_read_generic, &spr_write_generic,
1264 KVM_REG_PPC_DSISR, 0x00000000);
1265 spr_register_kvm(env, SPR_DAR, "DAR",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_generic,
1268 KVM_REG_PPC_DAR, 0x00000000);
1269 /* Timer */
1270 spr_register(env, SPR_DECR, "DECR",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_decr, &spr_write_decr,
1273 0x00000000);
1274
1275 spr_register(env, SPR_MPC_EIE, "EIE",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_generic, &spr_write_generic,
1278 0x00000000);
1279
1280 spr_register(env, SPR_MPC_EID, "EID",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, &spr_write_generic,
1283 0x00000000);
1284
1285 spr_register(env, SPR_MPC_NRI, "NRI",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_generic,
1288 0x00000000);
1289
1290 spr_register(env, SPR_MPC_CMPA, "CMPA",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294
1295 spr_register(env, SPR_MPC_CMPB, "CMPB",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299
1300 spr_register(env, SPR_MPC_CMPC, "CMPC",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304
1305 spr_register(env, SPR_MPC_CMPD, "CMPD",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309
1310 spr_register(env, SPR_MPC_ECR, "ECR",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314
1315 spr_register(env, SPR_MPC_DER, "DER",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319
1320 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_generic,
1323 0x00000000);
1324
1325 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
1329
1330 spr_register(env, SPR_MPC_CMPE, "CMPE",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334
1335 spr_register(env, SPR_MPC_CMPF, "CMPF",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_generic, &spr_write_generic,
1338 0x00000000);
1339
1340 spr_register(env, SPR_MPC_CMPG, "CMPG",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_generic,
1343 0x00000000);
1344
1345 spr_register(env, SPR_MPC_CMPH, "CMPH",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, &spr_write_generic,
1348 0x00000000);
1349
1350 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354
1355 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
1359
1360 spr_register(env, SPR_MPC_BAR, "BAR",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364
1365 spr_register(env, SPR_MPC_DPDR, "DPDR",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369
1370 spr_register(env, SPR_MPC_IMMR, "IMMR",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 }
1375
1376 static void register_5xx_sprs(CPUPPCState *env)
1377 {
1378 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1379 SPR_NOACCESS, SPR_NOACCESS,
1380 &spr_read_generic, &spr_write_generic,
1381 0x00000000);
1382
1383 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 &spr_read_generic, &spr_write_generic,
1386 0x00000000);
1387
1388 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1389 SPR_NOACCESS, SPR_NOACCESS,
1390 &spr_read_generic, &spr_write_generic,
1391 0x00000000);
1392
1393 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, &spr_write_generic,
1396 0x00000000);
1397
1398 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1399 SPR_NOACCESS, SPR_NOACCESS,
1400 &spr_read_generic, &spr_write_generic,
1401 0x00000000);
1402
1403 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1406 0x00000000);
1407
1408 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_generic,
1411 0x00000000);
1412
1413 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417
1418 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_generic, &spr_write_generic,
1421 0x00000000);
1422
1423 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1424 SPR_NOACCESS, SPR_NOACCESS,
1425 &spr_read_generic, &spr_write_generic,
1426 0x00000000);
1427
1428 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1429 SPR_NOACCESS, SPR_NOACCESS,
1430 &spr_read_generic, &spr_write_generic,
1431 0x00000000);
1432
1433 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1434 SPR_NOACCESS, SPR_NOACCESS,
1435 &spr_read_generic, &spr_write_generic,
1436 0x00000000);
1437
1438 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1439 SPR_NOACCESS, SPR_NOACCESS,
1440 &spr_read_generic, &spr_write_generic,
1441 0x00000000);
1442
1443 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1444 SPR_NOACCESS, SPR_NOACCESS,
1445 &spr_read_generic, &spr_write_generic,
1446 0x00000000);
1447
1448 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_generic,
1451 0x00000000);
1452
1453 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 &spr_read_generic, &spr_write_generic,
1456 0x00000000);
1457
1458 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462
1463 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1464 SPR_NOACCESS, SPR_NOACCESS,
1465 &spr_read_generic, &spr_write_generic,
1466 0x00000000);
1467
1468 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1469 SPR_NOACCESS, SPR_NOACCESS,
1470 &spr_read_generic, &spr_write_generic,
1471 0x00000000);
1472
1473 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477
1478 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_generic,
1481 0x00000000);
1482 }
1483
1484 static void register_8xx_sprs(CPUPPCState *env)
1485 {
1486
1487 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1488 SPR_NOACCESS, SPR_NOACCESS,
1489 &spr_read_generic, &spr_write_generic,
1490 0x00000000);
1491
1492 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1493 SPR_NOACCESS, SPR_NOACCESS,
1494 &spr_read_generic, &spr_write_generic,
1495 0x00000000);
1496
1497 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1500 0x00000000);
1501
1502 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, &spr_write_generic,
1505 0x00000000);
1506
1507 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1508 SPR_NOACCESS, SPR_NOACCESS,
1509 &spr_read_generic, &spr_write_generic,
1510 0x00000000);
1511
1512 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, &spr_write_generic,
1515 0x00000000);
1516
1517 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1518 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_generic,
1520 0x00000000);
1521
1522 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1525 0x00000000);
1526
1527 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_generic,
1530 0x00000000);
1531
1532 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, &spr_write_generic,
1535 0x00000000);
1536
1537 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_generic,
1540 0x00000000);
1541
1542 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1543 SPR_NOACCESS, SPR_NOACCESS,
1544 &spr_read_generic, &spr_write_generic,
1545 0x00000000);
1546
1547 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_generic,
1550 0x00000000);
1551
1552 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_generic,
1555 0x00000000);
1556
1557 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, &spr_write_generic,
1560 0x00000000);
1561
1562 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1563 SPR_NOACCESS, SPR_NOACCESS,
1564 &spr_read_generic, &spr_write_generic,
1565 0x00000000);
1566
1567 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571
1572 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1573 SPR_NOACCESS, SPR_NOACCESS,
1574 &spr_read_generic, &spr_write_generic,
1575 0x00000000);
1576
1577 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, &spr_write_generic,
1580 0x00000000);
1581
1582 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000);
1586
1587 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1588 SPR_NOACCESS, SPR_NOACCESS,
1589 &spr_read_generic, &spr_write_generic,
1590 0x00000000);
1591
1592 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, &spr_write_generic,
1595 0x00000000);
1596
1597 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1598 SPR_NOACCESS, SPR_NOACCESS,
1599 &spr_read_generic, &spr_write_generic,
1600 0x00000000);
1601
1602 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1603 SPR_NOACCESS, SPR_NOACCESS,
1604 &spr_read_generic, &spr_write_generic,
1605 0x00000000);
1606
1607 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1608 SPR_NOACCESS, SPR_NOACCESS,
1609 &spr_read_generic, &spr_write_generic,
1610 0x00000000);
1611 }
1612
1613 /*
1614 * AMR => SPR 29 (Power 2.04)
1615 * CTRL => SPR 136 (Power 2.04)
1616 * CTRL => SPR 152 (Power 2.04)
1617 * SCOMC => SPR 276 (64 bits ?)
1618 * SCOMD => SPR 277 (64 bits ?)
1619 * TBU40 => SPR 286 (Power 2.04 hypv)
1620 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1621 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1622 * HDSISR => SPR 306 (Power 2.04 hypv)
1623 * HDAR => SPR 307 (Power 2.04 hypv)
1624 * PURR => SPR 309 (Power 2.04 hypv)
1625 * HDEC => SPR 310 (Power 2.04 hypv)
1626 * HIOR => SPR 311 (hypv)
1627 * RMOR => SPR 312 (970)
1628 * HRMOR => SPR 313 (Power 2.04 hypv)
1629 * HSRR0 => SPR 314 (Power 2.04 hypv)
1630 * HSRR1 => SPR 315 (Power 2.04 hypv)
1631 * LPIDR => SPR 317 (970)
1632 * EPR => SPR 702 (Power 2.04 emb)
1633 * perf => 768-783 (Power 2.04)
1634 * perf => 784-799 (Power 2.04)
1635 * PPR => SPR 896 (Power 2.04)
1636 * DABRX => 1015 (Power 2.04 hypv)
1637 * FPECR => SPR 1022 (?)
1638 * ... and more (thermal management, performance counters, ...)
1639 */
1640
1641 /*****************************************************************************/
1642 /* Exception vectors models */
1643 static void init_excp_4xx_softmmu(CPUPPCState *env)
1644 {
1645 #if !defined(CONFIG_USER_ONLY)
1646 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1647 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1648 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1649 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1650 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1651 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1652 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1653 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1654 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1655 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1656 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1657 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1658 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1659 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1660 env->ivor_mask = 0x0000FFF0UL;
1661 env->ivpr_mask = 0xFFFF0000UL;
1662 /* Hardware reset vector */
1663 env->hreset_vector = 0xFFFFFFFCUL;
1664 #endif
1665 }
1666
1667 static void init_excp_MPC5xx(CPUPPCState *env)
1668 {
1669 #if !defined(CONFIG_USER_ONLY)
1670 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1671 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1672 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1673 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1674 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1675 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1676 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1677 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1678 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1679 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1680 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1681 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1682 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1683 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1684 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1685 env->ivor_mask = 0x0000FFF0UL;
1686 env->ivpr_mask = 0xFFFF0000UL;
1687 /* Hardware reset vector */
1688 env->hreset_vector = 0x00000100UL;
1689 #endif
1690 }
1691
1692 static void init_excp_MPC8xx(CPUPPCState *env)
1693 {
1694 #if !defined(CONFIG_USER_ONLY)
1695 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1696 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1697 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1698 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1699 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1700 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1701 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1702 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1703 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1704 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1705 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1706 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1707 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1708 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1709 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1710 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1711 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1712 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1713 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1714 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1715 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1716 env->ivor_mask = 0x0000FFF0UL;
1717 env->ivpr_mask = 0xFFFF0000UL;
1718 /* Hardware reset vector */
1719 env->hreset_vector = 0x00000100UL;
1720 #endif
1721 }
1722
1723 static void init_excp_G2(CPUPPCState *env)
1724 {
1725 #if !defined(CONFIG_USER_ONLY)
1726 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1727 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1728 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1729 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1730 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1731 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1732 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1733 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1734 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1735 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
1736 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1737 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1738 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1739 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1740 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1741 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1742 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1743 /* Hardware reset vector */
1744 env->hreset_vector = 0x00000100UL;
1745 #endif
1746 }
1747
1748 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
1749 {
1750 #if !defined(CONFIG_USER_ONLY)
1751 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1752 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1753 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1754 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1755 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1756 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1757 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1758 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1759 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1760 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1761 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1762 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1763 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1764 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1765 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1766 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1767 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1768 /*
1769 * These two are the same IVOR as POWERPC_EXCP_VPU and
1770 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1771 * powerpc_excp().
1772 */
1773 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1774 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
1775
1776 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
1777 env->ivor_mask = 0x0000FFF7UL;
1778 env->ivpr_mask = ivpr_mask;
1779 /* Hardware reset vector */
1780 env->hreset_vector = 0xFFFFFFFCUL;
1781 #endif
1782 }
1783
1784 static void init_excp_BookE(CPUPPCState *env)
1785 {
1786 #if !defined(CONFIG_USER_ONLY)
1787 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1788 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1789 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1790 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1791 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1792 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1793 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1794 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1795 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1796 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1797 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1798 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1799 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1800 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1801 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1802 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1803 env->ivor_mask = 0x0000FFF0UL;
1804 env->ivpr_mask = 0xFFFF0000UL;
1805 /* Hardware reset vector */
1806 env->hreset_vector = 0xFFFFFFFCUL;
1807 #endif
1808 }
1809
1810 static void init_excp_603(CPUPPCState *env)
1811 {
1812 #if !defined(CONFIG_USER_ONLY)
1813 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1814 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1815 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1816 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1817 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1818 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1819 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1820 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1821 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1822 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1823 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1824 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1825 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1826 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1827 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1828 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1829 /* Hardware reset vector */
1830 env->hreset_vector = 0x00000100UL;
1831 #endif
1832 }
1833
1834 static void init_excp_604(CPUPPCState *env)
1835 {
1836 #if !defined(CONFIG_USER_ONLY)
1837 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1838 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1839 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1840 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1841 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1842 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1843 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1844 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1845 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1846 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1847 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1848 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1849 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1850 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1851 /* Hardware reset vector */
1852 env->hreset_vector = 0x00000100UL;
1853 #endif
1854 }
1855
1856 static void init_excp_7x0(CPUPPCState *env)
1857 {
1858 #if !defined(CONFIG_USER_ONLY)
1859 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1860 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1861 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1862 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1863 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1864 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1865 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1866 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1867 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1868 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1869 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1870 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1871 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1872 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1873 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1874 /* Hardware reset vector */
1875 env->hreset_vector = 0x00000100UL;
1876 #endif
1877 }
1878
1879 static void init_excp_750cl(CPUPPCState *env)
1880 {
1881 #if !defined(CONFIG_USER_ONLY)
1882 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1883 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1884 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1885 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1886 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1887 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1888 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1889 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1890 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1891 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1892 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1893 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1894 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1895 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1896 /* Hardware reset vector */
1897 env->hreset_vector = 0x00000100UL;
1898 #endif
1899 }
1900
1901 static void init_excp_750cx(CPUPPCState *env)
1902 {
1903 #if !defined(CONFIG_USER_ONLY)
1904 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1905 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1906 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1907 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1908 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1909 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1910 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1911 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1912 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1913 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1914 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1915 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1916 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1917 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1918 /* Hardware reset vector */
1919 env->hreset_vector = 0x00000100UL;
1920 #endif
1921 }
1922
1923 /* XXX: Check if this is correct */
1924 static void init_excp_7x5(CPUPPCState *env)
1925 {
1926 #if !defined(CONFIG_USER_ONLY)
1927 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1928 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1929 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1930 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1931 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1932 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1933 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1934 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1935 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1936 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1937 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1938 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1939 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1940 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1941 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1942 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1943 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1944 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1945 /* Hardware reset vector */
1946 env->hreset_vector = 0x00000100UL;
1947 #endif
1948 }
1949
1950 static void init_excp_7400(CPUPPCState *env)
1951 {
1952 #if !defined(CONFIG_USER_ONLY)
1953 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1954 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1955 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1956 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1957 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1958 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1959 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1960 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1961 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1962 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1963 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1964 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1965 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1966 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1967 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1968 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1969 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1970 /* Hardware reset vector */
1971 env->hreset_vector = 0x00000100UL;
1972 #endif
1973 }
1974
1975 static void init_excp_7450(CPUPPCState *env)
1976 {
1977 #if !defined(CONFIG_USER_ONLY)
1978 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1979 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1980 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1981 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1982 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1983 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1984 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1985 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1986 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1987 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1988 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1989 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1990 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1991 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1992 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1993 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1994 /* Hardware reset vector */
1995 env->hreset_vector = 0x00000100UL;
1996 #endif
1997 }
1998
1999 #if defined(TARGET_PPC64)
2000 static void init_excp_970(CPUPPCState *env)
2001 {
2002 #if !defined(CONFIG_USER_ONLY)
2003 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2004 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2005 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2006 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2007 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2008 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2009 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2010 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2011 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2012 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2013 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2014 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2015 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2016 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2017 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2018 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2019 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2020 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2021 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2022 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2023 /* Hardware reset vector */
2024 env->hreset_vector = 0x0000000000000100ULL;
2025 #endif
2026 }
2027
2028 static void init_excp_POWER7(CPUPPCState *env)
2029 {
2030 #if !defined(CONFIG_USER_ONLY)
2031 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2032 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2033 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2034 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2035 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2036 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2037 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2038 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2039 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2040 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2041 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2042 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2043 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2044 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2045 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2046 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2047 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2048 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2049 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2050 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2051 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2052 /* Hardware reset vector */
2053 env->hreset_vector = 0x0000000000000100ULL;
2054 #endif
2055 }
2056
2057 static void init_excp_POWER8(CPUPPCState *env)
2058 {
2059 init_excp_POWER7(env);
2060
2061 #if !defined(CONFIG_USER_ONLY)
2062 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2063 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2064 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2065 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2066
2067 /* Userland exceptions without vector value in PowerISA v3.1 */
2068 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
2069 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
2070 #endif
2071 }
2072
2073 static void init_excp_POWER9(CPUPPCState *env)
2074 {
2075 init_excp_POWER8(env);
2076
2077 #if !defined(CONFIG_USER_ONLY)
2078 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2079 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2080 #endif
2081 }
2082
2083 static void init_excp_POWER10(CPUPPCState *env)
2084 {
2085 init_excp_POWER9(env);
2086 }
2087
2088 #endif
2089
2090 static int check_pow_hid0(CPUPPCState *env)
2091 {
2092 if (env->spr[SPR_HID0] & 0x00E00000) {
2093 return 1;
2094 }
2095
2096 return 0;
2097 }
2098
2099 static int check_pow_hid0_74xx(CPUPPCState *env)
2100 {
2101 if (env->spr[SPR_HID0] & 0x00600000) {
2102 return 1;
2103 }
2104
2105 return 0;
2106 }
2107
2108 static void init_proc_405(CPUPPCState *env)
2109 {
2110 register_40x_sprs(env);
2111 register_405_sprs(env);
2112 register_usprgh_sprs(env);
2113
2114 /* Memory management */
2115 #if !defined(CONFIG_USER_ONLY)
2116 env->nb_tlb = 64;
2117 env->nb_ways = 1;
2118 env->id_tlbs = 0;
2119 env->tlb_type = TLB_EMB;
2120 #endif
2121 init_excp_4xx_softmmu(env);
2122 env->dcache_line_size = 32;
2123 env->icache_line_size = 32;
2124 /* Allocate hardware IRQ controller */
2125 ppc40x_irq_init(env_archcpu(env));
2126
2127 SET_FIT_PERIOD(8, 12, 16, 20);
2128 SET_WDT_PERIOD(16, 20, 24, 28);
2129 }
2130
2131 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2132 {
2133 DeviceClass *dc = DEVICE_CLASS(oc);
2134 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2135
2136 dc->desc = "PowerPC 405";
2137 pcc->init_proc = init_proc_405;
2138 pcc->check_pow = check_pow_nocheck;
2139 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2140 PPC_DCR | PPC_WRTEE |
2141 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2142 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2143 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2144 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2145 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2146 pcc->msr_mask = (1ull << MSR_WE) |
2147 (1ull << MSR_CE) |
2148 (1ull << MSR_EE) |
2149 (1ull << MSR_PR) |
2150 (1ull << MSR_FP) |
2151 (1ull << MSR_ME) |
2152 (1ull << MSR_DWE) |
2153 (1ull << MSR_DE) |
2154 (1ull << MSR_IR) |
2155 (1ull << MSR_DR);
2156 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2157 pcc->excp_model = POWERPC_EXCP_40x;
2158 pcc->bus_model = PPC_FLAGS_INPUT_405;
2159 pcc->bfd_mach = bfd_mach_ppc_403;
2160 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2161 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2162 }
2163
2164 static void init_proc_440EP(CPUPPCState *env)
2165 {
2166 register_BookE_sprs(env, 0x000000000000FFFFULL);
2167 register_440_sprs(env);
2168 register_usprgh_sprs(env);
2169
2170 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, &spr_write_generic,
2173 0x00000000);
2174 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, &spr_write_generic,
2177 0x00000000);
2178 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2179 SPR_NOACCESS, SPR_NOACCESS,
2180 &spr_read_generic, &spr_write_generic,
2181 0x00000000);
2182
2183 spr_register(env, SPR_440_CCR1, "CCR1",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187 /* Memory management */
2188 #if !defined(CONFIG_USER_ONLY)
2189 env->nb_tlb = 64;
2190 env->nb_ways = 1;
2191 env->id_tlbs = 0;
2192 env->tlb_type = TLB_EMB;
2193 #endif
2194 init_excp_BookE(env);
2195 env->dcache_line_size = 32;
2196 env->icache_line_size = 32;
2197 ppc40x_irq_init(env_archcpu(env));
2198
2199 SET_FIT_PERIOD(12, 16, 20, 24);
2200 SET_WDT_PERIOD(20, 24, 28, 32);
2201 }
2202
2203 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2204 {
2205 DeviceClass *dc = DEVICE_CLASS(oc);
2206 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2207
2208 dc->desc = "PowerPC 440 EP";
2209 pcc->init_proc = init_proc_440EP;
2210 pcc->check_pow = check_pow_nocheck;
2211 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2212 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2213 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2214 PPC_FLOAT_STFIWX |
2215 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2216 PPC_CACHE | PPC_CACHE_ICBI |
2217 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2218 PPC_MEM_TLBSYNC | PPC_MFTB |
2219 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2220 PPC_440_SPEC;
2221 pcc->msr_mask = (1ull << MSR_POW) |
2222 (1ull << MSR_CE) |
2223 (1ull << MSR_EE) |
2224 (1ull << MSR_PR) |
2225 (1ull << MSR_FP) |
2226 (1ull << MSR_ME) |
2227 (1ull << MSR_FE0) |
2228 (1ull << MSR_DWE) |
2229 (1ull << MSR_DE) |
2230 (1ull << MSR_FE1) |
2231 (1ull << MSR_IR) |
2232 (1ull << MSR_DR);
2233 pcc->mmu_model = POWERPC_MMU_BOOKE;
2234 pcc->excp_model = POWERPC_EXCP_BOOKE;
2235 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2236 pcc->bfd_mach = bfd_mach_ppc_403;
2237 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2238 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2239 }
2240
2241 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2242 {
2243 DeviceClass *dc = DEVICE_CLASS(oc);
2244 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2245
2246 dc->desc = "PowerPC 460 EX";
2247 pcc->init_proc = init_proc_440EP;
2248 pcc->check_pow = check_pow_nocheck;
2249 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2250 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2251 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2252 PPC_FLOAT_STFIWX |
2253 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2254 PPC_CACHE | PPC_CACHE_ICBI |
2255 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2256 PPC_MEM_TLBSYNC | PPC_MFTB |
2257 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2258 PPC_440_SPEC;
2259 pcc->msr_mask = (1ull << MSR_POW) |
2260 (1ull << MSR_CE) |
2261 (1ull << MSR_EE) |
2262 (1ull << MSR_PR) |
2263 (1ull << MSR_FP) |
2264 (1ull << MSR_ME) |
2265 (1ull << MSR_FE0) |
2266 (1ull << MSR_DWE) |
2267 (1ull << MSR_DE) |
2268 (1ull << MSR_FE1) |
2269 (1ull << MSR_IR) |
2270 (1ull << MSR_DR);
2271 pcc->mmu_model = POWERPC_MMU_BOOKE;
2272 pcc->excp_model = POWERPC_EXCP_BOOKE;
2273 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2274 pcc->bfd_mach = bfd_mach_ppc_403;
2275 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2276 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2277 }
2278
2279 static void init_proc_440GP(CPUPPCState *env)
2280 {
2281 register_BookE_sprs(env, 0x000000000000FFFFULL);
2282 register_440_sprs(env);
2283 register_usprgh_sprs(env);
2284
2285 /* Memory management */
2286 #if !defined(CONFIG_USER_ONLY)
2287 env->nb_tlb = 64;
2288 env->nb_ways = 1;
2289 env->id_tlbs = 0;
2290 env->tlb_type = TLB_EMB;
2291 #endif
2292 init_excp_BookE(env);
2293 env->dcache_line_size = 32;
2294 env->icache_line_size = 32;
2295 /* XXX: TODO: allocate internal IRQ controller */
2296
2297 SET_FIT_PERIOD(12, 16, 20, 24);
2298 SET_WDT_PERIOD(20, 24, 28, 32);
2299 }
2300
2301 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2302 {
2303 DeviceClass *dc = DEVICE_CLASS(oc);
2304 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2305
2306 dc->desc = "PowerPC 440 GP";
2307 pcc->init_proc = init_proc_440GP;
2308 pcc->check_pow = check_pow_nocheck;
2309 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2310 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2311 PPC_CACHE | PPC_CACHE_ICBI |
2312 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2313 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2314 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2315 PPC_440_SPEC;
2316 pcc->msr_mask = (1ull << MSR_POW) |
2317 (1ull << MSR_CE) |
2318 (1ull << MSR_EE) |
2319 (1ull << MSR_PR) |
2320 (1ull << MSR_FP) |
2321 (1ull << MSR_ME) |
2322 (1ull << MSR_FE0) |
2323 (1ull << MSR_DWE) |
2324 (1ull << MSR_DE) |
2325 (1ull << MSR_FE1) |
2326 (1ull << MSR_IR) |
2327 (1ull << MSR_DR);
2328 pcc->mmu_model = POWERPC_MMU_BOOKE;
2329 pcc->excp_model = POWERPC_EXCP_BOOKE;
2330 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2331 pcc->bfd_mach = bfd_mach_ppc_403;
2332 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2333 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2334 }
2335
2336 static void init_proc_440x5(CPUPPCState *env)
2337 {
2338 register_BookE_sprs(env, 0x000000000000FFFFULL);
2339 register_440_sprs(env);
2340 register_usprgh_sprs(env);
2341
2342 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2343 SPR_NOACCESS, SPR_NOACCESS,
2344 &spr_read_generic, &spr_write_generic,
2345 0x00000000);
2346 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2351 SPR_NOACCESS, SPR_NOACCESS,
2352 &spr_read_generic, &spr_write_generic,
2353 0x00000000);
2354
2355 spr_register(env, SPR_440_CCR1, "CCR1",
2356 SPR_NOACCESS, SPR_NOACCESS,
2357 &spr_read_generic, &spr_write_generic,
2358 0x00000000);
2359 /* Memory management */
2360 #if !defined(CONFIG_USER_ONLY)
2361 env->nb_tlb = 64;
2362 env->nb_ways = 1;
2363 env->id_tlbs = 0;
2364 env->tlb_type = TLB_EMB;
2365 #endif
2366 init_excp_BookE(env);
2367 env->dcache_line_size = 32;
2368 env->icache_line_size = 32;
2369 ppc40x_irq_init(env_archcpu(env));
2370
2371 SET_FIT_PERIOD(12, 16, 20, 24);
2372 SET_WDT_PERIOD(20, 24, 28, 32);
2373 }
2374
2375 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2376 {
2377 DeviceClass *dc = DEVICE_CLASS(oc);
2378 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2379
2380 dc->desc = "PowerPC 440x5";
2381 pcc->init_proc = init_proc_440x5;
2382 pcc->check_pow = check_pow_nocheck;
2383 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2384 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2385 PPC_CACHE | PPC_CACHE_ICBI |
2386 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2387 PPC_MEM_TLBSYNC | PPC_MFTB |
2388 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2389 PPC_440_SPEC;
2390 pcc->msr_mask = (1ull << MSR_POW) |
2391 (1ull << MSR_CE) |
2392 (1ull << MSR_EE) |
2393 (1ull << MSR_PR) |
2394 (1ull << MSR_FP) |
2395 (1ull << MSR_ME) |
2396 (1ull << MSR_FE0) |
2397 (1ull << MSR_DWE) |
2398 (1ull << MSR_DE) |
2399 (1ull << MSR_FE1) |
2400 (1ull << MSR_IR) |
2401 (1ull << MSR_DR);
2402 pcc->mmu_model = POWERPC_MMU_BOOKE;
2403 pcc->excp_model = POWERPC_EXCP_BOOKE;
2404 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2405 pcc->bfd_mach = bfd_mach_ppc_403;
2406 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2407 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2408 }
2409
2410 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2411 {
2412 DeviceClass *dc = DEVICE_CLASS(oc);
2413 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2414
2415 dc->desc = "PowerPC 440x5 with double precision FPU";
2416 pcc->init_proc = init_proc_440x5;
2417 pcc->check_pow = check_pow_nocheck;
2418 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2419 PPC_FLOAT | PPC_FLOAT_FSQRT |
2420 PPC_FLOAT_STFIWX |
2421 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2422 PPC_CACHE | PPC_CACHE_ICBI |
2423 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2424 PPC_MEM_TLBSYNC | PPC_MFTB |
2425 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2426 PPC_440_SPEC;
2427 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2428 pcc->msr_mask = (1ull << MSR_POW) |
2429 (1ull << MSR_CE) |
2430 (1ull << MSR_EE) |
2431 (1ull << MSR_PR) |
2432 (1ull << MSR_FP) |
2433 (1ull << MSR_ME) |
2434 (1ull << MSR_FE0) |
2435 (1ull << MSR_DWE) |
2436 (1ull << MSR_DE) |
2437 (1ull << MSR_FE1) |
2438 (1ull << MSR_IR) |
2439 (1ull << MSR_DR);
2440 pcc->mmu_model = POWERPC_MMU_BOOKE;
2441 pcc->excp_model = POWERPC_EXCP_BOOKE;
2442 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2443 pcc->bfd_mach = bfd_mach_ppc_403;
2444 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2445 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2446 }
2447
2448 static void init_proc_MPC5xx(CPUPPCState *env)
2449 {
2450 register_5xx_8xx_sprs(env);
2451 register_5xx_sprs(env);
2452 init_excp_MPC5xx(env);
2453 env->dcache_line_size = 32;
2454 env->icache_line_size = 32;
2455 /* XXX: TODO: allocate internal IRQ controller */
2456 }
2457
2458 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2459 {
2460 DeviceClass *dc = DEVICE_CLASS(oc);
2461 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2462
2463 dc->desc = "Freescale 5xx cores (aka RCPU)";
2464 pcc->init_proc = init_proc_MPC5xx;
2465 pcc->check_pow = check_pow_none;
2466 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2467 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2468 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2469 PPC_MFTB;
2470 pcc->msr_mask = (1ull << MSR_ILE) |
2471 (1ull << MSR_EE) |
2472 (1ull << MSR_PR) |
2473 (1ull << MSR_FP) |
2474 (1ull << MSR_ME) |
2475 (1ull << MSR_FE0) |
2476 (1ull << MSR_SE) |
2477 (1ull << MSR_DE) |
2478 (1ull << MSR_FE1) |
2479 (1ull << MSR_EP) |
2480 (1ull << MSR_RI) |
2481 (1ull << MSR_LE);
2482 pcc->mmu_model = POWERPC_MMU_REAL;
2483 pcc->excp_model = POWERPC_EXCP_6xx;
2484 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2485 pcc->bfd_mach = bfd_mach_ppc_505;
2486 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2487 POWERPC_FLAG_BUS_CLK;
2488 }
2489
2490 static void init_proc_MPC8xx(CPUPPCState *env)
2491 {
2492 register_5xx_8xx_sprs(env);
2493 register_8xx_sprs(env);
2494 init_excp_MPC8xx(env);
2495 env->dcache_line_size = 32;
2496 env->icache_line_size = 32;
2497 /* XXX: TODO: allocate internal IRQ controller */
2498 }
2499
2500 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2501 {
2502 DeviceClass *dc = DEVICE_CLASS(oc);
2503 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2504
2505 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2506 pcc->init_proc = init_proc_MPC8xx;
2507 pcc->check_pow = check_pow_none;
2508 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2509 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2510 PPC_CACHE_ICBI | PPC_MFTB;
2511 pcc->msr_mask = (1ull << MSR_ILE) |
2512 (1ull << MSR_EE) |
2513 (1ull << MSR_PR) |
2514 (1ull << MSR_FP) |
2515 (1ull << MSR_ME) |
2516 (1ull << MSR_SE) |
2517 (1ull << MSR_DE) |
2518 (1ull << MSR_EP) |
2519 (1ull << MSR_IR) |
2520 (1ull << MSR_DR) |
2521 (1ull << MSR_RI) |
2522 (1ull << MSR_LE);
2523 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2524 pcc->excp_model = POWERPC_EXCP_6xx;
2525 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2526 pcc->bfd_mach = bfd_mach_ppc_860;
2527 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2528 POWERPC_FLAG_BUS_CLK;
2529 }
2530
2531 /* Freescale 82xx cores (aka PowerQUICC-II) */
2532
2533 static void init_proc_G2(CPUPPCState *env)
2534 {
2535 register_non_embedded_sprs(env);
2536 register_sdr1_sprs(env);
2537 register_G2_sprs(env);
2538
2539 /* Memory management */
2540 register_low_BATs(env);
2541 register_high_BATs(env);
2542 register_6xx_7xx_soft_tlb(env, 64, 2);
2543 init_excp_G2(env);
2544 env->dcache_line_size = 32;
2545 env->icache_line_size = 32;
2546 /* Allocate hardware IRQ controller */
2547 ppc6xx_irq_init(env_archcpu(env));
2548 }
2549
2550 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
2551 {
2552 DeviceClass *dc = DEVICE_CLASS(oc);
2553 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2554
2555 dc->desc = "PowerPC G2";
2556 pcc->init_proc = init_proc_G2;
2557 pcc->check_pow = check_pow_hid0;
2558 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2559 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2560 PPC_FLOAT_STFIWX |
2561 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2562 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2563 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2564 PPC_SEGMENT | PPC_EXTERN;
2565 pcc->msr_mask = (1ull << MSR_POW) |
2566 (1ull << MSR_TGPR) |
2567 (1ull << MSR_EE) |
2568 (1ull << MSR_PR) |
2569 (1ull << MSR_FP) |
2570 (1ull << MSR_ME) |
2571 (1ull << MSR_FE0) |
2572 (1ull << MSR_SE) |
2573 (1ull << MSR_DE) |
2574 (1ull << MSR_FE1) |
2575 (1ull << MSR_AL) |
2576 (1ull << MSR_EP) |
2577 (1ull << MSR_IR) |
2578 (1ull << MSR_DR) |
2579 (1ull << MSR_RI);
2580 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2581 pcc->excp_model = POWERPC_EXCP_6xx;
2582 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2583 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2584 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2585 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2586 }
2587
2588 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
2589 {
2590 DeviceClass *dc = DEVICE_CLASS(oc);
2591 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2592
2593 dc->desc = "PowerPC G2LE";
2594 pcc->init_proc = init_proc_G2;
2595 pcc->check_pow = check_pow_hid0;
2596 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2597 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2598 PPC_FLOAT_STFIWX |
2599 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2600 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2601 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2602 PPC_SEGMENT | PPC_EXTERN;
2603 pcc->msr_mask = (1ull << MSR_POW) |
2604 (1ull << MSR_TGPR) |
2605 (1ull << MSR_ILE) |
2606 (1ull << MSR_EE) |
2607 (1ull << MSR_PR) |
2608 (1ull << MSR_FP) |
2609 (1ull << MSR_ME) |
2610 (1ull << MSR_FE0) |
2611 (1ull << MSR_SE) |
2612 (1ull << MSR_DE) |
2613 (1ull << MSR_FE1) |
2614 (1ull << MSR_AL) |
2615 (1ull << MSR_EP) |
2616 (1ull << MSR_IR) |
2617 (1ull << MSR_DR) |
2618 (1ull << MSR_RI) |
2619 (1ull << MSR_LE);
2620 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2621 pcc->excp_model = POWERPC_EXCP_6xx;
2622 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2623 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2624 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2625 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2626 }
2627
2628 static void init_proc_e200(CPUPPCState *env)
2629 {
2630 register_BookE_sprs(env, 0x000000070000FFFFULL);
2631
2632 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2633 &spr_read_spefscr, &spr_write_spefscr,
2634 &spr_read_spefscr, &spr_write_spefscr,
2635 0x00000000);
2636 /* Memory management */
2637 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
2638 register_usprgh_sprs(env);
2639
2640 spr_register(env, SPR_HID0, "HID0",
2641 SPR_NOACCESS, SPR_NOACCESS,
2642 &spr_read_generic, &spr_write_generic,
2643 0x00000000);
2644
2645 spr_register(env, SPR_HID1, "HID1",
2646 SPR_NOACCESS, SPR_NOACCESS,
2647 &spr_read_generic, &spr_write_generic,
2648 0x00000000);
2649
2650 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
2651 SPR_NOACCESS, SPR_NOACCESS,
2652 &spr_read_generic, &spr_write_generic,
2653 0x00000000);
2654
2655 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2656 SPR_NOACCESS, SPR_NOACCESS,
2657 &spr_read_generic, &spr_write_generic,
2658 0x00000000);
2659
2660 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
2661 SPR_NOACCESS, SPR_NOACCESS,
2662 &spr_read_generic, &spr_write_generic,
2663 0x00000000);
2664
2665 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
2666 SPR_NOACCESS, SPR_NOACCESS,
2667 &spr_read_generic, &spr_write_generic,
2668 0x00000000);
2669
2670 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
2671 SPR_NOACCESS, SPR_NOACCESS,
2672 &spr_read_generic, &spr_write_generic,
2673 0x00000000);
2674
2675 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2676 &spr_read_generic, SPR_NOACCESS,
2677 &spr_read_generic, SPR_NOACCESS,
2678 0x00000000);
2679
2680 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2681 SPR_NOACCESS, SPR_NOACCESS,
2682 &spr_read_generic, &spr_write_generic,
2683 0x00000000);
2684
2685 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
2686 SPR_NOACCESS, SPR_NOACCESS,
2687 &spr_read_generic, &spr_write_generic,
2688 0x00000000);
2689
2690 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
2691 SPR_NOACCESS, SPR_NOACCESS,
2692 &spr_read_generic, &spr_write_generic,
2693 0x00000000);
2694
2695 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
2696 SPR_NOACCESS, SPR_NOACCESS,
2697 &spr_read_generic, &spr_write_generic,
2698 0x00000000);
2699
2700 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2701 SPR_NOACCESS, SPR_NOACCESS,
2702 &spr_read_generic, &spr_write_generic,
2703 0x00000000);
2704
2705 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2706 SPR_NOACCESS, SPR_NOACCESS,
2707 &spr_read_generic, &spr_write_generic,
2708 0x00000000);
2709
2710 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2711 SPR_NOACCESS, SPR_NOACCESS,
2712 &spr_read_generic, &spr_write_generic,
2713 0x00000000); /* TOFIX */
2714 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
2715 SPR_NOACCESS, SPR_NOACCESS,
2716 &spr_read_generic, &spr_write_generic,
2717 0x00000000);
2718 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
2719 SPR_NOACCESS, SPR_NOACCESS,
2720 &spr_read_generic, &spr_write_generic,
2721 0x00000000);
2722 #if !defined(CONFIG_USER_ONLY)
2723 env->nb_tlb = 64;
2724 env->nb_ways = 1;
2725 env->id_tlbs = 0;
2726 env->tlb_type = TLB_EMB;
2727 #endif
2728 init_excp_e200(env, 0xFFFF0000UL);
2729 env->dcache_line_size = 32;
2730 env->icache_line_size = 32;
2731 /* XXX: TODO: allocate internal IRQ controller */
2732 }
2733
2734 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
2735 {
2736 DeviceClass *dc = DEVICE_CLASS(oc);
2737 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2738
2739 dc->desc = "e200 core";
2740 pcc->init_proc = init_proc_e200;
2741 pcc->check_pow = check_pow_hid0;
2742 /*
2743 * XXX: unimplemented instructions:
2744 * dcblc
2745 * dcbtlst
2746 * dcbtstls
2747 * icblc
2748 * icbtls
2749 * tlbivax
2750 * all SPE multiply-accumulate instructions
2751 */
2752 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
2753 PPC_SPE | PPC_SPE_SINGLE |
2754 PPC_WRTEE | PPC_RFDI |
2755 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
2756 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2757 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
2758 PPC_BOOKE;
2759 pcc->msr_mask = (1ull << MSR_UCLE) |
2760 (1ull << MSR_SPE) |
2761 (1ull << MSR_POW) |
2762 (1ull << MSR_CE) |
2763 (1ull << MSR_EE) |
2764 (1ull << MSR_PR) |
2765 (1ull << MSR_FP) |
2766 (1ull << MSR_ME) |
2767 (1ull << MSR_FE0) |
2768 (1ull << MSR_DWE) |
2769 (1ull << MSR_DE) |
2770 (1ull << MSR_FE1) |
2771 (1ull << MSR_IR) |
2772 (1ull << MSR_DR);
2773 pcc->mmu_model = POWERPC_MMU_BOOKE206;
2774 pcc->excp_model = POWERPC_EXCP_BOOKE;
2775 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2776 pcc->bfd_mach = bfd_mach_ppc_860;
2777 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
2778 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
2779 POWERPC_FLAG_BUS_CLK;
2780 }
2781
2782 enum fsl_e500_version {
2783 fsl_e500v1,
2784 fsl_e500v2,
2785 fsl_e500mc,
2786 fsl_e5500,
2787 fsl_e6500,
2788 };
2789
2790 static void init_proc_e500(CPUPPCState *env, int version)
2791 {
2792 uint32_t tlbncfg[2];
2793 uint64_t ivor_mask;
2794 uint64_t ivpr_mask = 0xFFFF0000ULL;
2795 uint32_t l1cfg0 = 0x3800 /* 8 ways */
2796 | 0x0020; /* 32 kb */
2797 uint32_t l1cfg1 = 0x3800 /* 8 ways */
2798 | 0x0020; /* 32 kb */
2799 uint32_t mmucfg = 0;
2800 #if !defined(CONFIG_USER_ONLY)
2801 int i;
2802 #endif
2803
2804 /*
2805 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
2806 * complain when accessing them.
2807 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
2808 */
2809 switch (version) {
2810 case fsl_e500v1:
2811 case fsl_e500v2:
2812 default:
2813 ivor_mask = 0x0000000F0000FFFFULL;
2814 break;
2815 case fsl_e500mc:
2816 case fsl_e5500:
2817 ivor_mask = 0x000003FE0000FFFFULL;
2818 break;
2819 case fsl_e6500:
2820 ivor_mask = 0x000003FF0000FFFFULL;
2821 break;
2822 }
2823 register_BookE_sprs(env, ivor_mask);
2824
2825 spr_register(env, SPR_USPRG3, "USPRG3",
2826 &spr_read_ureg, SPR_NOACCESS,
2827 &spr_read_ureg, SPR_NOACCESS,
2828 0x00000000);
2829
2830 /* Processor identification */
2831 spr_register(env, SPR_BOOKE_PIR, "PIR",
2832 SPR_NOACCESS, SPR_NOACCESS,
2833 &spr_read_generic, &spr_write_pir,
2834 0x00000000);
2835
2836 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2837 &spr_read_spefscr, &spr_write_spefscr,
2838 &spr_read_spefscr, &spr_write_spefscr,
2839 0x00000000);
2840 #if !defined(CONFIG_USER_ONLY)
2841 /* Memory management */
2842 env->nb_pids = 3;
2843 env->nb_ways = 2;
2844 env->id_tlbs = 0;
2845 switch (version) {
2846 case fsl_e500v1:
2847 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
2848 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2849 break;
2850 case fsl_e500v2:
2851 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2852 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2853 break;
2854 case fsl_e500mc:
2855 case fsl_e5500:
2856 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2857 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
2858 break;
2859 case fsl_e6500:
2860 mmucfg = 0x6510B45;
2861 env->nb_pids = 1;
2862 tlbncfg[0] = 0x08052400;
2863 tlbncfg[1] = 0x40028040;
2864 break;
2865 default:
2866 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2867 env->spr[SPR_PVR]);
2868 }
2869 #endif
2870 /* Cache sizes */
2871 switch (version) {
2872 case fsl_e500v1:
2873 case fsl_e500v2:
2874 env->dcache_line_size = 32;
2875 env->icache_line_size = 32;
2876 break;
2877 case fsl_e500mc:
2878 case fsl_e5500:
2879 env->dcache_line_size = 64;
2880 env->icache_line_size = 64;
2881 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
2882 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
2883 break;
2884 case fsl_e6500:
2885 env->dcache_line_size = 32;
2886 env->icache_line_size = 32;
2887 l1cfg0 |= 0x0F83820;
2888 l1cfg1 |= 0x0B83820;
2889 break;
2890 default:
2891 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2892 env->spr[SPR_PVR]);
2893 }
2894 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
2895 register_usprgh_sprs(env);
2896
2897 spr_register(env, SPR_HID0, "HID0",
2898 SPR_NOACCESS, SPR_NOACCESS,
2899 &spr_read_generic, &spr_write_generic,
2900 0x00000000);
2901
2902 spr_register(env, SPR_HID1, "HID1",
2903 SPR_NOACCESS, SPR_NOACCESS,
2904 &spr_read_generic, &spr_write_generic,
2905 0x00000000);
2906
2907 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
2908 SPR_NOACCESS, SPR_NOACCESS,
2909 &spr_read_generic, &spr_write_generic,
2910 0x00000000);
2911
2912 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
2913 SPR_NOACCESS, SPR_NOACCESS,
2914 &spr_read_generic, &spr_write_generic,
2915 0x00000000);
2916
2917 spr_register(env, SPR_Exxx_MCAR, "MCAR",
2918 SPR_NOACCESS, SPR_NOACCESS,
2919 &spr_read_generic, &spr_write_generic,
2920 0x00000000);
2921
2922 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2923 SPR_NOACCESS, SPR_NOACCESS,
2924 &spr_read_generic, &spr_write_generic,
2925 0x00000000);
2926
2927 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
2928 SPR_NOACCESS, SPR_NOACCESS,
2929 &spr_read_generic, &spr_write_generic,
2930 0x00000000);
2931
2932 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2933 SPR_NOACCESS, SPR_NOACCESS,
2934 &spr_read_generic, &spr_write_generic,
2935 0x00000000);
2936
2937 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2938 &spr_read_generic, SPR_NOACCESS,
2939 &spr_read_generic, SPR_NOACCESS,
2940 l1cfg0);
2941 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
2942 &spr_read_generic, SPR_NOACCESS,
2943 &spr_read_generic, SPR_NOACCESS,
2944 l1cfg1);
2945 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2946 SPR_NOACCESS, SPR_NOACCESS,
2947 &spr_read_generic, &spr_write_e500_l1csr0,
2948 0x00000000);
2949 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
2950 SPR_NOACCESS, SPR_NOACCESS,
2951 &spr_read_generic, &spr_write_e500_l1csr1,
2952 0x00000000);
2953 if (version != fsl_e500v1 && version != fsl_e500v2) {
2954 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
2955 SPR_NOACCESS, SPR_NOACCESS,
2956 &spr_read_generic, &spr_write_e500_l2csr0,
2957 0x00000000);
2958 }
2959 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2960 SPR_NOACCESS, SPR_NOACCESS,
2961 &spr_read_generic, &spr_write_generic,
2962 0x00000000);
2963 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2964 SPR_NOACCESS, SPR_NOACCESS,
2965 &spr_read_generic, &spr_write_generic,
2966 0x00000000);
2967 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2968 SPR_NOACCESS, SPR_NOACCESS,
2969 &spr_read_generic, &spr_write_booke206_mmucsr0,
2970 0x00000000);
2971 spr_register(env, SPR_BOOKE_EPR, "EPR",
2972 SPR_NOACCESS, SPR_NOACCESS,
2973 &spr_read_generic, SPR_NOACCESS,
2974 0x00000000);
2975 /* XXX better abstract into Emb.xxx features */
2976 if ((version == fsl_e5500) || (version == fsl_e6500)) {
2977 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
2978 SPR_NOACCESS, SPR_NOACCESS,
2979 &spr_read_generic, &spr_write_generic,
2980 0x00000000);
2981 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
2982 SPR_NOACCESS, SPR_NOACCESS,
2983 &spr_read_mas73, &spr_write_mas73,
2984 0x00000000);
2985 ivpr_mask = (target_ulong)~0xFFFFULL;
2986 }
2987
2988 if (version == fsl_e6500) {
2989 /* Thread identification */
2990 spr_register(env, SPR_TIR, "TIR",
2991 SPR_NOACCESS, SPR_NOACCESS,
2992 &spr_read_generic, SPR_NOACCESS,
2993 0x00000000);
2994 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
2995 SPR_NOACCESS, SPR_NOACCESS,
2996 &spr_read_generic, SPR_NOACCESS,
2997 0x00000004);
2998 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
2999 SPR_NOACCESS, SPR_NOACCESS,
3000 &spr_read_generic, SPR_NOACCESS,
3001 0x7FFFFFFC);
3002 }
3003
3004 #if !defined(CONFIG_USER_ONLY)
3005 env->nb_tlb = 0;
3006 env->tlb_type = TLB_MAS;
3007 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3008 env->nb_tlb += booke206_tlb_size(env, i);
3009 }
3010 #endif
3011
3012 init_excp_e200(env, ivpr_mask);
3013 /* Allocate hardware IRQ controller */
3014 ppce500_irq_init(env_archcpu(env));
3015 }
3016
3017 static void init_proc_e500v1(CPUPPCState *env)
3018 {
3019 init_proc_e500(env, fsl_e500v1);
3020 }
3021
3022 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3023 {
3024 DeviceClass *dc = DEVICE_CLASS(oc);
3025 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3026
3027 dc->desc = "e500v1 core";
3028 pcc->init_proc = init_proc_e500v1;
3029 pcc->check_pow = check_pow_hid0;
3030 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3031 PPC_SPE | PPC_SPE_SINGLE |
3032 PPC_WRTEE | PPC_RFDI |
3033 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3034 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3035 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3036 pcc->insns_flags2 = PPC2_BOOKE206;
3037 pcc->msr_mask = (1ull << MSR_UCLE) |
3038 (1ull << MSR_SPE) |
3039 (1ull << MSR_POW) |
3040 (1ull << MSR_CE) |
3041 (1ull << MSR_EE) |
3042 (1ull << MSR_PR) |
3043 (1ull << MSR_FP) |
3044 (1ull << MSR_ME) |
3045 (1ull << MSR_FE0) |
3046 (1ull << MSR_DWE) |
3047 (1ull << MSR_DE) |
3048 (1ull << MSR_FE1) |
3049 (1ull << MSR_IR) |
3050 (1ull << MSR_DR);
3051 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3052 pcc->excp_model = POWERPC_EXCP_BOOKE;
3053 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3054 pcc->bfd_mach = bfd_mach_ppc_860;
3055 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3056 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3057 POWERPC_FLAG_BUS_CLK;
3058 }
3059
3060 static void init_proc_e500v2(CPUPPCState *env)
3061 {
3062 init_proc_e500(env, fsl_e500v2);
3063 }
3064
3065 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3066 {
3067 DeviceClass *dc = DEVICE_CLASS(oc);
3068 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3069
3070 dc->desc = "e500v2 core";
3071 pcc->init_proc = init_proc_e500v2;
3072 pcc->check_pow = check_pow_hid0;
3073 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3074 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3075 PPC_WRTEE | PPC_RFDI |
3076 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3077 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3078 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3079 pcc->insns_flags2 = PPC2_BOOKE206;
3080 pcc->msr_mask = (1ull << MSR_UCLE) |
3081 (1ull << MSR_SPE) |
3082 (1ull << MSR_POW) |
3083 (1ull << MSR_CE) |
3084 (1ull << MSR_EE) |
3085 (1ull << MSR_PR) |
3086 (1ull << MSR_FP) |
3087 (1ull << MSR_ME) |
3088 (1ull << MSR_FE0) |
3089 (1ull << MSR_DWE) |
3090 (1ull << MSR_DE) |
3091 (1ull << MSR_FE1) |
3092 (1ull << MSR_IR) |
3093 (1ull << MSR_DR);
3094 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3095 pcc->excp_model = POWERPC_EXCP_BOOKE;
3096 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3097 pcc->bfd_mach = bfd_mach_ppc_860;
3098 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3099 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3100 POWERPC_FLAG_BUS_CLK;
3101 }
3102
3103 static void init_proc_e500mc(CPUPPCState *env)
3104 {
3105 init_proc_e500(env, fsl_e500mc);
3106 }
3107
3108 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3109 {
3110 DeviceClass *dc = DEVICE_CLASS(oc);
3111 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3112
3113 dc->desc = "e500mc core";
3114 pcc->init_proc = init_proc_e500mc;
3115 pcc->check_pow = check_pow_none;
3116 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3117 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3118 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3119 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3120 PPC_FLOAT | PPC_FLOAT_FRES |
3121 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3122 PPC_FLOAT_STFIWX | PPC_WAIT |
3123 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3124 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3125 pcc->msr_mask = (1ull << MSR_GS) |
3126 (1ull << MSR_UCLE) |
3127 (1ull << MSR_CE) |
3128 (1ull << MSR_EE) |
3129 (1ull << MSR_PR) |
3130 (1ull << MSR_FP) |
3131 (1ull << MSR_ME) |
3132 (1ull << MSR_FE0) |
3133 (1ull << MSR_DE) |
3134 (1ull << MSR_FE1) |
3135 (1ull << MSR_IR) |
3136 (1ull << MSR_DR) |
3137 (1ull << MSR_PX) |
3138 (1ull << MSR_RI);
3139 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3140 pcc->excp_model = POWERPC_EXCP_BOOKE;
3141 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3142 /* FIXME: figure out the correct flag for e500mc */
3143 pcc->bfd_mach = bfd_mach_ppc_e500;
3144 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3145 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3146 }
3147
3148 #ifdef TARGET_PPC64
3149 static void init_proc_e5500(CPUPPCState *env)
3150 {
3151 init_proc_e500(env, fsl_e5500);
3152 }
3153
3154 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3155 {
3156 DeviceClass *dc = DEVICE_CLASS(oc);
3157 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3158
3159 dc->desc = "e5500 core";
3160 pcc->init_proc = init_proc_e5500;
3161 pcc->check_pow = check_pow_none;
3162 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3163 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3164 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3165 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3166 PPC_FLOAT | PPC_FLOAT_FRES |
3167 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3168 PPC_FLOAT_STFIWX | PPC_WAIT |
3169 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3170 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3171 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3172 PPC2_FP_CVT_S64;
3173 pcc->msr_mask = (1ull << MSR_CM) |
3174 (1ull << MSR_GS) |
3175 (1ull << MSR_UCLE) |
3176 (1ull << MSR_CE) |
3177 (1ull << MSR_EE) |
3178 (1ull << MSR_PR) |
3179 (1ull << MSR_FP) |
3180 (1ull << MSR_ME) |
3181 (1ull << MSR_FE0) |
3182 (1ull << MSR_DE) |
3183 (1ull << MSR_FE1) |
3184 (1ull << MSR_IR) |
3185 (1ull << MSR_DR) |
3186 (1ull << MSR_PX) |
3187 (1ull << MSR_RI);
3188 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3189 pcc->excp_model = POWERPC_EXCP_BOOKE;
3190 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3191 /* FIXME: figure out the correct flag for e5500 */
3192 pcc->bfd_mach = bfd_mach_ppc_e500;
3193 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3194 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3195 }
3196
3197 static void init_proc_e6500(CPUPPCState *env)
3198 {
3199 init_proc_e500(env, fsl_e6500);
3200 }
3201
3202 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3203 {
3204 DeviceClass *dc = DEVICE_CLASS(oc);
3205 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3206
3207 dc->desc = "e6500 core";
3208 pcc->init_proc = init_proc_e6500;
3209 pcc->check_pow = check_pow_none;
3210 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3211 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3212 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3213 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3214 PPC_FLOAT | PPC_FLOAT_FRES |
3215 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3216 PPC_FLOAT_STFIWX | PPC_WAIT |
3217 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3218 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3219 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3220 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3221 pcc->msr_mask = (1ull << MSR_CM) |
3222 (1ull << MSR_GS) |
3223 (1ull << MSR_UCLE) |
3224 (1ull << MSR_CE) |
3225 (1ull << MSR_EE) |
3226 (1ull << MSR_PR) |
3227 (1ull << MSR_FP) |
3228 (1ull << MSR_ME) |
3229 (1ull << MSR_FE0) |
3230 (1ull << MSR_DE) |
3231 (1ull << MSR_FE1) |
3232 (1ull << MSR_IS) |
3233 (1ull << MSR_DS) |
3234 (1ull << MSR_PX) |
3235 (1ull << MSR_RI) |
3236 (1ull << MSR_VR);
3237 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3238 pcc->excp_model = POWERPC_EXCP_BOOKE;
3239 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3240 pcc->bfd_mach = bfd_mach_ppc_e500;
3241 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3242 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3243 }
3244
3245 #endif
3246
3247 /* Non-embedded PowerPC */
3248 static void init_proc_603(CPUPPCState *env)
3249 {
3250 register_non_embedded_sprs(env);
3251 register_sdr1_sprs(env);
3252 register_603_sprs(env);
3253
3254 /* Memory management */
3255 register_low_BATs(env);
3256 register_6xx_7xx_soft_tlb(env, 64, 2);
3257 init_excp_603(env);
3258 env->dcache_line_size = 32;
3259 env->icache_line_size = 32;
3260 /* Allocate hardware IRQ controller */
3261 ppc6xx_irq_init(env_archcpu(env));
3262 }
3263
3264 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3265 {
3266 DeviceClass *dc = DEVICE_CLASS(oc);
3267 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3268
3269 dc->desc = "PowerPC 603";
3270 pcc->init_proc = init_proc_603;
3271 pcc->check_pow = check_pow_hid0;
3272 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3273 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3274 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3275 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3276 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3277 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3278 PPC_SEGMENT | PPC_EXTERN;
3279 pcc->msr_mask = (1ull << MSR_POW) |
3280 (1ull << MSR_TGPR) |
3281 (1ull << MSR_ILE) |
3282 (1ull << MSR_EE) |
3283 (1ull << MSR_PR) |
3284 (1ull << MSR_FP) |
3285 (1ull << MSR_ME) |
3286 (1ull << MSR_FE0) |
3287 (1ull << MSR_SE) |
3288 (1ull << MSR_DE) |
3289 (1ull << MSR_FE1) |
3290 (1ull << MSR_EP) |
3291 (1ull << MSR_IR) |
3292 (1ull << MSR_DR) |
3293 (1ull << MSR_RI) |
3294 (1ull << MSR_LE);
3295 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3296 pcc->excp_model = POWERPC_EXCP_6xx;
3297 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3298 pcc->bfd_mach = bfd_mach_ppc_603;
3299 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3300 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3301 }
3302
3303 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3304 {
3305 DeviceClass *dc = DEVICE_CLASS(oc);
3306 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3307
3308 dc->desc = "PowerPC 603e";
3309 pcc->init_proc = init_proc_603;
3310 pcc->check_pow = check_pow_hid0;
3311 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3312 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3313 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3314 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3315 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3316 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3317 PPC_SEGMENT | PPC_EXTERN;
3318 pcc->msr_mask = (1ull << MSR_POW) |
3319 (1ull << MSR_TGPR) |
3320 (1ull << MSR_ILE) |
3321 (1ull << MSR_EE) |
3322 (1ull << MSR_PR) |
3323 (1ull << MSR_FP) |
3324 (1ull << MSR_ME) |
3325 (1ull << MSR_FE0) |
3326 (1ull << MSR_SE) |
3327 (1ull << MSR_DE) |
3328 (1ull << MSR_FE1) |
3329 (1ull << MSR_EP) |
3330 (1ull << MSR_IR) |
3331 (1ull << MSR_DR) |
3332 (1ull << MSR_RI) |
3333 (1ull << MSR_LE);
3334 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3335 pcc->excp_model = POWERPC_EXCP_6xx;
3336 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3337 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3338 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3339 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3340 }
3341
3342 static void init_proc_e300(CPUPPCState *env)
3343 {
3344 init_proc_603(env);
3345 register_e300_sprs(env);
3346 }
3347
3348 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3349 {
3350 DeviceClass *dc = DEVICE_CLASS(oc);
3351 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3352
3353 dc->desc = "e300 core";
3354 pcc->init_proc = init_proc_e300;
3355 pcc->check_pow = check_pow_hid0;
3356 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3357 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3358 PPC_FLOAT_STFIWX |
3359 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3360 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3361 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3362 PPC_SEGMENT | PPC_EXTERN;
3363 pcc->msr_mask = (1ull << MSR_POW) |
3364 (1ull << MSR_TGPR) |
3365 (1ull << MSR_ILE) |
3366 (1ull << MSR_EE) |
3367 (1ull << MSR_PR) |
3368 (1ull << MSR_FP) |
3369 (1ull << MSR_ME) |
3370 (1ull << MSR_FE0) |
3371 (1ull << MSR_SE) |
3372 (1ull << MSR_DE) |
3373 (1ull << MSR_FE1) |
3374 (1ull << MSR_AL) |
3375 (1ull << MSR_EP) |
3376 (1ull << MSR_IR) |
3377 (1ull << MSR_DR) |
3378 (1ull << MSR_RI) |
3379 (1ull << MSR_LE);
3380 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3381 pcc->excp_model = POWERPC_EXCP_6xx;
3382 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3383 pcc->bfd_mach = bfd_mach_ppc_603;
3384 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3385 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3386 }
3387
3388 static void init_proc_604(CPUPPCState *env)
3389 {
3390 register_non_embedded_sprs(env);
3391 register_sdr1_sprs(env);
3392 register_604_sprs(env);
3393
3394 /* Memory management */
3395 register_low_BATs(env);
3396 init_excp_604(env);
3397 env->dcache_line_size = 32;
3398 env->icache_line_size = 32;
3399 /* Allocate hardware IRQ controller */
3400 ppc6xx_irq_init(env_archcpu(env));
3401 }
3402
3403 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3404 {
3405 DeviceClass *dc = DEVICE_CLASS(oc);
3406 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3407
3408 dc->desc = "PowerPC 604";
3409 pcc->init_proc = init_proc_604;
3410 pcc->check_pow = check_pow_nocheck;
3411 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3412 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3413 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3414 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3415 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3416 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3417 PPC_SEGMENT | PPC_EXTERN;
3418 pcc->msr_mask = (1ull << MSR_POW) |
3419 (1ull << MSR_ILE) |
3420 (1ull << MSR_EE) |
3421 (1ull << MSR_PR) |
3422 (1ull << MSR_FP) |
3423 (1ull << MSR_ME) |
3424 (1ull << MSR_FE0) |
3425 (1ull << MSR_SE) |
3426 (1ull << MSR_DE) |
3427 (1ull << MSR_FE1) |
3428 (1ull << MSR_EP) |
3429 (1ull << MSR_IR) |
3430 (1ull << MSR_DR) |
3431 (1ull << MSR_PMM) |
3432 (1ull << MSR_RI) |
3433 (1ull << MSR_LE);
3434 pcc->mmu_model = POWERPC_MMU_32B;
3435 pcc->excp_model = POWERPC_EXCP_6xx;
3436 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3437 pcc->bfd_mach = bfd_mach_ppc_604;
3438 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3439 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3440 }
3441
3442 static void init_proc_604E(CPUPPCState *env)
3443 {
3444 init_proc_604(env);
3445 register_604e_sprs(env);
3446 }
3447
3448 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3449 {
3450 DeviceClass *dc = DEVICE_CLASS(oc);
3451 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3452
3453 dc->desc = "PowerPC 604E";
3454 pcc->init_proc = init_proc_604E;
3455 pcc->check_pow = check_pow_nocheck;
3456 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3457 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3458 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3459 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3460 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3461 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3462 PPC_SEGMENT | PPC_EXTERN;
3463 pcc->msr_mask = (1ull << MSR_POW) |
3464 (1ull << MSR_ILE) |
3465 (1ull << MSR_EE) |
3466 (1ull << MSR_PR) |
3467 (1ull << MSR_FP) |
3468 (1ull << MSR_ME) |
3469 (1ull << MSR_FE0) |
3470 (1ull << MSR_SE) |
3471 (1ull << MSR_DE) |
3472 (1ull << MSR_FE1) |
3473 (1ull << MSR_EP) |
3474 (1ull << MSR_IR) |
3475 (1ull << MSR_DR) |
3476 (1ull << MSR_PMM) |
3477 (1ull << MSR_RI) |
3478 (1ull << MSR_LE);
3479 pcc->mmu_model = POWERPC_MMU_32B;
3480 pcc->excp_model = POWERPC_EXCP_6xx;
3481 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3482 pcc->bfd_mach = bfd_mach_ppc_604;
3483 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3484 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3485 }
3486
3487 static void init_proc_740(CPUPPCState *env)
3488 {
3489 register_non_embedded_sprs(env);
3490 register_sdr1_sprs(env);
3491 register_7xx_sprs(env);
3492 /* Thermal management */
3493 register_thrm_sprs(env);
3494
3495 /* Memory management */
3496 register_low_BATs(env);
3497 init_excp_7x0(env);
3498 env->dcache_line_size = 32;
3499 env->icache_line_size = 32;
3500 /* Allocate hardware IRQ controller */
3501 ppc6xx_irq_init(env_archcpu(env));
3502 }
3503
3504 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
3505 {
3506 DeviceClass *dc = DEVICE_CLASS(oc);
3507 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3508
3509 dc->desc = "PowerPC 740";
3510 pcc->init_proc = init_proc_740;
3511 pcc->check_pow = check_pow_hid0;
3512 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3513 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3514 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3515 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3516 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3517 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3518 PPC_SEGMENT | PPC_EXTERN;
3519 pcc->msr_mask = (1ull << MSR_POW) |
3520 (1ull << MSR_ILE) |
3521 (1ull << MSR_EE) |
3522 (1ull << MSR_PR) |
3523 (1ull << MSR_FP) |
3524 (1ull << MSR_ME) |
3525 (1ull << MSR_FE0) |
3526 (1ull << MSR_SE) |
3527 (1ull << MSR_DE) |
3528 (1ull << MSR_FE1) |
3529 (1ull << MSR_EP) |
3530 (1ull << MSR_IR) |
3531 (1ull << MSR_DR) |
3532 (1ull << MSR_PMM) |
3533 (1ull << MSR_RI) |
3534 (1ull << MSR_LE);
3535 pcc->mmu_model = POWERPC_MMU_32B;
3536 pcc->excp_model = POWERPC_EXCP_7xx;
3537 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3538 pcc->bfd_mach = bfd_mach_ppc_750;
3539 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3540 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3541 }
3542
3543 static void init_proc_750(CPUPPCState *env)
3544 {
3545 register_non_embedded_sprs(env);
3546 register_sdr1_sprs(env);
3547 register_7xx_sprs(env);
3548
3549 spr_register(env, SPR_L2CR, "L2CR",
3550 SPR_NOACCESS, SPR_NOACCESS,
3551 &spr_read_generic, spr_access_nop,
3552 0x00000000);
3553 /* Thermal management */
3554 register_thrm_sprs(env);
3555
3556 /* Memory management */
3557 register_low_BATs(env);
3558 /*
3559 * XXX: high BATs are also present but are known to be bugged on
3560 * die version 1.x
3561 */
3562 init_excp_7x0(env);
3563 env->dcache_line_size = 32;
3564 env->icache_line_size = 32;
3565 /* Allocate hardware IRQ controller */
3566 ppc6xx_irq_init(env_archcpu(env));
3567 }
3568
3569 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
3570 {
3571 DeviceClass *dc = DEVICE_CLASS(oc);
3572 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3573
3574 dc->desc = "PowerPC 750";
3575 pcc->init_proc = init_proc_750;
3576 pcc->check_pow = check_pow_hid0;
3577 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3578 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3579 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3580 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3581 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3582 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3583 PPC_SEGMENT | PPC_EXTERN;
3584 pcc->msr_mask = (1ull << MSR_POW) |
3585 (1ull << MSR_ILE) |
3586 (1ull << MSR_EE) |
3587 (1ull << MSR_PR) |
3588 (1ull << MSR_FP) |
3589 (1ull << MSR_ME) |
3590 (1ull << MSR_FE0) |
3591 (1ull << MSR_SE) |
3592 (1ull << MSR_DE) |
3593 (1ull << MSR_FE1) |
3594 (1ull << MSR_EP) |
3595 (1ull << MSR_IR) |
3596 (1ull << MSR_DR) |
3597 (1ull << MSR_PMM) |
3598 (1ull << MSR_RI) |
3599 (1ull << MSR_LE);
3600 pcc->mmu_model = POWERPC_MMU_32B;
3601 pcc->excp_model = POWERPC_EXCP_7xx;
3602 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3603 pcc->bfd_mach = bfd_mach_ppc_750;
3604 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3605 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3606 }
3607
3608 static void init_proc_750cl(CPUPPCState *env)
3609 {
3610 register_non_embedded_sprs(env);
3611 register_sdr1_sprs(env);
3612 register_7xx_sprs(env);
3613
3614 spr_register(env, SPR_L2CR, "L2CR",
3615 SPR_NOACCESS, SPR_NOACCESS,
3616 &spr_read_generic, spr_access_nop,
3617 0x00000000);
3618 /* Thermal management */
3619 /* Those registers are fake on 750CL */
3620 spr_register(env, SPR_THRM1, "THRM1",
3621 SPR_NOACCESS, SPR_NOACCESS,
3622 &spr_read_generic, &spr_write_generic,
3623 0x00000000);
3624 spr_register(env, SPR_THRM2, "THRM2",
3625 SPR_NOACCESS, SPR_NOACCESS,
3626 &spr_read_generic, &spr_write_generic,
3627 0x00000000);
3628 spr_register(env, SPR_THRM3, "THRM3",
3629 SPR_NOACCESS, SPR_NOACCESS,
3630 &spr_read_generic, &spr_write_generic,
3631 0x00000000);
3632
3633 spr_register(env, SPR_750_TDCL, "TDCL",
3634 SPR_NOACCESS, SPR_NOACCESS,
3635 &spr_read_generic, &spr_write_generic,
3636 0x00000000);
3637 spr_register(env, SPR_750_TDCH, "TDCH",
3638 SPR_NOACCESS, SPR_NOACCESS,
3639 &spr_read_generic, &spr_write_generic,
3640 0x00000000);
3641 /* DMA */
3642 spr_register(env, SPR_750_WPAR, "WPAR",
3643 SPR_NOACCESS, SPR_NOACCESS,
3644 &spr_read_generic, &spr_write_generic,
3645 0x00000000);
3646 spr_register(env, SPR_750_DMAL, "DMAL",
3647 SPR_NOACCESS, SPR_NOACCESS,
3648 &spr_read_generic, &spr_write_generic,
3649 0x00000000);
3650 spr_register(env, SPR_750_DMAU, "DMAU",
3651 SPR_NOACCESS, SPR_NOACCESS,
3652 &spr_read_generic, &spr_write_generic,
3653 0x00000000);
3654 /* Hardware implementation registers */
3655 spr_register(env, SPR_750CL_HID2, "HID2",
3656 SPR_NOACCESS, SPR_NOACCESS,
3657 &spr_read_generic, &spr_write_generic,
3658 0x00000000);
3659
3660 spr_register(env, SPR_750CL_HID4, "HID4",
3661 SPR_NOACCESS, SPR_NOACCESS,
3662 &spr_read_generic, &spr_write_generic,
3663 0x00000000);
3664 /* Quantization registers */
3665 spr_register(env, SPR_750_GQR0, "GQR0",
3666 SPR_NOACCESS, SPR_NOACCESS,
3667 &spr_read_generic, &spr_write_generic,
3668 0x00000000);
3669
3670 spr_register(env, SPR_750_GQR1, "GQR1",
3671 SPR_NOACCESS, SPR_NOACCESS,
3672 &spr_read_generic, &spr_write_generic,
3673 0x00000000);
3674
3675 spr_register(env, SPR_750_GQR2, "GQR2",
3676 SPR_NOACCESS, SPR_NOACCESS,
3677 &spr_read_generic, &spr_write_generic,
3678 0x00000000);
3679
3680 spr_register(env, SPR_750_GQR3, "GQR3",
3681 SPR_NOACCESS, SPR_NOACCESS,
3682 &spr_read_generic, &spr_write_generic,
3683 0x00000000);
3684
3685 spr_register(env, SPR_750_GQR4, "GQR4",
3686 SPR_NOACCESS, SPR_NOACCESS,
3687 &spr_read_generic, &spr_write_generic,
3688 0x00000000);
3689
3690 spr_register(env, SPR_750_GQR5, "GQR5",
3691 SPR_NOACCESS, SPR_NOACCESS,
3692 &spr_read_generic, &spr_write_generic,
3693 0x00000000);
3694
3695 spr_register(env, SPR_750_GQR6, "GQR6",
3696 SPR_NOACCESS, SPR_NOACCESS,
3697 &spr_read_generic, &spr_write_generic,
3698 0x00000000);
3699
3700 spr_register(env, SPR_750_GQR7, "GQR7",
3701 SPR_NOACCESS, SPR_NOACCESS,
3702 &spr_read_generic, &spr_write_generic,
3703 0x00000000);
3704 /* Memory management */
3705 register_low_BATs(env);
3706 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
3707 register_high_BATs(env);
3708 init_excp_750cl(env);
3709 env->dcache_line_size = 32;
3710 env->icache_line_size = 32;
3711 /* Allocate hardware IRQ controller */
3712 ppc6xx_irq_init(env_archcpu(env));
3713 }
3714
3715 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
3716 {
3717 DeviceClass *dc = DEVICE_CLASS(oc);
3718 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3719
3720 dc->desc = "PowerPC 750 CL";
3721 pcc->init_proc = init_proc_750cl;
3722 pcc->check_pow = check_pow_hid0;
3723 /*
3724 * XXX: not implemented:
3725 * cache lock instructions:
3726 * dcbz_l
3727 * floating point paired instructions
3728 * psq_lux
3729 * psq_lx
3730 * psq_stux
3731 * psq_stx
3732 * ps_abs
3733 * ps_add
3734 * ps_cmpo0
3735 * ps_cmpo1
3736 * ps_cmpu0
3737 * ps_cmpu1
3738 * ps_div
3739 * ps_madd
3740 * ps_madds0
3741 * ps_madds1
3742 * ps_merge00
3743 * ps_merge01
3744 * ps_merge10
3745 * ps_merge11
3746 * ps_mr
3747 * ps_msub
3748 * ps_mul
3749 * ps_muls0
3750 * ps_muls1
3751 * ps_nabs
3752 * ps_neg
3753 * ps_nmadd
3754 * ps_nmsub
3755 * ps_res
3756 * ps_rsqrte
3757 * ps_sel
3758 * ps_sub
3759 * ps_sum0
3760 * ps_sum1
3761 */
3762 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3763 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3764 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3765 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3766 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3767 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3768 PPC_SEGMENT | PPC_EXTERN;
3769 pcc->msr_mask = (1ull << MSR_POW) |
3770 (1ull << MSR_ILE) |
3771 (1ull << MSR_EE) |
3772 (1ull << MSR_PR) |
3773 (1ull << MSR_FP) |
3774 (1ull << MSR_ME) |
3775 (1ull << MSR_FE0) |
3776 (1ull << MSR_SE) |
3777 (1ull << MSR_DE) |
3778 (1ull << MSR_FE1) |
3779 (1ull << MSR_EP) |
3780 (1ull << MSR_IR) |
3781 (1ull << MSR_DR) |
3782 (1ull << MSR_PMM) |
3783 (1ull << MSR_RI) |
3784 (1ull << MSR_LE);
3785 pcc->mmu_model = POWERPC_MMU_32B;
3786 pcc->excp_model = POWERPC_EXCP_7xx;
3787 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3788 pcc->bfd_mach = bfd_mach_ppc_750;
3789 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3790 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3791 }
3792
3793 static void init_proc_750cx(CPUPPCState *env)
3794 {
3795 register_non_embedded_sprs(env);
3796 register_sdr1_sprs(env);
3797 register_7xx_sprs(env);
3798
3799 spr_register(env, SPR_L2CR, "L2CR",
3800 SPR_NOACCESS, SPR_NOACCESS,
3801 &spr_read_generic, spr_access_nop,
3802 0x00000000);
3803 /* Thermal management */
3804 register_thrm_sprs(env);
3805
3806 spr_register(env, SPR_SDA, "SDA",
3807 SPR_NOACCESS, SPR_NOACCESS,
3808 &spr_read_generic, &spr_write_generic,
3809 0x00000000);
3810
3811 /* Memory management */
3812 register_low_BATs(env);
3813 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
3814 register_high_BATs(env);
3815 init_excp_750cx(env);
3816 env->dcache_line_size = 32;
3817 env->icache_line_size = 32;
3818 /* Allocate hardware IRQ controller */
3819 ppc6xx_irq_init(env_archcpu(env));
3820 }
3821
3822 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
3823 {
3824 DeviceClass *dc = DEVICE_CLASS(oc);
3825 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3826
3827 dc->desc = "PowerPC 750CX";
3828 pcc->init_proc = init_proc_750cx;
3829 pcc->check_pow = check_pow_hid0;
3830 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3831 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3832 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3833 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3834 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3835 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3836 PPC_SEGMENT | PPC_EXTERN;
3837 pcc->msr_mask = (1ull << MSR_POW) |
3838 (1ull << MSR_ILE) |
3839 (1ull << MSR_EE) |
3840 (1ull << MSR_PR) |
3841 (1ull << MSR_FP) |
3842 (1ull << MSR_ME) |
3843 (1ull << MSR_FE0) |
3844 (1ull << MSR_SE) |
3845 (1ull << MSR_DE) |
3846 (1ull << MSR_FE1) |
3847 (1ull << MSR_EP) |
3848 (1ull << MSR_IR) |
3849 (1ull << MSR_DR) |
3850 (1ull << MSR_PMM) |
3851 (1ull << MSR_RI) |
3852 (1ull << MSR_LE);
3853 pcc->mmu_model = POWERPC_MMU_32B;
3854 pcc->excp_model = POWERPC_EXCP_7xx;
3855 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3856 pcc->bfd_mach = bfd_mach_ppc_750;
3857 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3858 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3859 }
3860
3861 static void init_proc_750fx(CPUPPCState *env)
3862 {
3863 register_non_embedded_sprs(env);
3864 register_sdr1_sprs(env);
3865 register_7xx_sprs(env);
3866
3867 spr_register(env, SPR_L2CR, "L2CR",
3868 SPR_NOACCESS, SPR_NOACCESS,
3869 &spr_read_generic, spr_access_nop,
3870 0x00000000);
3871 /* Thermal management */
3872 register_thrm_sprs(env);
3873
3874 spr_register(env, SPR_750_THRM4, "THRM4",
3875 SPR_NOACCESS, SPR_NOACCESS,
3876 &spr_read_generic, &spr_write_generic,
3877 0x00000000);
3878 /* Hardware implementation registers */
3879 spr_register(env, SPR_750FX_HID2, "HID2",
3880 SPR_NOACCESS, SPR_NOACCESS,
3881 &spr_read_generic, &spr_write_generic,
3882 0x00000000);
3883 /* Memory management */
3884 register_low_BATs(env);
3885 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3886 register_high_BATs(env);
3887 init_excp_7x0(env);
3888 env->dcache_line_size = 32;
3889 env->icache_line_size = 32;
3890 /* Allocate hardware IRQ controller */
3891 ppc6xx_irq_init(env_archcpu(env));
3892 }
3893
3894 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
3895 {
3896 DeviceClass *dc = DEVICE_CLASS(oc);
3897 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3898
3899 dc->desc = "PowerPC 750FX";
3900 pcc->init_proc = init_proc_750fx;
3901 pcc->check_pow = check_pow_hid0;
3902 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3903 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3904 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3905 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3906 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3907 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3908 PPC_SEGMENT | PPC_EXTERN;
3909 pcc->msr_mask = (1ull << MSR_POW) |
3910 (1ull << MSR_ILE) |
3911 (1ull << MSR_EE) |
3912 (1ull << MSR_PR) |
3913 (1ull << MSR_FP) |
3914 (1ull << MSR_ME) |
3915 (1ull << MSR_FE0) |
3916 (1ull << MSR_SE) |
3917 (1ull << MSR_DE) |
3918 (1ull << MSR_FE1) |
3919 (1ull << MSR_EP) |
3920 (1ull << MSR_IR) |
3921 (1ull << MSR_DR) |
3922 (1ull << MSR_PMM) |
3923 (1ull << MSR_RI) |
3924 (1ull << MSR_LE);
3925 pcc->mmu_model = POWERPC_MMU_32B;
3926 pcc->excp_model = POWERPC_EXCP_7xx;
3927 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3928 pcc->bfd_mach = bfd_mach_ppc_750;
3929 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3930 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3931 }
3932
3933 static void init_proc_750gx(CPUPPCState *env)
3934 {
3935 register_non_embedded_sprs(env);
3936 register_sdr1_sprs(env);
3937 register_7xx_sprs(env);
3938
3939 spr_register(env, SPR_L2CR, "L2CR",
3940 SPR_NOACCESS, SPR_NOACCESS,
3941 &spr_read_generic, spr_access_nop,
3942 0x00000000);
3943 /* Thermal management */
3944 register_thrm_sprs(env);
3945
3946 spr_register(env, SPR_750_THRM4, "THRM4",
3947 SPR_NOACCESS, SPR_NOACCESS,
3948 &spr_read_generic, &spr_write_generic,
3949 0x00000000);
3950 /* Hardware implementation registers */
3951 spr_register(env, SPR_750FX_HID2, "HID2",
3952 SPR_NOACCESS, SPR_NOACCESS,
3953 &spr_read_generic, &spr_write_generic,
3954 0x00000000);
3955 /* Memory management */
3956 register_low_BATs(env);
3957 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3958 register_high_BATs(env);
3959 init_excp_7x0(env);
3960 env->dcache_line_size = 32;
3961 env->icache_line_size = 32;
3962 /* Allocate hardware IRQ controller */
3963 ppc6xx_irq_init(env_archcpu(env));
3964 }
3965
3966 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
3967 {
3968 DeviceClass *dc = DEVICE_CLASS(oc);
3969 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3970
3971 dc->desc = "PowerPC 750GX";
3972 pcc->init_proc = init_proc_750gx;
3973 pcc->check_pow = check_pow_hid0;
3974 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3975 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3976 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3977 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3978 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3979 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3980 PPC_SEGMENT | PPC_EXTERN;
3981 pcc->msr_mask = (1ull << MSR_POW) |
3982 (1ull << MSR_ILE) |
3983 (1ull << MSR_EE) |
3984 (1ull << MSR_PR) |
3985 (1ull << MSR_FP) |
3986 (1ull << MSR_ME) |
3987 (1ull << MSR_FE0) |
3988 (1ull << MSR_SE) |
3989 (1ull << MSR_DE) |
3990 (1ull << MSR_FE1) |
3991 (1ull << MSR_EP) |
3992 (1ull << MSR_IR) |
3993 (1ull << MSR_DR) |
3994 (1ull << MSR_PMM) |
3995 (1ull << MSR_RI) |
3996 (1ull << MSR_LE);
3997 pcc->mmu_model = POWERPC_MMU_32B;
3998 pcc->excp_model = POWERPC_EXCP_7xx;
3999 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4000 pcc->bfd_mach = bfd_mach_ppc_750;
4001 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4002 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4003 }
4004
4005 static void init_proc_745(CPUPPCState *env)
4006 {
4007 register_non_embedded_sprs(env);
4008 register_sdr1_sprs(env);
4009 register_7xx_sprs(env);
4010 register_745_sprs(env);
4011 /* Thermal management */
4012 register_thrm_sprs(env);
4013
4014 /* Memory management */
4015 register_low_BATs(env);
4016 register_high_BATs(env);
4017 register_6xx_7xx_soft_tlb(env, 64, 2);
4018 init_excp_7x5(env);
4019 env->dcache_line_size = 32;
4020 env->icache_line_size = 32;
4021 /* Allocate hardware IRQ controller */
4022 ppc6xx_irq_init(env_archcpu(env));
4023 }
4024
4025 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4026 {
4027 DeviceClass *dc = DEVICE_CLASS(oc);
4028 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4029
4030 dc->desc = "PowerPC 745";
4031 pcc->init_proc = init_proc_745;
4032 pcc->check_pow = check_pow_hid0;
4033 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4034 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4035 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4036 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4037 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4038 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4039 PPC_SEGMENT | PPC_EXTERN;
4040 pcc->msr_mask = (1ull << MSR_POW) |
4041 (1ull << MSR_ILE) |
4042 (1ull << MSR_EE) |
4043 (1ull << MSR_PR) |
4044 (1ull << MSR_FP) |
4045 (1ull << MSR_ME) |
4046 (1ull << MSR_FE0) |
4047 (1ull << MSR_SE) |
4048 (1ull << MSR_DE) |
4049 (1ull << MSR_FE1) |
4050 (1ull << MSR_EP) |
4051 (1ull << MSR_IR) |
4052 (1ull << MSR_DR) |
4053 (1ull << MSR_PMM) |
4054 (1ull << MSR_RI) |
4055 (1ull << MSR_LE);
4056 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4057 pcc->excp_model = POWERPC_EXCP_7xx;
4058 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4059 pcc->bfd_mach = bfd_mach_ppc_750;
4060 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4061 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4062 }
4063
4064 static void init_proc_755(CPUPPCState *env)
4065 {
4066 init_proc_745(env);
4067 register_755_sprs(env);
4068 }
4069
4070 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4071 {
4072 DeviceClass *dc = DEVICE_CLASS(oc);
4073 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4074
4075 dc->desc = "PowerPC 755";
4076 pcc->init_proc = init_proc_755;
4077 pcc->check_pow = check_pow_hid0;
4078 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4079 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4080 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4081 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4082 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4083 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4084 PPC_SEGMENT | PPC_EXTERN;
4085 pcc->msr_mask = (1ull << MSR_POW) |
4086 (1ull << MSR_ILE) |
4087 (1ull << MSR_EE) |
4088 (1ull << MSR_PR) |
4089 (1ull << MSR_FP) |
4090 (1ull << MSR_ME) |
4091 (1ull << MSR_FE0) |
4092 (1ull << MSR_SE) |
4093 (1ull << MSR_DE) |
4094 (1ull << MSR_FE1) |
4095 (1ull << MSR_EP) |
4096 (1ull << MSR_IR) |
4097 (1ull << MSR_DR) |
4098 (1ull << MSR_PMM) |
4099 (1ull << MSR_RI) |
4100 (1ull << MSR_LE);
4101 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4102 pcc->excp_model = POWERPC_EXCP_7xx;
4103 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4104 pcc->bfd_mach = bfd_mach_ppc_750;
4105 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4106 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4107 }
4108
4109 static void init_proc_7400(CPUPPCState *env)
4110 {
4111 register_non_embedded_sprs(env);
4112 register_sdr1_sprs(env);
4113 register_74xx_sprs(env);
4114 vscr_init(env, 0x00010000);
4115
4116 spr_register(env, SPR_UBAMR, "UBAMR",
4117 &spr_read_ureg, SPR_NOACCESS,
4118 &spr_read_ureg, SPR_NOACCESS,
4119 0x00000000);
4120
4121 spr_register(env, SPR_MSSCR1, "MSSCR1",
4122 SPR_NOACCESS, SPR_NOACCESS,
4123 &spr_read_generic, &spr_write_generic,
4124 0x00000000);
4125 /* Thermal management */
4126 register_thrm_sprs(env);
4127 /* Memory management */
4128 register_low_BATs(env);
4129 init_excp_7400(env);
4130 env->dcache_line_size = 32;
4131 env->icache_line_size = 32;
4132 /* Allocate hardware IRQ controller */
4133 ppc6xx_irq_init(env_archcpu(env));
4134 }
4135
4136 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4137 {
4138 DeviceClass *dc = DEVICE_CLASS(oc);
4139 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4140
4141 dc->desc = "PowerPC 7400 (aka G4)";
4142 pcc->init_proc = init_proc_7400;
4143 pcc->check_pow = check_pow_hid0;
4144 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4145 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4146 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4147 PPC_FLOAT_STFIWX |
4148 PPC_CACHE | PPC_CACHE_ICBI |
4149 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4150 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4151 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4152 PPC_MEM_TLBIA |
4153 PPC_SEGMENT | PPC_EXTERN |
4154 PPC_ALTIVEC;
4155 pcc->msr_mask = (1ull << MSR_VR) |
4156 (1ull << MSR_POW) |
4157 (1ull << MSR_ILE) |
4158 (1ull << MSR_EE) |
4159 (1ull << MSR_PR) |
4160 (1ull << MSR_FP) |
4161 (1ull << MSR_ME) |
4162 (1ull << MSR_FE0) |
4163 (1ull << MSR_SE) |
4164 (1ull << MSR_DE) |
4165 (1ull << MSR_FE1) |
4166 (1ull << MSR_EP) |
4167 (1ull << MSR_IR) |
4168 (1ull << MSR_DR) |
4169 (1ull << MSR_PMM) |
4170 (1ull << MSR_RI) |
4171 (1ull << MSR_LE);
4172 pcc->mmu_model = POWERPC_MMU_32B;
4173 pcc->excp_model = POWERPC_EXCP_74xx;
4174 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4175 pcc->bfd_mach = bfd_mach_ppc_7400;
4176 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4177 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4178 POWERPC_FLAG_BUS_CLK;
4179 }
4180
4181 static void init_proc_7410(CPUPPCState *env)
4182 {
4183 register_non_embedded_sprs(env);
4184 register_sdr1_sprs(env);
4185 register_74xx_sprs(env);
4186 vscr_init(env, 0x00010000);
4187
4188 spr_register(env, SPR_UBAMR, "UBAMR",
4189 &spr_read_ureg, SPR_NOACCESS,
4190 &spr_read_ureg, SPR_NOACCESS,
4191 0x00000000);
4192 /* Thermal management */
4193 register_thrm_sprs(env);
4194 /* L2PMCR */
4195
4196 spr_register(env, SPR_L2PMCR, "L2PMCR",
4197 SPR_NOACCESS, SPR_NOACCESS,
4198 &spr_read_generic, &spr_write_generic,
4199 0x00000000);
4200 /* LDSTDB */
4201
4202 spr_register(env, SPR_LDSTDB, "LDSTDB",
4203 SPR_NOACCESS, SPR_NOACCESS,
4204 &spr_read_generic, &spr_write_generic,
4205 0x00000000);
4206 /* Memory management */
4207 register_low_BATs(env);
4208 init_excp_7400(env);
4209 env->dcache_line_size = 32;
4210 env->icache_line_size = 32;
4211 /* Allocate hardware IRQ controller */
4212 ppc6xx_irq_init(env_archcpu(env));
4213 }
4214
4215 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4216 {
4217 DeviceClass *dc = DEVICE_CLASS(oc);
4218 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4219
4220 dc->desc = "PowerPC 7410 (aka G4)";
4221 pcc->init_proc = init_proc_7410;
4222 pcc->check_pow = check_pow_hid0;
4223 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4224 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4225 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4226 PPC_FLOAT_STFIWX |
4227 PPC_CACHE | PPC_CACHE_ICBI |
4228 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4229 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4230 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4231 PPC_MEM_TLBIA |
4232 PPC_SEGMENT | PPC_EXTERN |
4233 PPC_ALTIVEC;
4234 pcc->msr_mask = (1ull << MSR_VR) |
4235 (1ull << MSR_POW) |
4236 (1ull << MSR_ILE) |
4237 (1ull << MSR_EE) |
4238 (1ull << MSR_PR) |
4239 (1ull << MSR_FP) |
4240 (1ull << MSR_ME) |
4241 (1ull << MSR_FE0) |
4242 (1ull << MSR_SE) |
4243 (1ull << MSR_DE) |
4244 (1ull << MSR_FE1) |
4245 (1ull << MSR_EP) |
4246 (1ull << MSR_IR) |
4247 (1ull << MSR_DR) |
4248 (1ull << MSR_PMM) |
4249 (1ull << MSR_RI) |
4250 (1ull << MSR_LE);
4251 pcc->mmu_model = POWERPC_MMU_32B;
4252 pcc->excp_model = POWERPC_EXCP_74xx;
4253 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4254 pcc->bfd_mach = bfd_mach_ppc_7400;
4255 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4256 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4257 POWERPC_FLAG_BUS_CLK;
4258 }
4259
4260 static void init_proc_7440(CPUPPCState *env)
4261 {
4262 register_non_embedded_sprs(env);
4263 register_sdr1_sprs(env);
4264 register_74xx_sprs(env);
4265 vscr_init(env, 0x00010000);
4266
4267 spr_register(env, SPR_UBAMR, "UBAMR",
4268 &spr_read_ureg, SPR_NOACCESS,
4269 &spr_read_ureg, SPR_NOACCESS,
4270 0x00000000);
4271 /* LDSTCR */
4272 spr_register(env, SPR_LDSTCR, "LDSTCR",
4273 SPR_NOACCESS, SPR_NOACCESS,
4274 &spr_read_generic, &spr_write_generic,
4275 0x00000000);
4276 /* ICTRL */
4277 spr_register(env, SPR_ICTRL, "ICTRL",
4278 SPR_NOACCESS, SPR_NOACCESS,
4279 &spr_read_generic, &spr_write_generic,
4280 0x00000000);
4281 /* MSSSR0 */
4282 spr_register(env, SPR_MSSSR0, "MSSSR0",
4283 SPR_NOACCESS, SPR_NOACCESS,
4284 &spr_read_generic, &spr_write_generic,
4285 0x00000000);
4286 /* PMC */
4287 spr_register(env, SPR_7XX_PMC5, "PMC5",
4288 SPR_NOACCESS, SPR_NOACCESS,
4289 &spr_read_generic, &spr_write_generic,
4290 0x00000000);
4291
4292 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4293 &spr_read_ureg, SPR_NOACCESS,
4294 &spr_read_ureg, SPR_NOACCESS,
4295 0x00000000);
4296
4297 spr_register(env, SPR_7XX_PMC6, "PMC6",
4298 SPR_NOACCESS, SPR_NOACCESS,
4299 &spr_read_generic, &spr_write_generic,
4300 0x00000000);
4301
4302 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4303 &spr_read_ureg, SPR_NOACCESS,
4304 &spr_read_ureg, SPR_NOACCESS,
4305 0x00000000);
4306 /* Memory management */
4307 register_low_BATs(env);
4308 init_excp_7450(env);
4309 env->dcache_line_size = 32;
4310 env->icache_line_size = 32;
4311 /* Allocate hardware IRQ controller */
4312 ppc6xx_irq_init(env_archcpu(env));
4313 }
4314
4315 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4316 {
4317 DeviceClass *dc = DEVICE_CLASS(oc);
4318 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4319
4320 dc->desc = "PowerPC 7440 (aka G4)";
4321 pcc->init_proc = init_proc_7440;
4322 pcc->check_pow = check_pow_hid0_74xx;
4323 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4324 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4325 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4326 PPC_FLOAT_STFIWX |
4327 PPC_CACHE | PPC_CACHE_ICBI |
4328 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4329 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4330 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4331 PPC_MEM_TLBIA |
4332 PPC_SEGMENT | PPC_EXTERN |
4333 PPC_ALTIVEC;
4334 pcc->msr_mask = (1ull << MSR_VR) |
4335 (1ull << MSR_POW) |
4336 (1ull << MSR_ILE) |
4337 (1ull << MSR_EE) |
4338 (1ull << MSR_PR) |
4339 (1ull << MSR_FP) |
4340 (1ull << MSR_ME) |
4341 (1ull << MSR_FE0) |
4342 (1ull << MSR_SE) |
4343 (1ull << MSR_DE) |
4344 (1ull << MSR_FE1) |
4345 (1ull << MSR_EP) |
4346 (1ull << MSR_IR) |
4347 (1ull << MSR_DR) |
4348 (1ull << MSR_PMM) |
4349 (1ull << MSR_RI) |
4350 (1ull << MSR_LE);
4351 pcc->mmu_model = POWERPC_MMU_32B;
4352 pcc->excp_model = POWERPC_EXCP_74xx;
4353 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4354 pcc->bfd_mach = bfd_mach_ppc_7400;
4355 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4356 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4357 POWERPC_FLAG_BUS_CLK;
4358 }
4359
4360 static void init_proc_7450(CPUPPCState *env)
4361 {
4362 register_non_embedded_sprs(env);
4363 register_sdr1_sprs(env);
4364 register_74xx_sprs(env);
4365 vscr_init(env, 0x00010000);
4366 /* Level 3 cache control */
4367 register_l3_ctrl(env);
4368 /* L3ITCR1 */
4369 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4370 SPR_NOACCESS, SPR_NOACCESS,
4371 &spr_read_generic, &spr_write_generic,
4372 0x00000000);
4373 /* L3ITCR2 */
4374 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4375 SPR_NOACCESS, SPR_NOACCESS,
4376 &spr_read_generic, &spr_write_generic,
4377 0x00000000);
4378 /* L3ITCR3 */
4379 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4380 SPR_NOACCESS, SPR_NOACCESS,
4381 &spr_read_generic, &spr_write_generic,
4382 0x00000000);
4383 /* L3OHCR */
4384 spr_register(env, SPR_L3OHCR, "L3OHCR",
4385 SPR_NOACCESS, SPR_NOACCESS,
4386 &spr_read_generic, &spr_write_generic,
4387 0x00000000);
4388
4389 spr_register(env, SPR_UBAMR, "UBAMR",
4390 &spr_read_ureg, SPR_NOACCESS,
4391 &spr_read_ureg, SPR_NOACCESS,
4392 0x00000000);
4393 /* LDSTCR */
4394 spr_register(env, SPR_LDSTCR, "LDSTCR",
4395 SPR_NOACCESS, SPR_NOACCESS,
4396 &spr_read_generic, &spr_write_generic,
4397 0x00000000);
4398 /* ICTRL */
4399 spr_register(env, SPR_ICTRL, "ICTRL",
4400 SPR_NOACCESS, SPR_NOACCESS,
4401 &spr_read_generic, &spr_write_generic,
4402 0x00000000);
4403 /* MSSSR0 */
4404 spr_register(env, SPR_MSSSR0, "MSSSR0",
4405 SPR_NOACCESS, SPR_NOACCESS,
4406 &spr_read_generic, &spr_write_generic,
4407 0x00000000);
4408 /* PMC */
4409 spr_register(env, SPR_7XX_PMC5, "PMC5",
4410 SPR_NOACCESS, SPR_NOACCESS,
4411 &spr_read_generic, &spr_write_generic,
4412 0x00000000);
4413
4414 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4415 &spr_read_ureg, SPR_NOACCESS,
4416 &spr_read_ureg, SPR_NOACCESS,
4417 0x00000000);
4418
4419 spr_register(env, SPR_7XX_PMC6, "PMC6",
4420 SPR_NOACCESS, SPR_NOACCESS,
4421 &spr_read_generic, &spr_write_generic,
4422 0x00000000);
4423
4424 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4425 &spr_read_ureg, SPR_NOACCESS,
4426 &spr_read_ureg, SPR_NOACCESS,
4427 0x00000000);
4428 /* Memory management */
4429 register_low_BATs(env);
4430 init_excp_7450(env);
4431 env->dcache_line_size = 32;
4432 env->icache_line_size = 32;
4433 /* Allocate hardware IRQ controller */
4434 ppc6xx_irq_init(env_archcpu(env));
4435 }
4436
4437 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
4438 {
4439 DeviceClass *dc = DEVICE_CLASS(oc);
4440 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4441
4442 dc->desc = "PowerPC 7450 (aka G4)";
4443 pcc->init_proc = init_proc_7450;
4444 pcc->check_pow = check_pow_hid0_74xx;
4445 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4446 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4447 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4448 PPC_FLOAT_STFIWX |
4449 PPC_CACHE | PPC_CACHE_ICBI |
4450 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4451 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4452 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4453 PPC_MEM_TLBIA |
4454 PPC_SEGMENT | PPC_EXTERN |
4455 PPC_ALTIVEC;
4456 pcc->msr_mask = (1ull << MSR_VR) |
4457 (1ull << MSR_POW) |
4458 (1ull << MSR_ILE) |
4459 (1ull << MSR_EE) |
4460 (1ull << MSR_PR) |
4461 (1ull << MSR_FP) |
4462 (1ull << MSR_ME) |
4463 (1ull << MSR_FE0) |
4464 (1ull << MSR_SE) |
4465 (1ull << MSR_DE) |
4466 (1ull << MSR_FE1) |
4467 (1ull << MSR_EP) |
4468 (1ull << MSR_IR) |
4469 (1ull << MSR_DR) |
4470 (1ull << MSR_PMM) |
4471 (1ull << MSR_RI) |
4472 (1ull << MSR_LE);
4473 pcc->mmu_model = POWERPC_MMU_32B;
4474 pcc->excp_model = POWERPC_EXCP_74xx;
4475 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4476 pcc->bfd_mach = bfd_mach_ppc_7400;
4477 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4478 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4479 POWERPC_FLAG_BUS_CLK;
4480 }
4481
4482 static void init_proc_7445(CPUPPCState *env)
4483 {
4484 register_non_embedded_sprs(env);
4485 register_sdr1_sprs(env);
4486 register_74xx_sprs(env);
4487 vscr_init(env, 0x00010000);
4488 /* LDSTCR */
4489 spr_register(env, SPR_LDSTCR, "LDSTCR",
4490 SPR_NOACCESS, SPR_NOACCESS,
4491 &spr_read_generic, &spr_write_generic,
4492 0x00000000);
4493 /* ICTRL */
4494 spr_register(env, SPR_ICTRL, "ICTRL",
4495 SPR_NOACCESS, SPR_NOACCESS,
4496 &spr_read_generic, &spr_write_generic,
4497 0x00000000);
4498 /* MSSSR0 */
4499 spr_register(env, SPR_MSSSR0, "MSSSR0",
4500 SPR_NOACCESS, SPR_NOACCESS,
4501 &spr_read_generic, &spr_write_generic,
4502 0x00000000);
4503 /* PMC */
4504 spr_register(env, SPR_7XX_PMC5, "PMC5",
4505 SPR_NOACCESS, SPR_NOACCESS,
4506 &spr_read_generic, &spr_write_generic,
4507 0x00000000);
4508
4509 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4510 &spr_read_ureg, SPR_NOACCESS,
4511 &spr_read_ureg, SPR_NOACCESS,
4512 0x00000000);
4513
4514 spr_register(env, SPR_7XX_PMC6, "PMC6",
4515 SPR_NOACCESS, SPR_NOACCESS,
4516 &spr_read_generic, &spr_write_generic,
4517 0x00000000);
4518
4519 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4520 &spr_read_ureg, SPR_NOACCESS,
4521 &spr_read_ureg, SPR_NOACCESS,
4522 0x00000000);
4523 /* SPRGs */
4524 spr_register(env, SPR_SPRG4, "SPRG4",
4525 SPR_NOACCESS, SPR_NOACCESS,
4526 &spr_read_generic, &spr_write_generic,
4527 0x00000000);
4528 spr_register(env, SPR_USPRG4, "USPRG4",
4529 &spr_read_ureg, SPR_NOACCESS,
4530 &spr_read_ureg, SPR_NOACCESS,
4531 0x00000000);
4532 spr_register(env, SPR_SPRG5, "SPRG5",
4533 SPR_NOACCESS, SPR_NOACCESS,
4534 &spr_read_generic, &spr_write_generic,
4535 0x00000000);
4536 spr_register(env, SPR_USPRG5, "USPRG5",
4537 &spr_read_ureg, SPR_NOACCESS,
4538 &spr_read_ureg, SPR_NOACCESS,
4539 0x00000000);
4540 spr_register(env, SPR_SPRG6, "SPRG6",
4541 SPR_NOACCESS, SPR_NOACCESS,
4542 &spr_read_generic, &spr_write_generic,
4543 0x00000000);
4544 spr_register(env, SPR_USPRG6, "USPRG6",
4545 &spr_read_ureg, SPR_NOACCESS,
4546 &spr_read_ureg, SPR_NOACCESS,
4547 0x00000000);
4548 spr_register(env, SPR_SPRG7, "SPRG7",
4549 SPR_NOACCESS, SPR_NOACCESS,
4550 &spr_read_generic, &spr_write_generic,
4551 0x00000000);
4552 spr_register(env, SPR_USPRG7, "USPRG7",
4553 &spr_read_ureg, SPR_NOACCESS,
4554 &spr_read_ureg, SPR_NOACCESS,
4555 0x00000000);
4556 /* Memory management */
4557 register_low_BATs(env);
4558 register_high_BATs(env);
4559 init_excp_7450(env);
4560 env->dcache_line_size = 32;
4561 env->icache_line_size = 32;
4562 /* Allocate hardware IRQ controller */
4563 ppc6xx_irq_init(env_archcpu(env));
4564 }
4565
4566 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
4567 {
4568 DeviceClass *dc = DEVICE_CLASS(oc);
4569 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4570
4571 dc->desc = "PowerPC 7445 (aka G4)";
4572 pcc->init_proc = init_proc_7445;
4573 pcc->check_pow = check_pow_hid0_74xx;
4574 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4575 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4576 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4577 PPC_FLOAT_STFIWX |
4578 PPC_CACHE | PPC_CACHE_ICBI |
4579 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4580 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4581 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4582 PPC_MEM_TLBIA |
4583 PPC_SEGMENT | PPC_EXTERN |
4584 PPC_ALTIVEC;
4585 pcc->msr_mask = (1ull << MSR_VR) |
4586 (1ull << MSR_POW) |
4587 (1ull << MSR_ILE) |
4588 (1ull << MSR_EE) |
4589 (1ull << MSR_PR) |
4590 (1ull << MSR_FP) |
4591 (1ull << MSR_ME) |
4592 (1ull << MSR_FE0) |
4593 (1ull << MSR_SE) |
4594 (1ull << MSR_DE) |
4595 (1ull << MSR_FE1) |
4596 (1ull << MSR_EP) |
4597 (1ull << MSR_IR) |
4598 (1ull << MSR_DR) |
4599 (1ull << MSR_PMM) |
4600 (1ull << MSR_RI) |
4601 (1ull << MSR_LE);
4602 pcc->mmu_model = POWERPC_MMU_32B;
4603 pcc->excp_model = POWERPC_EXCP_74xx;
4604 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4605 pcc->bfd_mach = bfd_mach_ppc_7400;
4606 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4607 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4608 POWERPC_FLAG_BUS_CLK;
4609 }
4610
4611 static void init_proc_7455(CPUPPCState *env)
4612 {
4613 register_non_embedded_sprs(env);
4614 register_sdr1_sprs(env);
4615 register_74xx_sprs(env);
4616 vscr_init(env, 0x00010000);
4617 /* Level 3 cache control */
4618 register_l3_ctrl(env);
4619 /* LDSTCR */
4620 spr_register(env, SPR_LDSTCR, "LDSTCR",
4621 SPR_NOACCESS, SPR_NOACCESS,
4622 &spr_read_generic, &spr_write_generic,
4623 0x00000000);
4624 /* ICTRL */
4625 spr_register(env, SPR_ICTRL, "ICTRL",
4626 SPR_NOACCESS, SPR_NOACCESS,
4627 &spr_read_generic, &spr_write_generic,
4628 0x00000000);
4629 /* MSSSR0 */
4630 spr_register(env, SPR_MSSSR0, "MSSSR0",
4631 SPR_NOACCESS, SPR_NOACCESS,
4632 &spr_read_generic, &spr_write_generic,
4633 0x00000000);
4634 /* PMC */
4635 spr_register(env, SPR_7XX_PMC5, "PMC5",
4636 SPR_NOACCESS, SPR_NOACCESS,
4637 &spr_read_generic, &spr_write_generic,
4638 0x00000000);
4639
4640 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4641 &spr_read_ureg, SPR_NOACCESS,
4642 &spr_read_ureg, SPR_NOACCESS,
4643 0x00000000);
4644
4645 spr_register(env, SPR_7XX_PMC6, "PMC6",
4646 SPR_NOACCESS, SPR_NOACCESS,
4647 &spr_read_generic, &spr_write_generic,
4648 0x00000000);
4649
4650 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4651 &spr_read_ureg, SPR_NOACCESS,
4652 &spr_read_ureg, SPR_NOACCESS,
4653 0x00000000);
4654 /* SPRGs */
4655 spr_register(env, SPR_SPRG4, "SPRG4",
4656 SPR_NOACCESS, SPR_NOACCESS,
4657 &spr_read_generic, &spr_write_generic,
4658 0x00000000);
4659 spr_register(env, SPR_USPRG4, "USPRG4",
4660 &spr_read_ureg, SPR_NOACCESS,
4661 &spr_read_ureg, SPR_NOACCESS,
4662 0x00000000);
4663 spr_register(env, SPR_SPRG5, "SPRG5",
4664 SPR_NOACCESS, SPR_NOACCESS,
4665 &spr_read_generic, &spr_write_generic,
4666 0x00000000);
4667 spr_register(env, SPR_USPRG5, "USPRG5",
4668 &spr_read_ureg, SPR_NOACCESS,
4669 &spr_read_ureg, SPR_NOACCESS,
4670 0x00000000);
4671 spr_register(env, SPR_SPRG6, "SPRG6",
4672 SPR_NOACCESS, SPR_NOACCESS,
4673 &spr_read_generic, &spr_write_generic,
4674 0x00000000);
4675 spr_register(env, SPR_USPRG6, "USPRG6",
4676 &spr_read_ureg, SPR_NOACCESS,
4677 &spr_read_ureg, SPR_NOACCESS,
4678 0x00000000);
4679 spr_register(env, SPR_SPRG7, "SPRG7",
4680 SPR_NOACCESS, SPR_NOACCESS,
4681 &spr_read_generic, &spr_write_generic,
4682 0x00000000);
4683 spr_register(env, SPR_USPRG7, "USPRG7",
4684 &spr_read_ureg, SPR_NOACCESS,
4685 &spr_read_ureg, SPR_NOACCESS,
4686 0x00000000);
4687 /* Memory management */
4688 register_low_BATs(env);
4689 register_high_BATs(env);
4690 init_excp_7450(env);
4691 env->dcache_line_size = 32;
4692 env->icache_line_size = 32;
4693 /* Allocate hardware IRQ controller */
4694 ppc6xx_irq_init(env_archcpu(env));
4695 }
4696
4697 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
4698 {
4699 DeviceClass *dc = DEVICE_CLASS(oc);
4700 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4701
4702 dc->desc = "PowerPC 7455 (aka G4)";
4703 pcc->init_proc = init_proc_7455;
4704 pcc->check_pow = check_pow_hid0_74xx;
4705 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4706 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4707 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4708 PPC_FLOAT_STFIWX |
4709 PPC_CACHE | PPC_CACHE_ICBI |
4710 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4711 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4712 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4713 PPC_MEM_TLBIA |
4714 PPC_SEGMENT | PPC_EXTERN |
4715 PPC_ALTIVEC;
4716 pcc->msr_mask = (1ull << MSR_VR) |
4717 (1ull << MSR_POW) |
4718 (1ull << MSR_ILE) |
4719 (1ull << MSR_EE) |
4720 (1ull << MSR_PR) |
4721 (1ull << MSR_FP) |
4722 (1ull << MSR_ME) |
4723 (1ull << MSR_FE0) |
4724 (1ull << MSR_SE) |
4725 (1ull << MSR_DE) |
4726 (1ull << MSR_FE1) |
4727 (1ull << MSR_EP) |
4728 (1ull << MSR_IR) |
4729 (1ull << MSR_DR) |
4730 (1ull << MSR_PMM) |
4731 (1ull << MSR_RI) |
4732 (1ull << MSR_LE);
4733 pcc->mmu_model = POWERPC_MMU_32B;
4734 pcc->excp_model = POWERPC_EXCP_74xx;
4735 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4736 pcc->bfd_mach = bfd_mach_ppc_7400;
4737 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4738 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4739 POWERPC_FLAG_BUS_CLK;
4740 }
4741
4742 static void init_proc_7457(CPUPPCState *env)
4743 {
4744 register_non_embedded_sprs(env);
4745 register_sdr1_sprs(env);
4746 register_74xx_sprs(env);
4747 vscr_init(env, 0x00010000);
4748 /* Level 3 cache control */
4749 register_l3_ctrl(env);
4750 /* L3ITCR1 */
4751 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4752 SPR_NOACCESS, SPR_NOACCESS,
4753 &spr_read_generic, &spr_write_generic,
4754 0x00000000);
4755 /* L3ITCR2 */
4756 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4757 SPR_NOACCESS, SPR_NOACCESS,
4758 &spr_read_generic, &spr_write_generic,
4759 0x00000000);
4760 /* L3ITCR3 */
4761 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4762 SPR_NOACCESS, SPR_NOACCESS,
4763 &spr_read_generic, &spr_write_generic,
4764 0x00000000);
4765 /* L3OHCR */
4766 spr_register(env, SPR_L3OHCR, "L3OHCR",
4767 SPR_NOACCESS, SPR_NOACCESS,
4768 &spr_read_generic, &spr_write_generic,
4769 0x00000000);
4770 /* LDSTCR */
4771 spr_register(env, SPR_LDSTCR, "LDSTCR",
4772 SPR_NOACCESS, SPR_NOACCESS,
4773 &spr_read_generic, &spr_write_generic,
4774 0x00000000);
4775 /* ICTRL */
4776 spr_register(env, SPR_ICTRL, "ICTRL",
4777 SPR_NOACCESS, SPR_NOACCESS,
4778 &spr_read_generic, &spr_write_generic,
4779 0x00000000);
4780 /* MSSSR0 */
4781 spr_register(env, SPR_MSSSR0, "MSSSR0",
4782 SPR_NOACCESS, SPR_NOACCESS,
4783 &spr_read_generic, &spr_write_generic,
4784 0x00000000);
4785 /* PMC */
4786 spr_register(env, SPR_7XX_PMC5, "PMC5",
4787 SPR_NOACCESS, SPR_NOACCESS,
4788 &spr_read_generic, &spr_write_generic,
4789 0x00000000);
4790
4791 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4792 &spr_read_ureg, SPR_NOACCESS,
4793 &spr_read_ureg, SPR_NOACCESS,
4794 0x00000000);
4795
4796 spr_register(env, SPR_7XX_PMC6, "PMC6",
4797 SPR_NOACCESS, SPR_NOACCESS,
4798 &spr_read_generic, &spr_write_generic,
4799 0x00000000);
4800
4801 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4802 &spr_read_ureg, SPR_NOACCESS,
4803 &spr_read_ureg, SPR_NOACCESS,
4804 0x00000000);
4805 /* SPRGs */
4806 spr_register(env, SPR_SPRG4, "SPRG4",
4807 SPR_NOACCESS, SPR_NOACCESS,
4808 &spr_read_generic, &spr_write_generic,
4809 0x00000000);
4810 spr_register(env, SPR_USPRG4, "USPRG4",
4811 &spr_read_ureg, SPR_NOACCESS,
4812 &spr_read_ureg, SPR_NOACCESS,
4813 0x00000000);
4814 spr_register(env, SPR_SPRG5, "SPRG5",
4815 SPR_NOACCESS, SPR_NOACCESS,
4816 &spr_read_generic, &spr_write_generic,
4817 0x00000000);
4818 spr_register(env, SPR_USPRG5, "USPRG5",
4819 &spr_read_ureg, SPR_NOACCESS,
4820 &spr_read_ureg, SPR_NOACCESS,
4821 0x00000000);
4822 spr_register(env, SPR_SPRG6, "SPRG6",
4823 SPR_NOACCESS, SPR_NOACCESS,
4824 &spr_read_generic, &spr_write_generic,
4825 0x00000000);
4826 spr_register(env, SPR_USPRG6, "USPRG6",
4827 &spr_read_ureg, SPR_NOACCESS,
4828 &spr_read_ureg, SPR_NOACCESS,
4829 0x00000000);
4830 spr_register(env, SPR_SPRG7, "SPRG7",
4831 SPR_NOACCESS, SPR_NOACCESS,
4832 &spr_read_generic, &spr_write_generic,
4833 0x00000000);
4834 spr_register(env, SPR_USPRG7, "USPRG7",
4835 &spr_read_ureg, SPR_NOACCESS,
4836 &spr_read_ureg, SPR_NOACCESS,
4837 0x00000000);
4838 /* Memory management */
4839 register_low_BATs(env);
4840 register_high_BATs(env);
4841 init_excp_7450(env);
4842 env->dcache_line_size = 32;
4843 env->icache_line_size = 32;
4844 /* Allocate hardware IRQ controller */
4845 ppc6xx_irq_init(env_archcpu(env));
4846 }
4847
4848 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
4849 {
4850 DeviceClass *dc = DEVICE_CLASS(oc);
4851 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4852
4853 dc->desc = "PowerPC 7457 (aka G4)";
4854 pcc->init_proc = init_proc_7457;
4855 pcc->check_pow = check_pow_hid0_74xx;
4856 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4857 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4858 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4859 PPC_FLOAT_STFIWX |
4860 PPC_CACHE | PPC_CACHE_ICBI |
4861 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4862 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4863 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4864 PPC_MEM_TLBIA |
4865 PPC_SEGMENT | PPC_EXTERN |
4866 PPC_ALTIVEC;
4867 pcc->msr_mask = (1ull << MSR_VR) |
4868 (1ull << MSR_POW) |
4869 (1ull << MSR_ILE) |
4870 (1ull << MSR_EE) |
4871 (1ull << MSR_PR) |
4872 (1ull << MSR_FP) |
4873 (1ull << MSR_ME) |
4874 (1ull << MSR_FE0) |
4875 (1ull << MSR_SE) |
4876 (1ull << MSR_DE) |
4877 (1ull << MSR_FE1) |
4878 (1ull << MSR_EP) |
4879 (1ull << MSR_IR) |
4880 (1ull << MSR_DR) |
4881 (1ull << MSR_PMM) |
4882 (1ull << MSR_RI) |
4883 (1ull << MSR_LE);
4884 pcc->mmu_model = POWERPC_MMU_32B;
4885 pcc->excp_model = POWERPC_EXCP_74xx;
4886 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4887 pcc->bfd_mach = bfd_mach_ppc_7400;
4888 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4889 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4890 POWERPC_FLAG_BUS_CLK;
4891 }
4892
4893 static void init_proc_e600(CPUPPCState *env)
4894 {
4895 register_non_embedded_sprs(env);
4896 register_sdr1_sprs(env);
4897 register_74xx_sprs(env);
4898 vscr_init(env, 0x00010000);
4899
4900 spr_register(env, SPR_UBAMR, "UBAMR",
4901 &spr_read_ureg, SPR_NOACCESS,
4902 &spr_read_ureg, SPR_NOACCESS,
4903 0x00000000);
4904
4905 spr_register(env, SPR_LDSTCR, "LDSTCR",
4906 SPR_NOACCESS, SPR_NOACCESS,
4907 &spr_read_generic, &spr_write_generic,
4908 0x00000000);
4909
4910 spr_register(env, SPR_ICTRL, "ICTRL",
4911 SPR_NOACCESS, SPR_NOACCESS,
4912 &spr_read_generic, &spr_write_generic,
4913 0x00000000);
4914
4915 spr_register(env, SPR_MSSSR0, "MSSSR0",
4916 SPR_NOACCESS, SPR_NOACCESS,
4917 &spr_read_generic, &spr_write_generic,
4918 0x00000000);
4919
4920 spr_register(env, SPR_7XX_PMC5, "PMC5",
4921 SPR_NOACCESS, SPR_NOACCESS,
4922 &spr_read_generic, &spr_write_generic,
4923 0x00000000);
4924
4925 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4926 &spr_read_ureg, SPR_NOACCESS,
4927 &spr_read_ureg, SPR_NOACCESS,
4928 0x00000000);
4929
4930 spr_register(env, SPR_7XX_PMC6, "PMC6",
4931 SPR_NOACCESS, SPR_NOACCESS,
4932 &spr_read_generic, &spr_write_generic,
4933 0x00000000);
4934
4935 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4936 &spr_read_ureg, SPR_NOACCESS,
4937 &spr_read_ureg, SPR_NOACCESS,
4938 0x00000000);
4939 /* SPRGs */
4940 spr_register(env, SPR_SPRG4, "SPRG4",
4941 SPR_NOACCESS, SPR_NOACCESS,
4942 &spr_read_generic, &spr_write_generic,
4943 0x00000000);
4944 spr_register(env, SPR_USPRG4, "USPRG4",
4945 &spr_read_ureg, SPR_NOACCESS,
4946 &spr_read_ureg, SPR_NOACCESS,
4947 0x00000000);
4948 spr_register(env, SPR_SPRG5, "SPRG5",
4949 SPR_NOACCESS, SPR_NOACCESS,
4950 &spr_read_generic, &spr_write_generic,
4951 0x00000000);
4952 spr_register(env, SPR_USPRG5, "USPRG5",
4953 &spr_read_ureg, SPR_NOACCESS,
4954 &spr_read_ureg, SPR_NOACCESS,
4955 0x00000000);
4956 spr_register(env, SPR_SPRG6, "SPRG6",
4957 SPR_NOACCESS, SPR_NOACCESS,
4958 &spr_read_generic, &spr_write_generic,
4959 0x00000000);
4960 spr_register(env, SPR_USPRG6, "USPRG6",
4961 &spr_read_ureg, SPR_NOACCESS,
4962 &spr_read_ureg, SPR_NOACCESS,
4963 0x00000000);
4964 spr_register(env, SPR_SPRG7, "SPRG7",
4965 SPR_NOACCESS, SPR_NOACCESS,
4966 &spr_read_generic, &spr_write_generic,
4967 0x00000000);
4968 spr_register(env, SPR_USPRG7, "USPRG7",
4969 &spr_read_ureg, SPR_NOACCESS,
4970 &spr_read_ureg, SPR_NOACCESS,
4971 0x00000000);
4972 /* Memory management */
4973 register_low_BATs(env);
4974 register_high_BATs(env);
4975 init_excp_7450(env);
4976 env->dcache_line_size = 32;
4977 env->icache_line_size = 32;
4978 /* Allocate hardware IRQ controller */
4979 ppc6xx_irq_init(env_archcpu(env));
4980 }
4981
4982 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
4983 {
4984 DeviceClass *dc = DEVICE_CLASS(oc);
4985 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4986
4987 dc->desc = "PowerPC e600";
4988 pcc->init_proc = init_proc_e600;
4989 pcc->check_pow = check_pow_hid0_74xx;
4990 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4991 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4992 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4993 PPC_FLOAT_STFIWX |
4994 PPC_CACHE | PPC_CACHE_ICBI |
4995 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4996 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4997 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4998 PPC_MEM_TLBIA |
4999 PPC_SEGMENT | PPC_EXTERN |
5000 PPC_ALTIVEC;
5001 pcc->insns_flags2 = PPC_NONE;
5002 pcc->msr_mask = (1ull << MSR_VR) |
5003 (1ull << MSR_POW) |
5004 (1ull << MSR_ILE) |
5005 (1ull << MSR_EE) |
5006 (1ull << MSR_PR) |
5007 (1ull << MSR_FP) |
5008 (1ull << MSR_ME) |
5009 (1ull << MSR_FE0) |
5010 (1ull << MSR_SE) |
5011 (1ull << MSR_DE) |
5012 (1ull << MSR_FE1) |
5013 (1ull << MSR_EP) |
5014 (1ull << MSR_IR) |
5015 (1ull << MSR_DR) |
5016 (1ull << MSR_PMM) |
5017 (1ull << MSR_RI) |
5018 (1ull << MSR_LE);
5019 pcc->mmu_model = POWERPC_MMU_32B;
5020 pcc->excp_model = POWERPC_EXCP_74xx;
5021 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5022 pcc->bfd_mach = bfd_mach_ppc_7400;
5023 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5024 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5025 POWERPC_FLAG_BUS_CLK;
5026 }
5027
5028 #if defined(TARGET_PPC64)
5029 #if defined(CONFIG_USER_ONLY)
5030 #define POWERPC970_HID5_INIT 0x00000080
5031 #else
5032 #define POWERPC970_HID5_INIT 0x00000000
5033 #endif
5034
5035 static int check_pow_970(CPUPPCState *env)
5036 {
5037 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5038 return 1;
5039 }
5040
5041 return 0;
5042 }
5043
5044 static void register_970_hid_sprs(CPUPPCState *env)
5045 {
5046 /* Hardware implementation registers */
5047 spr_register(env, SPR_HID0, "HID0",
5048 SPR_NOACCESS, SPR_NOACCESS,
5049 &spr_read_generic, &spr_write_clear,
5050 0x60000000);
5051 spr_register(env, SPR_HID1, "HID1",
5052 SPR_NOACCESS, SPR_NOACCESS,
5053 &spr_read_generic, &spr_write_generic,
5054 0x00000000);
5055 spr_register(env, SPR_970_HID5, "HID5",
5056 SPR_NOACCESS, SPR_NOACCESS,
5057 &spr_read_generic, &spr_write_generic,
5058 POWERPC970_HID5_INIT);
5059 }
5060
5061 static void register_970_hior_sprs(CPUPPCState *env)
5062 {
5063 spr_register(env, SPR_HIOR, "SPR_HIOR",
5064 SPR_NOACCESS, SPR_NOACCESS,
5065 &spr_read_hior, &spr_write_hior,
5066 0x00000000);
5067 }
5068
5069 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5070 {
5071 spr_register(env, SPR_CTRL, "SPR_CTRL",
5072 SPR_NOACCESS, SPR_NOACCESS,
5073 SPR_NOACCESS, &spr_write_CTRL,
5074 0x00000000);
5075 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
5076 &spr_read_ureg, SPR_NOACCESS,
5077 &spr_read_ureg, SPR_NOACCESS,
5078 0x00000000);
5079 }
5080
5081 static void register_book3s_altivec_sprs(CPUPPCState *env)
5082 {
5083 if (!(env->insns_flags & PPC_ALTIVEC)) {
5084 return;
5085 }
5086
5087 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5088 &spr_read_generic, &spr_write_generic,
5089 &spr_read_generic, &spr_write_generic,
5090 KVM_REG_PPC_VRSAVE, 0x00000000);
5091
5092 }
5093
5094 static void register_book3s_dbg_sprs(CPUPPCState *env)
5095 {
5096 /*
5097 * TODO: different specs define different scopes for these,
5098 * will have to address this:
5099 * 970: super/write and super/read
5100 * powerisa 2.03..2.04: hypv/write and super/read.
5101 * powerisa 2.05 and newer: hypv/write and hypv/read.
5102 */
5103 spr_register_kvm(env, SPR_DABR, "DABR",
5104 SPR_NOACCESS, SPR_NOACCESS,
5105 &spr_read_generic, &spr_write_generic,
5106 KVM_REG_PPC_DABR, 0x00000000);
5107 spr_register_kvm(env, SPR_DABRX, "DABRX",
5108 SPR_NOACCESS, SPR_NOACCESS,
5109 &spr_read_generic, &spr_write_generic,
5110 KVM_REG_PPC_DABRX, 0x00000000);
5111 }
5112
5113 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5114 {
5115 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5116 SPR_NOACCESS, SPR_NOACCESS,
5117 SPR_NOACCESS, SPR_NOACCESS,
5118 &spr_read_generic, &spr_write_generic,
5119 KVM_REG_PPC_DAWR, 0x00000000);
5120 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5121 SPR_NOACCESS, SPR_NOACCESS,
5122 SPR_NOACCESS, SPR_NOACCESS,
5123 &spr_read_generic, &spr_write_generic,
5124 KVM_REG_PPC_DAWRX, 0x00000000);
5125 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5126 SPR_NOACCESS, SPR_NOACCESS,
5127 SPR_NOACCESS, SPR_NOACCESS,
5128 &spr_read_generic, &spr_write_generic,
5129 KVM_REG_PPC_CIABR, 0x00000000);
5130 }
5131
5132 static void register_970_dbg_sprs(CPUPPCState *env)
5133 {
5134 /* Breakpoints */
5135 spr_register(env, SPR_IABR, "IABR",
5136 SPR_NOACCESS, SPR_NOACCESS,
5137 &spr_read_generic, &spr_write_generic,
5138 0x00000000);
5139 }
5140
5141 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5142 {
5143 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5144 SPR_NOACCESS, SPR_NOACCESS,
5145 &spr_read_generic, &spr_write_MMCR0,
5146 KVM_REG_PPC_MMCR0, 0x80000000);
5147 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5148 SPR_NOACCESS, SPR_NOACCESS,
5149 &spr_read_generic, &spr_write_MMCR1,
5150 KVM_REG_PPC_MMCR1, 0x00000000);
5151 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5152 SPR_NOACCESS, SPR_NOACCESS,
5153 &spr_read_generic, &spr_write_generic,
5154 KVM_REG_PPC_MMCRA, 0x00000000);
5155 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5156 SPR_NOACCESS, SPR_NOACCESS,
5157 &spr_read_PMC, &spr_write_PMC,
5158 KVM_REG_PPC_PMC1, 0x00000000);
5159 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5160 SPR_NOACCESS, SPR_NOACCESS,
5161 &spr_read_PMC, &spr_write_PMC,
5162 KVM_REG_PPC_PMC2, 0x00000000);
5163 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5164 SPR_NOACCESS, SPR_NOACCESS,
5165 &spr_read_PMC, &spr_write_PMC,
5166 KVM_REG_PPC_PMC3, 0x00000000);
5167 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5168 SPR_NOACCESS, SPR_NOACCESS,
5169 &spr_read_PMC, &spr_write_PMC,
5170 KVM_REG_PPC_PMC4, 0x00000000);
5171 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5172 SPR_NOACCESS, SPR_NOACCESS,
5173 &spr_read_PMC, &spr_write_PMC,
5174 KVM_REG_PPC_PMC5, 0x00000000);
5175 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5176 SPR_NOACCESS, SPR_NOACCESS,
5177 &spr_read_PMC, &spr_write_PMC,
5178 KVM_REG_PPC_PMC6, 0x00000000);
5179 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5180 SPR_NOACCESS, SPR_NOACCESS,
5181 &spr_read_generic, &spr_write_generic,
5182 KVM_REG_PPC_SIAR, 0x00000000);
5183 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5184 SPR_NOACCESS, SPR_NOACCESS,
5185 &spr_read_generic, &spr_write_generic,
5186 KVM_REG_PPC_SDAR, 0x00000000);
5187 }
5188
5189 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5190 {
5191 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5192 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5193 &spr_read_ureg, &spr_write_ureg,
5194 0x80000000);
5195 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5196 &spr_read_ureg, SPR_NOACCESS,
5197 &spr_read_ureg, &spr_write_ureg,
5198 0x00000000);
5199 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5200 &spr_read_ureg, SPR_NOACCESS,
5201 &spr_read_ureg, &spr_write_ureg,
5202 0x00000000);
5203 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5204 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5205 &spr_read_ureg, &spr_write_ureg,
5206 0x00000000);
5207 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5208 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5209 &spr_read_ureg, &spr_write_ureg,
5210 0x00000000);
5211 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5212 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5213 &spr_read_ureg, &spr_write_ureg,
5214 0x00000000);
5215 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5216 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5217 &spr_read_ureg, &spr_write_ureg,
5218 0x00000000);
5219 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5220 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5221 &spr_read_ureg, &spr_write_ureg,
5222 0x00000000);
5223 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5224 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5225 &spr_read_ureg, &spr_write_ureg,
5226 0x00000000);
5227 spr_register(env, SPR_POWER_USIAR, "USIAR",
5228 &spr_read_ureg, SPR_NOACCESS,
5229 &spr_read_ureg, &spr_write_ureg,
5230 0x00000000);
5231 spr_register(env, SPR_POWER_USDAR, "USDAR",
5232 &spr_read_ureg, SPR_NOACCESS,
5233 &spr_read_ureg, &spr_write_ureg,
5234 0x00000000);
5235 }
5236
5237 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5238 {
5239 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5240 SPR_NOACCESS, SPR_NOACCESS,
5241 &spr_read_generic, &spr_write_generic,
5242 KVM_REG_PPC_PMC7, 0x00000000);
5243 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5244 SPR_NOACCESS, SPR_NOACCESS,
5245 &spr_read_generic, &spr_write_generic,
5246 KVM_REG_PPC_PMC8, 0x00000000);
5247 }
5248
5249 static void register_970_pmu_user_sprs(CPUPPCState *env)
5250 {
5251 spr_register(env, SPR_970_UPMC7, "UPMC7",
5252 &spr_read_ureg, SPR_NOACCESS,
5253 &spr_read_ureg, &spr_write_ureg,
5254 0x00000000);
5255 spr_register(env, SPR_970_UPMC8, "UPMC8",
5256 &spr_read_ureg, SPR_NOACCESS,
5257 &spr_read_ureg, &spr_write_ureg,
5258 0x00000000);
5259 }
5260
5261 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5262 {
5263 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5264 SPR_NOACCESS, SPR_NOACCESS,
5265 &spr_read_generic, &spr_write_generic,
5266 KVM_REG_PPC_MMCR2, 0x00000000);
5267 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5268 SPR_NOACCESS, SPR_NOACCESS,
5269 &spr_read_generic, &spr_write_generic,
5270 KVM_REG_PPC_MMCRS, 0x00000000);
5271 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5272 SPR_NOACCESS, SPR_NOACCESS,
5273 &spr_read_generic, &spr_write_generic,
5274 KVM_REG_PPC_SIER, 0x00000000);
5275 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5276 SPR_NOACCESS, SPR_NOACCESS,
5277 &spr_read_generic, &spr_write_generic,
5278 KVM_REG_PPC_SPMC1, 0x00000000);
5279 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5280 SPR_NOACCESS, SPR_NOACCESS,
5281 &spr_read_generic, &spr_write_generic,
5282 KVM_REG_PPC_SPMC2, 0x00000000);
5283 spr_register_kvm(env, SPR_TACR, "TACR",
5284 SPR_NOACCESS, SPR_NOACCESS,
5285 &spr_read_generic, &spr_write_generic,
5286 KVM_REG_PPC_TACR, 0x00000000);
5287 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5288 SPR_NOACCESS, SPR_NOACCESS,
5289 &spr_read_generic, &spr_write_generic,
5290 KVM_REG_PPC_TCSCR, 0x00000000);
5291 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5292 SPR_NOACCESS, SPR_NOACCESS,
5293 &spr_read_generic, &spr_write_generic,
5294 KVM_REG_PPC_CSIGR, 0x00000000);
5295 }
5296
5297 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5298 {
5299 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5300 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5301 &spr_read_ureg, &spr_write_ureg,
5302 0x00000000);
5303 spr_register(env, SPR_POWER_USIER, "USIER",
5304 &spr_read_generic, SPR_NOACCESS,
5305 &spr_read_generic, &spr_write_generic,
5306 0x00000000);
5307 }
5308
5309 static void register_power5p_ear_sprs(CPUPPCState *env)
5310 {
5311 /* External access control */
5312 spr_register(env, SPR_EAR, "EAR",
5313 SPR_NOACCESS, SPR_NOACCESS,
5314 &spr_read_generic, &spr_write_generic,
5315 0x00000000);
5316 }
5317
5318 static void register_power5p_tb_sprs(CPUPPCState *env)
5319 {
5320 /* TBU40 (High 40 bits of the Timebase register */
5321 spr_register_hv(env, SPR_TBU40, "TBU40",
5322 SPR_NOACCESS, SPR_NOACCESS,
5323 SPR_NOACCESS, SPR_NOACCESS,
5324 SPR_NOACCESS, &spr_write_tbu40,
5325 0x00000000);
5326 }
5327
5328 static void register_970_lpar_sprs(CPUPPCState *env)
5329 {
5330 #if !defined(CONFIG_USER_ONLY)
5331 /*
5332 * PPC970: HID4 covers things later controlled by the LPCR and
5333 * RMOR in later CPUs, but with a different encoding. We only
5334 * support the 970 in "Apple mode" which has all hypervisor
5335 * facilities disabled by strapping, so we can basically just
5336 * ignore it
5337 */
5338 spr_register(env, SPR_970_HID4, "HID4",
5339 SPR_NOACCESS, SPR_NOACCESS,
5340 &spr_read_generic, &spr_write_generic,
5341 0x00000000);
5342 #endif
5343 }
5344
5345 static void register_power5p_lpar_sprs(CPUPPCState *env)
5346 {
5347 #if !defined(CONFIG_USER_ONLY)
5348 /* Logical partitionning */
5349 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5350 SPR_NOACCESS, SPR_NOACCESS,
5351 SPR_NOACCESS, SPR_NOACCESS,
5352 &spr_read_generic, &spr_write_lpcr,
5353 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5354 spr_register_hv(env, SPR_HDEC, "HDEC",
5355 SPR_NOACCESS, SPR_NOACCESS,
5356 SPR_NOACCESS, SPR_NOACCESS,
5357 &spr_read_hdecr, &spr_write_hdecr, 0);
5358 #endif
5359 }
5360
5361 static void register_book3s_ids_sprs(CPUPPCState *env)
5362 {
5363 /* FIXME: Will need to deal with thread vs core only SPRs */
5364
5365 /* Processor identification */
5366 spr_register_hv(env, SPR_PIR, "PIR",
5367 SPR_NOACCESS, SPR_NOACCESS,
5368 &spr_read_generic, SPR_NOACCESS,
5369 &spr_read_generic, NULL,
5370 0x00000000);
5371 spr_register_hv(env, SPR_HID0, "HID0",
5372 SPR_NOACCESS, SPR_NOACCESS,
5373 SPR_NOACCESS, SPR_NOACCESS,
5374 &spr_read_generic, &spr_write_generic,
5375 0x00000000);
5376 spr_register_hv(env, SPR_TSCR, "TSCR",
5377 SPR_NOACCESS, SPR_NOACCESS,
5378 SPR_NOACCESS, SPR_NOACCESS,
5379 &spr_read_generic, &spr_write_generic,
5380 0x00000000);
5381 spr_register_hv(env, SPR_HMER, "HMER",
5382 SPR_NOACCESS, SPR_NOACCESS,
5383 SPR_NOACCESS, SPR_NOACCESS,
5384 &spr_read_generic, &spr_write_hmer,
5385 0x00000000);
5386 spr_register_hv(env, SPR_HMEER, "HMEER",
5387 SPR_NOACCESS, SPR_NOACCESS,
5388 SPR_NOACCESS, SPR_NOACCESS,
5389 &spr_read_generic, &spr_write_generic,
5390 0x00000000);
5391 spr_register_hv(env, SPR_TFMR, "TFMR",
5392 SPR_NOACCESS, SPR_NOACCESS,
5393 SPR_NOACCESS, SPR_NOACCESS,
5394 &spr_read_generic, &spr_write_generic,
5395 0x00000000);
5396 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5397 SPR_NOACCESS, SPR_NOACCESS,
5398 SPR_NOACCESS, SPR_NOACCESS,
5399 &spr_read_generic, &spr_write_lpidr,
5400 0x00000000);
5401 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5402 SPR_NOACCESS, SPR_NOACCESS,
5403 SPR_NOACCESS, SPR_NOACCESS,
5404 &spr_read_generic, &spr_write_generic,
5405 0x00000000);
5406 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5407 SPR_NOACCESS, SPR_NOACCESS,
5408 SPR_NOACCESS, SPR_NOACCESS,
5409 &spr_read_generic, &spr_write_generic,
5410 0x00000000);
5411 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5412 SPR_NOACCESS, SPR_NOACCESS,
5413 SPR_NOACCESS, SPR_NOACCESS,
5414 &spr_read_generic, &spr_write_generic,
5415 0x00000000);
5416 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5417 SPR_NOACCESS, SPR_NOACCESS,
5418 SPR_NOACCESS, SPR_NOACCESS,
5419 &spr_read_generic, &spr_write_generic,
5420 0x00000000);
5421 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5422 SPR_NOACCESS, SPR_NOACCESS,
5423 SPR_NOACCESS, SPR_NOACCESS,
5424 &spr_read_generic, &spr_write_generic,
5425 0x00000000);
5426 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5427 SPR_NOACCESS, SPR_NOACCESS,
5428 SPR_NOACCESS, SPR_NOACCESS,
5429 &spr_read_generic, &spr_write_generic,
5430 0x00000000);
5431 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5432 SPR_NOACCESS, SPR_NOACCESS,
5433 SPR_NOACCESS, SPR_NOACCESS,
5434 &spr_read_generic, &spr_write_generic,
5435 0x00000000);
5436 spr_register_hv(env, SPR_HDAR, "HDAR",
5437 SPR_NOACCESS, SPR_NOACCESS,
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5442 SPR_NOACCESS, SPR_NOACCESS,
5443 SPR_NOACCESS, SPR_NOACCESS,
5444 &spr_read_generic, &spr_write_generic,
5445 0x00000000);
5446 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5447 SPR_NOACCESS, SPR_NOACCESS,
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_generic,
5450 0x00000000);
5451 }
5452
5453 static void register_rmor_sprs(CPUPPCState *env)
5454 {
5455 spr_register_hv(env, SPR_RMOR, "RMOR",
5456 SPR_NOACCESS, SPR_NOACCESS,
5457 SPR_NOACCESS, SPR_NOACCESS,
5458 &spr_read_generic, &spr_write_generic,
5459 0x00000000);
5460 }
5461
5462 static void register_power8_ids_sprs(CPUPPCState *env)
5463 {
5464 /* Thread identification */
5465 spr_register(env, SPR_TIR, "TIR",
5466 SPR_NOACCESS, SPR_NOACCESS,
5467 &spr_read_generic, SPR_NOACCESS,
5468 0x00000000);
5469 }
5470
5471 static void register_book3s_purr_sprs(CPUPPCState *env)
5472 {
5473 #if !defined(CONFIG_USER_ONLY)
5474 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5475 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5476 &spr_read_purr, SPR_NOACCESS,
5477 &spr_read_purr, SPR_NOACCESS,
5478 &spr_read_purr, &spr_write_purr,
5479 KVM_REG_PPC_PURR, 0x00000000);
5480 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5481 &spr_read_purr, SPR_NOACCESS,
5482 &spr_read_purr, SPR_NOACCESS,
5483 &spr_read_purr, &spr_write_purr,
5484 KVM_REG_PPC_SPURR, 0x00000000);
5485 #endif
5486 }
5487
5488 static void register_power6_dbg_sprs(CPUPPCState *env)
5489 {
5490 #if !defined(CONFIG_USER_ONLY)
5491 spr_register(env, SPR_CFAR, "SPR_CFAR",
5492 SPR_NOACCESS, SPR_NOACCESS,
5493 &spr_read_cfar, &spr_write_cfar,
5494 0x00000000);
5495 #endif
5496 }
5497
5498 static void register_power5p_common_sprs(CPUPPCState *env)
5499 {
5500 spr_register_kvm(env, SPR_PPR, "PPR",
5501 &spr_read_generic, &spr_write_generic,
5502 &spr_read_generic, &spr_write_generic,
5503 KVM_REG_PPC_PPR, 0x00000000);
5504 }
5505
5506 static void register_power6_common_sprs(CPUPPCState *env)
5507 {
5508 #if !defined(CONFIG_USER_ONLY)
5509 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
5510 SPR_NOACCESS, SPR_NOACCESS,
5511 &spr_read_generic, &spr_write_generic,
5512 KVM_REG_PPC_DSCR, 0x00000000);
5513 #endif
5514 /*
5515 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
5516 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
5517 */
5518 spr_register_hv(env, SPR_PCR, "PCR",
5519 SPR_NOACCESS, SPR_NOACCESS,
5520 SPR_NOACCESS, SPR_NOACCESS,
5521 &spr_read_generic, &spr_write_pcr,
5522 0x00000000);
5523 }
5524
5525 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
5526 {
5527 spr_register_kvm(env, SPR_TAR, "TAR",
5528 &spr_read_tar, &spr_write_tar,
5529 &spr_read_generic, &spr_write_generic,
5530 KVM_REG_PPC_TAR, 0x00000000);
5531 }
5532
5533 static void register_power8_tm_sprs(CPUPPCState *env)
5534 {
5535 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
5536 &spr_read_tm, &spr_write_tm,
5537 &spr_read_tm, &spr_write_tm,
5538 KVM_REG_PPC_TFHAR, 0x00000000);
5539 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
5540 &spr_read_tm, &spr_write_tm,
5541 &spr_read_tm, &spr_write_tm,
5542 KVM_REG_PPC_TFIAR, 0x00000000);
5543 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
5544 &spr_read_tm, &spr_write_tm,
5545 &spr_read_tm, &spr_write_tm,
5546 KVM_REG_PPC_TEXASR, 0x00000000);
5547 spr_register(env, SPR_TEXASRU, "TEXASRU",
5548 &spr_read_tm_upper32, &spr_write_tm_upper32,
5549 &spr_read_tm_upper32, &spr_write_tm_upper32,
5550 0x00000000);
5551 }
5552
5553 static void register_power8_ebb_sprs(CPUPPCState *env)
5554 {
5555 spr_register(env, SPR_BESCRS, "BESCRS",
5556 &spr_read_ebb, &spr_write_ebb,
5557 &spr_read_generic, &spr_write_generic,
5558 0x00000000);
5559 spr_register(env, SPR_BESCRSU, "BESCRSU",
5560 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5561 &spr_read_prev_upper32, &spr_write_prev_upper32,
5562 0x00000000);
5563 spr_register(env, SPR_BESCRR, "BESCRR",
5564 &spr_read_ebb, &spr_write_ebb,
5565 &spr_read_generic, &spr_write_generic,
5566 0x00000000);
5567 spr_register(env, SPR_BESCRRU, "BESCRRU",
5568 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5569 &spr_read_prev_upper32, &spr_write_prev_upper32,
5570 0x00000000);
5571 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
5572 &spr_read_ebb, &spr_write_ebb,
5573 &spr_read_generic, &spr_write_generic,
5574 KVM_REG_PPC_EBBHR, 0x00000000);
5575 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
5576 &spr_read_ebb, &spr_write_ebb,
5577 &spr_read_generic, &spr_write_generic,
5578 KVM_REG_PPC_EBBRR, 0x00000000);
5579 spr_register_kvm(env, SPR_BESCR, "BESCR",
5580 &spr_read_ebb, &spr_write_ebb,
5581 &spr_read_generic, &spr_write_generic,
5582 KVM_REG_PPC_BESCR, 0x00000000);
5583 }
5584
5585 /* Virtual Time Base */
5586 static void register_vtb_sprs(CPUPPCState *env)
5587 {
5588 spr_register_kvm_hv(env, SPR_VTB, "VTB",
5589 SPR_NOACCESS, SPR_NOACCESS,
5590 &spr_read_vtb, SPR_NOACCESS,
5591 &spr_read_vtb, &spr_write_vtb,
5592 KVM_REG_PPC_VTB, 0x00000000);
5593 }
5594
5595 static void register_power8_fscr_sprs(CPUPPCState *env)
5596 {
5597 #if defined(CONFIG_USER_ONLY)
5598 target_ulong initval = 1ULL << FSCR_TAR;
5599 #else
5600 target_ulong initval = 0;
5601 #endif
5602 spr_register_kvm(env, SPR_FSCR, "FSCR",
5603 SPR_NOACCESS, SPR_NOACCESS,
5604 &spr_read_generic, &spr_write_generic,
5605 KVM_REG_PPC_FSCR, initval);
5606 }
5607
5608 static void register_power8_pspb_sprs(CPUPPCState *env)
5609 {
5610 spr_register_kvm(env, SPR_PSPB, "PSPB",
5611 SPR_NOACCESS, SPR_NOACCESS,
5612 &spr_read_generic, &spr_write_generic32,
5613 KVM_REG_PPC_PSPB, 0);
5614 }
5615
5616 static void register_power8_dpdes_sprs(CPUPPCState *env)
5617 {
5618 #if !defined(CONFIG_USER_ONLY)
5619 /* Directed Privileged Door-bell Exception State, used for IPI */
5620 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
5621 SPR_NOACCESS, SPR_NOACCESS,
5622 &spr_read_dpdes, SPR_NOACCESS,
5623 &spr_read_dpdes, &spr_write_dpdes,
5624 KVM_REG_PPC_DPDES, 0x00000000);
5625 #endif
5626 }
5627
5628 static void register_power8_ic_sprs(CPUPPCState *env)
5629 {
5630 #if !defined(CONFIG_USER_ONLY)
5631 spr_register_hv(env, SPR_IC, "IC",
5632 SPR_NOACCESS, SPR_NOACCESS,
5633 &spr_read_generic, SPR_NOACCESS,
5634 &spr_read_generic, &spr_write_generic,
5635 0);
5636 #endif
5637 }
5638
5639 static void register_power8_book4_sprs(CPUPPCState *env)
5640 {
5641 /* Add a number of P8 book4 registers */
5642 #if !defined(CONFIG_USER_ONLY)
5643 spr_register_kvm(env, SPR_ACOP, "ACOP",
5644 SPR_NOACCESS, SPR_NOACCESS,
5645 &spr_read_generic, &spr_write_generic,
5646 KVM_REG_PPC_ACOP, 0);
5647 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
5648 SPR_NOACCESS, SPR_NOACCESS,
5649 &spr_read_generic, &spr_write_pidr,
5650 KVM_REG_PPC_PID, 0);
5651 spr_register_kvm(env, SPR_WORT, "WORT",
5652 SPR_NOACCESS, SPR_NOACCESS,
5653 &spr_read_generic, &spr_write_generic,
5654 KVM_REG_PPC_WORT, 0);
5655 #endif
5656 }
5657
5658 static void register_power7_book4_sprs(CPUPPCState *env)
5659 {
5660 /* Add a number of P7 book4 registers */
5661 #if !defined(CONFIG_USER_ONLY)
5662 spr_register_kvm(env, SPR_ACOP, "ACOP",
5663 SPR_NOACCESS, SPR_NOACCESS,
5664 &spr_read_generic, &spr_write_generic,
5665 KVM_REG_PPC_ACOP, 0);
5666 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
5667 SPR_NOACCESS, SPR_NOACCESS,
5668 &spr_read_generic, &spr_write_generic,
5669 KVM_REG_PPC_PID, 0);
5670 #endif
5671 }
5672
5673 static void register_power8_rpr_sprs(CPUPPCState *env)
5674 {
5675 #if !defined(CONFIG_USER_ONLY)
5676 spr_register_hv(env, SPR_RPR, "RPR",
5677 SPR_NOACCESS, SPR_NOACCESS,
5678 SPR_NOACCESS, SPR_NOACCESS,
5679 &spr_read_generic, &spr_write_generic,
5680 0x00000103070F1F3F);
5681 #endif
5682 }
5683
5684 static void register_power9_mmu_sprs(CPUPPCState *env)
5685 {
5686 #if !defined(CONFIG_USER_ONLY)
5687 /* Partition Table Control */
5688 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
5689 SPR_NOACCESS, SPR_NOACCESS,
5690 SPR_NOACCESS, SPR_NOACCESS,
5691 &spr_read_generic, &spr_write_ptcr,
5692 KVM_REG_PPC_PTCR, 0x00000000);
5693 /* Address Segment Descriptor Register */
5694 spr_register_hv(env, SPR_ASDR, "ASDR",
5695 SPR_NOACCESS, SPR_NOACCESS,
5696 SPR_NOACCESS, SPR_NOACCESS,
5697 &spr_read_generic, &spr_write_generic,
5698 0x0000000000000000);
5699 #endif
5700 }
5701
5702 static void register_power10_hash_sprs(CPUPPCState *env)
5703 {
5704 /*
5705 * it's the OS responsability to generate a random value for the registers
5706 * in each process' context. So, initialize it with 0 here.
5707 */
5708 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0;
5709 #if defined(CONFIG_USER_ONLY)
5710 /* in linux-user, setup the hash register with a random value */
5711 GRand *rand = g_rand_new();
5712 hashkeyr_initial_value =
5713 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5714 hashpkeyr_initial_value =
5715 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5716 g_rand_free(rand);
5717 #endif
5718 spr_register(env, SPR_HASHKEYR, "HASHKEYR",
5719 SPR_NOACCESS, SPR_NOACCESS,
5720 &spr_read_generic, &spr_write_generic,
5721 hashkeyr_initial_value);
5722 spr_register_hv(env, SPR_HASHPKEYR, "HASHPKEYR",
5723 SPR_NOACCESS, SPR_NOACCESS,
5724 SPR_NOACCESS, SPR_NOACCESS,
5725 &spr_read_generic, &spr_write_generic,
5726 hashpkeyr_initial_value);
5727 }
5728
5729 static void register_power10_dexcr_sprs(CPUPPCState *env)
5730 {
5731 spr_register(env, SPR_DEXCR, "DEXCR",
5732 SPR_NOACCESS, SPR_NOACCESS,
5733 &spr_read_generic, &spr_write_generic,
5734 0);
5735
5736 spr_register(env, SPR_UDEXCR, "DEXCR",
5737 &spr_read_dexcr_ureg, SPR_NOACCESS,
5738 &spr_read_dexcr_ureg, SPR_NOACCESS,
5739 0);
5740
5741 spr_register_hv(env, SPR_HDEXCR, "HDEXCR",
5742 SPR_NOACCESS, SPR_NOACCESS,
5743 SPR_NOACCESS, SPR_NOACCESS,
5744 &spr_read_generic, &spr_write_generic,
5745 0);
5746
5747 spr_register(env, SPR_UHDEXCR, "HDEXCR",
5748 &spr_read_dexcr_ureg, SPR_NOACCESS,
5749 &spr_read_dexcr_ureg, SPR_NOACCESS,
5750 0);
5751 }
5752
5753 /*
5754 * Initialize PMU counter overflow timers for Power8 and
5755 * newer Power chips when using TCG.
5756 */
5757 static void init_tcg_pmu_power8(CPUPPCState *env)
5758 {
5759 /* Init PMU overflow timers */
5760 if (tcg_enabled()) {
5761 cpu_ppc_pmu_init(env);
5762 }
5763 }
5764
5765 static void init_proc_book3s_common(CPUPPCState *env)
5766 {
5767 register_non_embedded_sprs(env);
5768 register_book3s_altivec_sprs(env);
5769 register_book3s_pmu_sup_sprs(env);
5770 register_book3s_pmu_user_sprs(env);
5771 register_book3s_ctrl_sprs(env);
5772 /*
5773 * Can't find information on what this should be on reset. This
5774 * value is the one used by 74xx processors.
5775 */
5776 vscr_init(env, 0x00010000);
5777
5778 spr_register(env, SPR_USPRG3, "USPRG3",
5779 &spr_read_ureg, SPR_NOACCESS,
5780 &spr_read_ureg, SPR_NOACCESS,
5781 0x00000000);
5782 }
5783
5784 static void init_proc_970(CPUPPCState *env)
5785 {
5786 /* Common Registers */
5787 init_proc_book3s_common(env);
5788 register_sdr1_sprs(env);
5789 register_book3s_dbg_sprs(env);
5790
5791 /* 970 Specific Registers */
5792 register_970_hid_sprs(env);
5793 register_970_hior_sprs(env);
5794 register_low_BATs(env);
5795 register_970_pmu_sup_sprs(env);
5796 register_970_pmu_user_sprs(env);
5797 register_970_lpar_sprs(env);
5798 register_970_dbg_sprs(env);
5799
5800 /* env variables */
5801 env->dcache_line_size = 128;
5802 env->icache_line_size = 128;
5803
5804 /* Allocate hardware IRQ controller */
5805 init_excp_970(env);
5806 ppc970_irq_init(env_archcpu(env));
5807 }
5808
5809 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
5810 {
5811 DeviceClass *dc = DEVICE_CLASS(oc);
5812 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5813
5814 dc->desc = "PowerPC 970";
5815 pcc->init_proc = init_proc_970;
5816 pcc->check_pow = check_pow_970;
5817 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5818 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5819 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5820 PPC_FLOAT_STFIWX |
5821 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5822 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5823 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5824 PPC_64B | PPC_ALTIVEC |
5825 PPC_SEGMENT_64B | PPC_SLBI;
5826 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
5827 pcc->msr_mask = (1ull << MSR_SF) |
5828 (1ull << MSR_VR) |
5829 (1ull << MSR_POW) |
5830 (1ull << MSR_EE) |
5831 (1ull << MSR_PR) |
5832 (1ull << MSR_FP) |
5833 (1ull << MSR_ME) |
5834 (1ull << MSR_FE0) |
5835 (1ull << MSR_SE) |
5836 (1ull << MSR_DE) |
5837 (1ull << MSR_FE1) |
5838 (1ull << MSR_IR) |
5839 (1ull << MSR_DR) |
5840 (1ull << MSR_PMM) |
5841 (1ull << MSR_RI);
5842 pcc->mmu_model = POWERPC_MMU_64B;
5843 #if defined(CONFIG_SOFTMMU)
5844 pcc->hash64_opts = &ppc_hash64_opts_basic;
5845 #endif
5846 pcc->excp_model = POWERPC_EXCP_970;
5847 pcc->bus_model = PPC_FLAGS_INPUT_970;
5848 pcc->bfd_mach = bfd_mach_ppc64;
5849 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5850 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5851 POWERPC_FLAG_BUS_CLK;
5852 pcc->l1_dcache_size = 0x8000;
5853 pcc->l1_icache_size = 0x10000;
5854 }
5855
5856 static void init_proc_power5plus(CPUPPCState *env)
5857 {
5858 /* Common Registers */
5859 init_proc_book3s_common(env);
5860 register_sdr1_sprs(env);
5861 register_book3s_dbg_sprs(env);
5862
5863 /* POWER5+ Specific Registers */
5864 register_970_hid_sprs(env);
5865 register_970_hior_sprs(env);
5866 register_low_BATs(env);
5867 register_970_pmu_sup_sprs(env);
5868 register_970_pmu_user_sprs(env);
5869 register_power5p_common_sprs(env);
5870 register_power5p_lpar_sprs(env);
5871 register_power5p_ear_sprs(env);
5872 register_power5p_tb_sprs(env);
5873
5874 /* env variables */
5875 env->dcache_line_size = 128;
5876 env->icache_line_size = 128;
5877
5878 /* Allocate hardware IRQ controller */
5879 init_excp_970(env);
5880 ppc970_irq_init(env_archcpu(env));
5881 }
5882
5883 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
5884 {
5885 DeviceClass *dc = DEVICE_CLASS(oc);
5886 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5887
5888 dc->fw_name = "PowerPC,POWER5";
5889 dc->desc = "POWER5+";
5890 pcc->init_proc = init_proc_power5plus;
5891 pcc->check_pow = check_pow_970;
5892 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5893 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5894 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5895 PPC_FLOAT_STFIWX |
5896 PPC_FLOAT_EXT |
5897 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5898 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5899 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5900 PPC_64B |
5901 PPC_POPCNTB |
5902 PPC_SEGMENT_64B | PPC_SLBI;
5903 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
5904 pcc->msr_mask = (1ull << MSR_SF) |
5905 (1ull << MSR_VR) |
5906 (1ull << MSR_POW) |
5907 (1ull << MSR_EE) |
5908 (1ull << MSR_PR) |
5909 (1ull << MSR_FP) |
5910 (1ull << MSR_ME) |
5911 (1ull << MSR_FE0) |
5912 (1ull << MSR_SE) |
5913 (1ull << MSR_DE) |
5914 (1ull << MSR_FE1) |
5915 (1ull << MSR_IR) |
5916 (1ull << MSR_DR) |
5917 (1ull << MSR_PMM) |
5918 (1ull << MSR_RI);
5919 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
5920 LPCR_RMI | LPCR_HDICE;
5921 pcc->mmu_model = POWERPC_MMU_2_03;
5922 #if defined(CONFIG_SOFTMMU)
5923 pcc->hash64_opts = &ppc_hash64_opts_basic;
5924 pcc->lrg_decr_bits = 32;
5925 #endif
5926 pcc->excp_model = POWERPC_EXCP_970;
5927 pcc->bus_model = PPC_FLAGS_INPUT_970;
5928 pcc->bfd_mach = bfd_mach_ppc64;
5929 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5930 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5931 POWERPC_FLAG_BUS_CLK;
5932 pcc->l1_dcache_size = 0x8000;
5933 pcc->l1_icache_size = 0x10000;
5934 }
5935
5936 static void init_proc_POWER7(CPUPPCState *env)
5937 {
5938 /* Common Registers */
5939 init_proc_book3s_common(env);
5940 register_sdr1_sprs(env);
5941 register_book3s_dbg_sprs(env);
5942
5943 /* POWER7 Specific Registers */
5944 register_book3s_ids_sprs(env);
5945 register_rmor_sprs(env);
5946 register_amr_sprs(env);
5947 register_book3s_purr_sprs(env);
5948 register_power5p_common_sprs(env);
5949 register_power5p_lpar_sprs(env);
5950 register_power5p_ear_sprs(env);
5951 register_power5p_tb_sprs(env);
5952 register_power6_common_sprs(env);
5953 register_power6_dbg_sprs(env);
5954 register_power7_book4_sprs(env);
5955
5956 /* env variables */
5957 env->dcache_line_size = 128;
5958 env->icache_line_size = 128;
5959
5960 /* Allocate hardware IRQ controller */
5961 init_excp_POWER7(env);
5962 ppcPOWER7_irq_init(env_archcpu(env));
5963 }
5964
5965 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
5966 {
5967 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
5968 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
5969
5970 if (!best) {
5971 if (base == CPU_POWERPC_POWER7_BASE) {
5972 return true;
5973 }
5974 if (base == CPU_POWERPC_POWER7P_BASE) {
5975 return true;
5976 }
5977 }
5978
5979 if (base != pcc_base) {
5980 return false;
5981 }
5982
5983 return true;
5984 }
5985
5986 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
5987 {
5988 DeviceClass *dc = DEVICE_CLASS(oc);
5989 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5990
5991 dc->fw_name = "PowerPC,POWER7";
5992 dc->desc = "POWER7";
5993 pcc->pvr_match = ppc_pvr_match_power7;
5994 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
5995 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
5996 pcc->init_proc = init_proc_POWER7;
5997 pcc->check_pow = check_pow_nocheck;
5998 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
5999 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6000 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6001 PPC_FLOAT_FRSQRTES |
6002 PPC_FLOAT_STFIWX |
6003 PPC_FLOAT_EXT |
6004 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6005 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6006 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6007 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6008 PPC_SEGMENT_64B | PPC_SLBI |
6009 PPC_POPCNTB | PPC_POPCNTWD |
6010 PPC_CILDST;
6011 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
6012 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6013 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6014 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
6015 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
6016 pcc->msr_mask = (1ull << MSR_SF) |
6017 (1ull << MSR_VR) |
6018 (1ull << MSR_VSX) |
6019 (1ull << MSR_EE) |
6020 (1ull << MSR_PR) |
6021 (1ull << MSR_FP) |
6022 (1ull << MSR_ME) |
6023 (1ull << MSR_FE0) |
6024 (1ull << MSR_SE) |
6025 (1ull << MSR_DE) |
6026 (1ull << MSR_FE1) |
6027 (1ull << MSR_IR) |
6028 (1ull << MSR_DR) |
6029 (1ull << MSR_PMM) |
6030 (1ull << MSR_RI) |
6031 (1ull << MSR_LE);
6032 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6033 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6034 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6035 LPCR_MER | LPCR_TC |
6036 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6037 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6038 pcc->mmu_model = POWERPC_MMU_2_06;
6039 #if defined(CONFIG_SOFTMMU)
6040 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6041 pcc->lrg_decr_bits = 32;
6042 #endif
6043 pcc->excp_model = POWERPC_EXCP_POWER7;
6044 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6045 pcc->bfd_mach = bfd_mach_ppc64;
6046 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6047 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6048 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6049 POWERPC_FLAG_VSX;
6050 pcc->l1_dcache_size = 0x8000;
6051 pcc->l1_icache_size = 0x8000;
6052 }
6053
6054 static void init_proc_POWER8(CPUPPCState *env)
6055 {
6056 /* Common Registers */
6057 init_proc_book3s_common(env);
6058 register_sdr1_sprs(env);
6059 register_book3s_207_dbg_sprs(env);
6060
6061 /* Common TCG PMU */
6062 init_tcg_pmu_power8(env);
6063
6064 /* POWER8 Specific Registers */
6065 register_book3s_ids_sprs(env);
6066 register_rmor_sprs(env);
6067 register_amr_sprs(env);
6068 register_iamr_sprs(env);
6069 register_book3s_purr_sprs(env);
6070 register_power5p_common_sprs(env);
6071 register_power5p_lpar_sprs(env);
6072 register_power5p_ear_sprs(env);
6073 register_power5p_tb_sprs(env);
6074 register_power6_common_sprs(env);
6075 register_power6_dbg_sprs(env);
6076 register_power8_tce_address_control_sprs(env);
6077 register_power8_ids_sprs(env);
6078 register_power8_ebb_sprs(env);
6079 register_power8_fscr_sprs(env);
6080 register_power8_pmu_sup_sprs(env);
6081 register_power8_pmu_user_sprs(env);
6082 register_power8_tm_sprs(env);
6083 register_power8_pspb_sprs(env);
6084 register_power8_dpdes_sprs(env);
6085 register_vtb_sprs(env);
6086 register_power8_ic_sprs(env);
6087 register_power8_book4_sprs(env);
6088 register_power8_rpr_sprs(env);
6089
6090 /* env variables */
6091 env->dcache_line_size = 128;
6092 env->icache_line_size = 128;
6093
6094 /* Allocate hardware IRQ controller */
6095 init_excp_POWER8(env);
6096 ppcPOWER7_irq_init(env_archcpu(env));
6097 }
6098
6099 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6100 {
6101 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6102 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6103
6104 if (!best) {
6105 if (base == CPU_POWERPC_POWER8_BASE) {
6106 return true;
6107 }
6108 if (base == CPU_POWERPC_POWER8E_BASE) {
6109 return true;
6110 }
6111 if (base == CPU_POWERPC_POWER8NVL_BASE) {
6112 return true;
6113 }
6114 }
6115 if (base != pcc_base) {
6116 return false;
6117 }
6118
6119 return true;
6120 }
6121
6122 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
6123 {
6124 DeviceClass *dc = DEVICE_CLASS(oc);
6125 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6126
6127 dc->fw_name = "PowerPC,POWER8";
6128 dc->desc = "POWER8";
6129 pcc->pvr_match = ppc_pvr_match_power8;
6130 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6131 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6132 pcc->init_proc = init_proc_POWER8;
6133 pcc->check_pow = check_pow_nocheck;
6134 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6135 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6136 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6137 PPC_FLOAT_FRSQRTES |
6138 PPC_FLOAT_STFIWX |
6139 PPC_FLOAT_EXT |
6140 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6141 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6142 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6143 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6144 PPC_SEGMENT_64B | PPC_SLBI |
6145 PPC_POPCNTB | PPC_POPCNTWD |
6146 PPC_CILDST;
6147 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6148 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6149 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6150 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6151 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6152 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6153 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
6154 PPC2_BCDA_ISA206;
6155 pcc->msr_mask = (1ull << MSR_SF) |
6156 (1ull << MSR_HV) |
6157 (1ull << MSR_TM) |
6158 (1ull << MSR_VR) |
6159 (1ull << MSR_VSX) |
6160 (1ull << MSR_EE) |
6161 (1ull << MSR_PR) |
6162 (1ull << MSR_FP) |
6163 (1ull << MSR_ME) |
6164 (1ull << MSR_FE0) |
6165 (1ull << MSR_SE) |
6166 (1ull << MSR_DE) |
6167 (1ull << MSR_FE1) |
6168 (1ull << MSR_IR) |
6169 (1ull << MSR_DR) |
6170 (1ull << MSR_PMM) |
6171 (1ull << MSR_RI) |
6172 (1ull << MSR_TS0) |
6173 (1ull << MSR_TS1) |
6174 (1ull << MSR_LE);
6175 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6176 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6177 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6178 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6179 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6180 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6181 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6182 pcc->mmu_model = POWERPC_MMU_2_07;
6183 #if defined(CONFIG_SOFTMMU)
6184 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6185 pcc->lrg_decr_bits = 32;
6186 pcc->n_host_threads = 8;
6187 #endif
6188 pcc->excp_model = POWERPC_EXCP_POWER8;
6189 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6190 pcc->bfd_mach = bfd_mach_ppc64;
6191 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6192 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6193 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6194 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6195 pcc->l1_dcache_size = 0x8000;
6196 pcc->l1_icache_size = 0x8000;
6197 }
6198
6199 #ifdef CONFIG_SOFTMMU
6200 /*
6201 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6202 * Encoded as array of int_32s in the form:
6203 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6204 * x -> AP encoding
6205 * y -> radix mode supported page size (encoded as a shift)
6206 */
6207 static struct ppc_radix_page_info POWER9_radix_page_info = {
6208 .count = 4,
6209 .entries = {
6210 0x0000000c, /* 4K - enc: 0x0 */
6211 0xa0000010, /* 64K - enc: 0x5 */
6212 0x20000015, /* 2M - enc: 0x1 */
6213 0x4000001e /* 1G - enc: 0x2 */
6214 }
6215 };
6216 #endif /* CONFIG_SOFTMMU */
6217
6218 static void init_proc_POWER9(CPUPPCState *env)
6219 {
6220 /* Common Registers */
6221 init_proc_book3s_common(env);
6222 register_book3s_207_dbg_sprs(env);
6223
6224 /* Common TCG PMU */
6225 init_tcg_pmu_power8(env);
6226
6227 /* POWER8 Specific Registers */
6228 register_book3s_ids_sprs(env);
6229 register_amr_sprs(env);
6230 register_iamr_sprs(env);
6231 register_book3s_purr_sprs(env);
6232 register_power5p_common_sprs(env);
6233 register_power5p_lpar_sprs(env);
6234 register_power5p_ear_sprs(env);
6235 register_power5p_tb_sprs(env);
6236 register_power6_common_sprs(env);
6237 register_power6_dbg_sprs(env);
6238 register_power8_tce_address_control_sprs(env);
6239 register_power8_ids_sprs(env);
6240 register_power8_ebb_sprs(env);
6241 register_power8_fscr_sprs(env);
6242 register_power8_pmu_sup_sprs(env);
6243 register_power8_pmu_user_sprs(env);
6244 register_power8_tm_sprs(env);
6245 register_power8_pspb_sprs(env);
6246 register_power8_dpdes_sprs(env);
6247 register_vtb_sprs(env);
6248 register_power8_ic_sprs(env);
6249 register_power8_book4_sprs(env);
6250 register_power8_rpr_sprs(env);
6251 register_power9_mmu_sprs(env);
6252
6253 /* POWER9 Specific registers */
6254 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6255 spr_read_generic, spr_write_generic,
6256 KVM_REG_PPC_TIDR, 0);
6257
6258 /* FIXME: Filter fields properly based on privilege level */
6259 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6260 spr_read_generic, spr_write_generic,
6261 KVM_REG_PPC_PSSCR, 0);
6262
6263 /* env variables */
6264 env->dcache_line_size = 128;
6265 env->icache_line_size = 128;
6266
6267 /* Allocate hardware IRQ controller */
6268 init_excp_POWER9(env);
6269 ppcPOWER9_irq_init(env_archcpu(env));
6270 }
6271
6272 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6273 {
6274 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6275 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6276
6277 if (!best) {
6278 if (base == CPU_POWERPC_POWER9_BASE) {
6279 return true;
6280 }
6281 }
6282
6283 if (base != pcc_base) {
6284 return false;
6285 }
6286
6287 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6288 /* Major DD version matches to power9_v1.0 and power9_v2.0 */
6289 return true;
6290 }
6291
6292 return false;
6293 }
6294
6295 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
6296 {
6297 DeviceClass *dc = DEVICE_CLASS(oc);
6298 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6299
6300 dc->fw_name = "PowerPC,POWER9";
6301 dc->desc = "POWER9";
6302 pcc->pvr_match = ppc_pvr_match_power9;
6303 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
6304 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
6305 PCR_COMPAT_2_05;
6306 pcc->init_proc = init_proc_POWER9;
6307 pcc->check_pow = check_pow_nocheck;
6308 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6309 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6310 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6311 PPC_FLOAT_FRSQRTES |
6312 PPC_FLOAT_STFIWX |
6313 PPC_FLOAT_EXT |
6314 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6315 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6316 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6317 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6318 PPC_SEGMENT_64B | PPC_SLBI |
6319 PPC_POPCNTB | PPC_POPCNTWD |
6320 PPC_CILDST;
6321 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6322 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6323 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6324 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6325 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6326 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6327 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC |
6328 PPC2_BCDA_ISA206;
6329 pcc->msr_mask = (1ull << MSR_SF) |
6330 (1ull << MSR_HV) |
6331 (1ull << MSR_TM) |
6332 (1ull << MSR_VR) |
6333 (1ull << MSR_VSX) |
6334 (1ull << MSR_EE) |
6335 (1ull << MSR_PR) |
6336 (1ull << MSR_FP) |
6337 (1ull << MSR_ME) |
6338 (1ull << MSR_FE0) |
6339 (1ull << MSR_SE) |
6340 (1ull << MSR_DE) |
6341 (1ull << MSR_FE1) |
6342 (1ull << MSR_IR) |
6343 (1ull << MSR_DR) |
6344 (1ull << MSR_PMM) |
6345 (1ull << MSR_RI) |
6346 (1ull << MSR_LE);
6347 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6348 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6349 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6350 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6351 LPCR_DEE | LPCR_OEE))
6352 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6353 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6354 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6355 pcc->mmu_model = POWERPC_MMU_3_00;
6356 #if defined(CONFIG_SOFTMMU)
6357 /* segment page size remain the same */
6358 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6359 pcc->radix_page_info = &POWER9_radix_page_info;
6360 pcc->lrg_decr_bits = 56;
6361 pcc->n_host_threads = 4;
6362 #endif
6363 pcc->excp_model = POWERPC_EXCP_POWER9;
6364 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6365 pcc->bfd_mach = bfd_mach_ppc64;
6366 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6367 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6368 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6369 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
6370 pcc->l1_dcache_size = 0x8000;
6371 pcc->l1_icache_size = 0x8000;
6372 }
6373
6374 #ifdef CONFIG_SOFTMMU
6375 /*
6376 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6377 * Encoded as array of int_32s in the form:
6378 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6379 * x -> AP encoding
6380 * y -> radix mode supported page size (encoded as a shift)
6381 */
6382 static struct ppc_radix_page_info POWER10_radix_page_info = {
6383 .count = 4,
6384 .entries = {
6385 0x0000000c, /* 4K - enc: 0x0 */
6386 0xa0000010, /* 64K - enc: 0x5 */
6387 0x20000015, /* 2M - enc: 0x1 */
6388 0x4000001e /* 1G - enc: 0x2 */
6389 }
6390 };
6391 #endif /* CONFIG_SOFTMMU */
6392
6393 static void init_proc_POWER10(CPUPPCState *env)
6394 {
6395 /* Common Registers */
6396 init_proc_book3s_common(env);
6397 register_book3s_207_dbg_sprs(env);
6398
6399 /* Common TCG PMU */
6400 init_tcg_pmu_power8(env);
6401
6402 /* POWER8 Specific Registers */
6403 register_book3s_ids_sprs(env);
6404 register_amr_sprs(env);
6405 register_iamr_sprs(env);
6406 register_book3s_purr_sprs(env);
6407 register_power5p_common_sprs(env);
6408 register_power5p_lpar_sprs(env);
6409 register_power5p_ear_sprs(env);
6410 register_power5p_tb_sprs(env);
6411 register_power6_common_sprs(env);
6412 register_power6_dbg_sprs(env);
6413 register_power8_tce_address_control_sprs(env);
6414 register_power8_ids_sprs(env);
6415 register_power8_ebb_sprs(env);
6416 register_power8_fscr_sprs(env);
6417 register_power8_pmu_sup_sprs(env);
6418 register_power8_pmu_user_sprs(env);
6419 register_power8_tm_sprs(env);
6420 register_power8_pspb_sprs(env);
6421 register_power8_dpdes_sprs(env);
6422 register_vtb_sprs(env);
6423 register_power8_ic_sprs(env);
6424 register_power8_book4_sprs(env);
6425 register_power8_rpr_sprs(env);
6426 register_power9_mmu_sprs(env);
6427 register_power10_hash_sprs(env);
6428 register_power10_dexcr_sprs(env);
6429
6430 /* FIXME: Filter fields properly based on privilege level */
6431 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6432 spr_read_generic, spr_write_generic,
6433 KVM_REG_PPC_PSSCR, 0);
6434
6435 /* env variables */
6436 env->dcache_line_size = 128;
6437 env->icache_line_size = 128;
6438
6439 /* Allocate hardware IRQ controller */
6440 init_excp_POWER10(env);
6441 ppcPOWER9_irq_init(env_archcpu(env));
6442 }
6443
6444 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6445 {
6446 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6447 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6448
6449 if (!best) {
6450 if (base == CPU_POWERPC_POWER10_BASE) {
6451 return true;
6452 }
6453 }
6454
6455 if (base != pcc_base) {
6456 return false;
6457 }
6458
6459 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6460 /* Major DD version matches to power10_v1.0 and power10_v2.0 */
6461 return true;
6462 }
6463
6464 return false;
6465 }
6466
6467 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
6468 {
6469 DeviceClass *dc = DEVICE_CLASS(oc);
6470 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6471
6472 dc->fw_name = "PowerPC,POWER10";
6473 dc->desc = "POWER10";
6474 pcc->pvr_match = ppc_pvr_match_power10;
6475 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
6476 PCR_COMPAT_3_00;
6477 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
6478 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6479 pcc->init_proc = init_proc_POWER10;
6480 pcc->check_pow = check_pow_nocheck;
6481 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6482 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6483 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6484 PPC_FLOAT_FRSQRTES |
6485 PPC_FLOAT_STFIWX |
6486 PPC_FLOAT_EXT |
6487 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6488 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6489 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6490 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6491 PPC_SEGMENT_64B | PPC_SLBI |
6492 PPC_POPCNTB | PPC_POPCNTWD |
6493 PPC_CILDST;
6494 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6495 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6496 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6497 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6498 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6499 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6500 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
6501 PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
6502 pcc->msr_mask = (1ull << MSR_SF) |
6503 (1ull << MSR_HV) |
6504 (1ull << MSR_TM) |
6505 (1ull << MSR_VR) |
6506 (1ull << MSR_VSX) |
6507 (1ull << MSR_EE) |
6508 (1ull << MSR_PR) |
6509 (1ull << MSR_FP) |
6510 (1ull << MSR_ME) |
6511 (1ull << MSR_FE0) |
6512 (1ull << MSR_SE) |
6513 (1ull << MSR_DE) |
6514 (1ull << MSR_FE1) |
6515 (1ull << MSR_IR) |
6516 (1ull << MSR_DR) |
6517 (1ull << MSR_PMM) |
6518 (1ull << MSR_RI) |
6519 (1ull << MSR_LE);
6520 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6521 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6522 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6523 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6524 LPCR_DEE | LPCR_OEE))
6525 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6526 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6527 /* DD2 adds an extra HAIL bit */
6528 pcc->lpcr_mask |= LPCR_HAIL;
6529
6530 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6531 pcc->mmu_model = POWERPC_MMU_3_00;
6532 #if defined(CONFIG_SOFTMMU)
6533 /* segment page size remain the same */
6534 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6535 pcc->radix_page_info = &POWER10_radix_page_info;
6536 pcc->lrg_decr_bits = 56;
6537 #endif
6538 pcc->excp_model = POWERPC_EXCP_POWER10;
6539 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6540 pcc->bfd_mach = bfd_mach_ppc64;
6541 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6542 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6543 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6544 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
6545 pcc->l1_dcache_size = 0x8000;
6546 pcc->l1_icache_size = 0x8000;
6547 }
6548
6549 #if !defined(CONFIG_USER_ONLY)
6550 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
6551 {
6552 CPUPPCState *env = &cpu->env;
6553
6554 cpu->vhyp = vhyp;
6555
6556 /*
6557 * With a virtual hypervisor mode we never allow the CPU to go
6558 * hypervisor mode itself
6559 */
6560 env->msr_mask &= ~MSR_HVB;
6561 }
6562
6563 #endif /* !defined(CONFIG_USER_ONLY) */
6564
6565 #endif /* defined(TARGET_PPC64) */
6566
6567 /*****************************************************************************/
6568 /* Generic CPU instantiation routine */
6569 static void init_ppc_proc(PowerPCCPU *cpu)
6570 {
6571 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6572 CPUPPCState *env = &cpu->env;
6573 #if !defined(CONFIG_USER_ONLY)
6574 int i;
6575
6576 /* Set all exception vectors to an invalid address */
6577 for (i = 0; i < POWERPC_EXCP_NB; i++) {
6578 env->excp_vectors[i] = (target_ulong)(-1ULL);
6579 }
6580 env->ivor_mask = 0x00000000;
6581 env->ivpr_mask = 0x00000000;
6582 /* Default MMU definitions */
6583 env->nb_BATs = 0;
6584 env->nb_tlb = 0;
6585 env->nb_ways = 0;
6586 env->tlb_type = TLB_NONE;
6587 #endif
6588 /* Register SPR common to all PowerPC implementations */
6589 register_generic_sprs(cpu);
6590
6591 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
6592 (*pcc->init_proc)(env);
6593
6594 #if !defined(CONFIG_USER_ONLY)
6595 ppc_gdb_gen_spr_xml(cpu);
6596 #endif
6597
6598 /* MSR bits & flags consistency checks */
6599 if (env->msr_mask & (1 << 25)) {
6600 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6601 case POWERPC_FLAG_SPE:
6602 case POWERPC_FLAG_VRE:
6603 break;
6604 default:
6605 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6606 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
6607 exit(1);
6608 }
6609 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6610 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6611 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
6612 exit(1);
6613 }
6614 if (env->msr_mask & (1 << 17)) {
6615 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6616 case POWERPC_FLAG_TGPR:
6617 case POWERPC_FLAG_CE:
6618 break;
6619 default:
6620 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6621 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
6622 exit(1);
6623 }
6624 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6625 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6626 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
6627 exit(1);
6628 }
6629 if (env->msr_mask & (1 << 10)) {
6630 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6631 POWERPC_FLAG_UBLE)) {
6632 case POWERPC_FLAG_SE:
6633 case POWERPC_FLAG_DWE:
6634 case POWERPC_FLAG_UBLE:
6635 break;
6636 default:
6637 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6638 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6639 "POWERPC_FLAG_UBLE\n");
6640 exit(1);
6641 }
6642 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6643 POWERPC_FLAG_UBLE)) {
6644 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6645 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6646 "POWERPC_FLAG_UBLE\n");
6647 exit(1);
6648 }
6649 if (env->msr_mask & (1 << 9)) {
6650 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6651 case POWERPC_FLAG_BE:
6652 case POWERPC_FLAG_DE:
6653 break;
6654 default:
6655 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6656 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6657 exit(1);
6658 }
6659 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6660 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6661 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6662 exit(1);
6663 }
6664 if (env->msr_mask & (1 << 2)) {
6665 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6666 case POWERPC_FLAG_PX:
6667 case POWERPC_FLAG_PMM:
6668 break;
6669 default:
6670 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6671 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6672 exit(1);
6673 }
6674 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6675 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6676 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6677 exit(1);
6678 }
6679 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
6680 fprintf(stderr, "PowerPC flags inconsistency\n"
6681 "Should define the time-base and decrementer clock source\n");
6682 exit(1);
6683 }
6684 /* Allocate TLBs buffer when needed */
6685 #if !defined(CONFIG_USER_ONLY)
6686 if (env->nb_tlb != 0) {
6687 int nb_tlb = env->nb_tlb;
6688 if (env->id_tlbs != 0) {
6689 nb_tlb *= 2;
6690 }
6691 switch (env->tlb_type) {
6692 case TLB_6XX:
6693 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
6694 break;
6695 case TLB_EMB:
6696 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
6697 break;
6698 case TLB_MAS:
6699 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
6700 break;
6701 }
6702 /* Pre-compute some useful values */
6703 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6704 }
6705 #endif
6706 if (env->check_pow == NULL) {
6707 warn_report("no power management check handler registered."
6708 " Attempt QEMU to crash very soon !");
6709 }
6710 }
6711
6712
6713 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
6714 {
6715 CPUState *cs = CPU(dev);
6716 PowerPCCPU *cpu = POWERPC_CPU(dev);
6717 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6718 Error *local_err = NULL;
6719
6720 cpu_exec_realizefn(cs, &local_err);
6721 if (local_err != NULL) {
6722 error_propagate(errp, local_err);
6723 return;
6724 }
6725 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
6726 cpu->vcpu_id = cs->cpu_index;
6727 }
6728
6729 if (tcg_enabled()) {
6730 if (ppc_fixup_cpu(cpu) != 0) {
6731 error_setg(errp, "Unable to emulate selected CPU with TCG");
6732 goto unrealize;
6733 }
6734 }
6735
6736 create_ppc_opcodes(cpu, &local_err);
6737 if (local_err != NULL) {
6738 error_propagate(errp, local_err);
6739 goto unrealize;
6740 }
6741 init_ppc_proc(cpu);
6742
6743 ppc_gdb_init(cs, pcc);
6744 qemu_init_vcpu(cs);
6745
6746 pcc->parent_realize(dev, errp);
6747
6748 return;
6749
6750 unrealize:
6751 cpu_exec_unrealizefn(cs);
6752 }
6753
6754 static void ppc_cpu_unrealize(DeviceState *dev)
6755 {
6756 PowerPCCPU *cpu = POWERPC_CPU(dev);
6757 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6758
6759 pcc->parent_unrealize(dev);
6760
6761 cpu_remove_sync(CPU(cpu));
6762
6763 destroy_ppc_opcodes(cpu);
6764 }
6765
6766 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
6767 {
6768 ObjectClass *oc = (ObjectClass *)a;
6769 uint32_t pvr = *(uint32_t *)b;
6770 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6771
6772 /* -cpu host does a PVR lookup during construction */
6773 if (unlikely(strcmp(object_class_get_name(oc),
6774 TYPE_HOST_POWERPC_CPU) == 0)) {
6775 return -1;
6776 }
6777
6778 return pcc->pvr == pvr ? 0 : -1;
6779 }
6780
6781 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
6782 {
6783 GSList *list, *item;
6784 PowerPCCPUClass *pcc = NULL;
6785
6786 list = object_class_get_list(TYPE_POWERPC_CPU, false);
6787 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
6788 if (item != NULL) {
6789 pcc = POWERPC_CPU_CLASS(item->data);
6790 }
6791 g_slist_free(list);
6792
6793 return pcc;
6794 }
6795
6796 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
6797 {
6798 ObjectClass *oc = (ObjectClass *)a;
6799 uint32_t pvr = *(uint32_t *)b;
6800 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6801
6802 /* -cpu host does a PVR lookup during construction */
6803 if (unlikely(strcmp(object_class_get_name(oc),
6804 TYPE_HOST_POWERPC_CPU) == 0)) {
6805 return -1;
6806 }
6807
6808 if (pcc->pvr_match(pcc, pvr, true)) {
6809 return 0;
6810 }
6811
6812 return -1;
6813 }
6814
6815 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
6816 {
6817 GSList *list, *item;
6818 PowerPCCPUClass *pcc = NULL;
6819
6820 list = object_class_get_list(TYPE_POWERPC_CPU, true);
6821 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
6822 if (item != NULL) {
6823 pcc = POWERPC_CPU_CLASS(item->data);
6824 }
6825 g_slist_free(list);
6826
6827 return pcc;
6828 }
6829
6830 static const char *ppc_cpu_lookup_alias(const char *alias)
6831 {
6832 int ai;
6833
6834 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
6835 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
6836 return ppc_cpu_aliases[ai].model;
6837 }
6838 }
6839
6840 return NULL;
6841 }
6842
6843 ObjectClass *ppc_cpu_class_by_name(const char *name)
6844 {
6845 char *cpu_model, *typename;
6846 ObjectClass *oc;
6847 const char *p;
6848 unsigned long pvr;
6849
6850 /*
6851 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
6852 * 0x prefix if present)
6853 */
6854 if (!qemu_strtoul(name, &p, 16, &pvr)) {
6855 int len = p - name;
6856 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
6857 if ((len == 8) && (*p == '\0')) {
6858 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
6859 }
6860 }
6861
6862 /*
6863 * All ppc CPUs represent hardware that exists in the real world, i.e.: we
6864 * do not have a "max" CPU with all possible emulated features enabled.
6865 * Return the default CPU type for the machine because that has greater
6866 * chance of being useful as the "max" CPU.
6867 */
6868 #if !defined(CONFIG_USER_ONLY)
6869 if (strcmp(name, "max") == 0) {
6870 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
6871 if (mc) {
6872 return object_class_by_name(mc->default_cpu_type);
6873 }
6874 }
6875 #endif
6876
6877 cpu_model = g_ascii_strdown(name, -1);
6878 p = ppc_cpu_lookup_alias(cpu_model);
6879 if (p) {
6880 g_free(cpu_model);
6881 cpu_model = g_strdup(p);
6882 }
6883
6884 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
6885 oc = object_class_by_name(typename);
6886 g_free(typename);
6887 g_free(cpu_model);
6888
6889 return oc;
6890 }
6891
6892 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
6893 {
6894 ObjectClass *oc = OBJECT_CLASS(pcc);
6895
6896 while (oc && !object_class_is_abstract(oc)) {
6897 oc = object_class_get_parent(oc);
6898 }
6899 assert(oc);
6900
6901 return POWERPC_CPU_CLASS(oc);
6902 }
6903
6904 /* Sort by PVR, ordering special case "host" last. */
6905 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
6906 {
6907 ObjectClass *oc_a = (ObjectClass *)a;
6908 ObjectClass *oc_b = (ObjectClass *)b;
6909 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
6910 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
6911 const char *name_a = object_class_get_name(oc_a);
6912 const char *name_b = object_class_get_name(oc_b);
6913
6914 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
6915 return 1;
6916 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
6917 return -1;
6918 } else {
6919 /* Avoid an integer overflow during subtraction */
6920 if (pcc_a->pvr < pcc_b->pvr) {
6921 return -1;
6922 } else if (pcc_a->pvr > pcc_b->pvr) {
6923 return 1;
6924 } else {
6925 return 0;
6926 }
6927 }
6928 }
6929
6930 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
6931 {
6932 ObjectClass *oc = data;
6933 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6934 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
6935 const char *typename = object_class_get_name(oc);
6936 char *name;
6937 int i;
6938
6939 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
6940 return;
6941 }
6942
6943 name = g_strndup(typename,
6944 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
6945 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
6946 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
6947 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
6948 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
6949
6950 if (alias_oc != oc) {
6951 continue;
6952 }
6953 /*
6954 * If running with KVM, we might update the family alias later, so
6955 * avoid printing the wrong alias here and use "preferred" instead
6956 */
6957 if (strcmp(alias->alias, family->desc) == 0) {
6958 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
6959 alias->alias, family->desc);
6960 } else {
6961 qemu_printf("PowerPC %-16s (alias for %s)\n",
6962 alias->alias, name);
6963 }
6964 }
6965 g_free(name);
6966 }
6967
6968 void ppc_cpu_list(void)
6969 {
6970 GSList *list;
6971
6972 list = object_class_get_list(TYPE_POWERPC_CPU, false);
6973 list = g_slist_sort(list, ppc_cpu_list_compare);
6974 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
6975 g_slist_free(list);
6976
6977 #ifdef CONFIG_KVM
6978 qemu_printf("\n");
6979 qemu_printf("PowerPC %s\n", "host");
6980 #endif
6981 }
6982
6983 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
6984 {
6985 PowerPCCPU *cpu = POWERPC_CPU(cs);
6986
6987 cpu->env.nip = value;
6988 }
6989
6990 static vaddr ppc_cpu_get_pc(CPUState *cs)
6991 {
6992 PowerPCCPU *cpu = POWERPC_CPU(cs);
6993
6994 return cpu->env.nip;
6995 }
6996
6997 #ifdef CONFIG_TCG
6998 static void ppc_restore_state_to_opc(CPUState *cs,
6999 const TranslationBlock *tb,
7000 const uint64_t *data)
7001 {
7002 PowerPCCPU *cpu = POWERPC_CPU(cs);
7003
7004 cpu->env.nip = data[0];
7005 }
7006 #endif /* CONFIG_TCG */
7007
7008 static bool ppc_cpu_has_work(CPUState *cs)
7009 {
7010 return cs->interrupt_request & CPU_INTERRUPT_HARD;
7011 }
7012
7013 static void ppc_cpu_reset_hold(Object *obj)
7014 {
7015 CPUState *s = CPU(obj);
7016 PowerPCCPU *cpu = POWERPC_CPU(s);
7017 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7018 CPUPPCState *env = &cpu->env;
7019 target_ulong msr;
7020 int i;
7021
7022 if (pcc->parent_phases.hold) {
7023 pcc->parent_phases.hold(obj);
7024 }
7025
7026 msr = (target_ulong)0;
7027 msr |= (target_ulong)MSR_HVB;
7028 msr |= (target_ulong)1 << MSR_EP;
7029 #if defined(DO_SINGLE_STEP) && 0
7030 /* Single step trace mode */
7031 msr |= (target_ulong)1 << MSR_SE;
7032 msr |= (target_ulong)1 << MSR_BE;
7033 #endif
7034 #if defined(CONFIG_USER_ONLY)
7035 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7036 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7037 msr |= (target_ulong)1 << MSR_FE1;
7038 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7039 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7040 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7041 msr |= (target_ulong)1 << MSR_PR;
7042 #if defined(TARGET_PPC64)
7043 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7044 #endif
7045 #if !TARGET_BIG_ENDIAN
7046 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7047 if (!((env->msr_mask >> MSR_LE) & 1)) {
7048 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7049 exit(1);
7050 }
7051 #endif
7052 #endif
7053
7054 #if defined(TARGET_PPC64)
7055 if (mmu_is_64bit(env->mmu_model)) {
7056 msr |= (1ULL << MSR_SF);
7057 }
7058 #endif
7059
7060 hreg_store_msr(env, msr, 1);
7061
7062 #if !defined(CONFIG_USER_ONLY)
7063 env->nip = env->hreset_vector | env->excp_prefix;
7064
7065 if (tcg_enabled()) {
7066 if (env->mmu_model != POWERPC_MMU_REAL) {
7067 ppc_tlb_invalidate_all(env);
7068 }
7069 pmu_update_summaries(env);
7070 }
7071
7072 /* clean any pending stop state */
7073 env->resume_as_sreset = 0;
7074 #endif
7075 hreg_compute_hflags(env);
7076 env->reserve_addr = (target_ulong)-1ULL;
7077 /* Be sure no exception or interrupt is pending */
7078 env->pending_interrupts = 0;
7079 s->exception_index = POWERPC_EXCP_NONE;
7080 env->error_code = 0;
7081 ppc_irq_reset(cpu);
7082
7083 /* tininess for underflow is detected before rounding */
7084 set_float_detect_tininess(float_tininess_before_rounding,
7085 &env->fp_status);
7086
7087 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7088 ppc_spr_t *spr = &env->spr_cb[i];
7089
7090 if (!spr->name) {
7091 continue;
7092 }
7093 env->spr[i] = spr->default_value;
7094 }
7095 }
7096
7097 #ifndef CONFIG_USER_ONLY
7098
7099 static bool ppc_cpu_is_big_endian(CPUState *cs)
7100 {
7101 PowerPCCPU *cpu = POWERPC_CPU(cs);
7102 CPUPPCState *env = &cpu->env;
7103
7104 cpu_synchronize_state(cs);
7105
7106 return !FIELD_EX64(env->msr, MSR, LE);
7107 }
7108
7109 #ifdef CONFIG_TCG
7110 static void ppc_cpu_exec_enter(CPUState *cs)
7111 {
7112 PowerPCCPU *cpu = POWERPC_CPU(cs);
7113
7114 if (cpu->vhyp) {
7115 PPCVirtualHypervisorClass *vhc =
7116 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7117 vhc->cpu_exec_enter(cpu->vhyp, cpu);
7118 }
7119 }
7120
7121 static void ppc_cpu_exec_exit(CPUState *cs)
7122 {
7123 PowerPCCPU *cpu = POWERPC_CPU(cs);
7124
7125 if (cpu->vhyp) {
7126 PPCVirtualHypervisorClass *vhc =
7127 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7128 vhc->cpu_exec_exit(cpu->vhyp, cpu);
7129 }
7130 }
7131 #endif /* CONFIG_TCG */
7132
7133 #endif /* !CONFIG_USER_ONLY */
7134
7135 static void ppc_cpu_instance_init(Object *obj)
7136 {
7137 PowerPCCPU *cpu = POWERPC_CPU(obj);
7138 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7139 CPUPPCState *env = &cpu->env;
7140
7141 cpu_set_cpustate_pointers(cpu);
7142 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7143
7144 env->msr_mask = pcc->msr_mask;
7145 env->mmu_model = pcc->mmu_model;
7146 env->excp_model = pcc->excp_model;
7147 env->bus_model = pcc->bus_model;
7148 env->insns_flags = pcc->insns_flags;
7149 env->insns_flags2 = pcc->insns_flags2;
7150 env->flags = pcc->flags;
7151 env->bfd_mach = pcc->bfd_mach;
7152 env->check_pow = pcc->check_pow;
7153
7154 /*
7155 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7156 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7157 * mode support will remain, thus enforcing that we cannot use
7158 * priv. instructions in guest in PAPR mode. For 970 we currently
7159 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7160 * 970. If we ever want to support 970 HV mode, we'll have to add
7161 * a processor attribute of some sort.
7162 */
7163 #if !defined(CONFIG_USER_ONLY)
7164 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7165 #endif
7166
7167 ppc_hash64_init(cpu);
7168 }
7169
7170 static void ppc_cpu_instance_finalize(Object *obj)
7171 {
7172 PowerPCCPU *cpu = POWERPC_CPU(obj);
7173
7174 ppc_hash64_finalize(cpu);
7175 }
7176
7177 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
7178 {
7179 return pcc->pvr == pvr;
7180 }
7181
7182 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7183 {
7184 PowerPCCPU *cpu = POWERPC_CPU(cs);
7185 CPUPPCState *env = &cpu->env;
7186
7187 if ((env->hflags >> MSR_LE) & 1) {
7188 info->endian = BFD_ENDIAN_LITTLE;
7189 }
7190 info->mach = env->bfd_mach;
7191 if (!env->bfd_mach) {
7192 #ifdef TARGET_PPC64
7193 info->mach = bfd_mach_ppc64;
7194 #else
7195 info->mach = bfd_mach_ppc;
7196 #endif
7197 }
7198
7199 info->cap_arch = CS_ARCH_PPC;
7200 #ifdef TARGET_PPC64
7201 info->cap_mode = CS_MODE_64;
7202 #endif
7203 }
7204
7205 static Property ppc_cpu_properties[] = {
7206 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
7207 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
7208 false),
7209 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
7210 false),
7211 DEFINE_PROP_END_OF_LIST(),
7212 };
7213
7214 #ifndef CONFIG_USER_ONLY
7215 #include "hw/core/sysemu-cpu-ops.h"
7216
7217 static const struct SysemuCPUOps ppc_sysemu_ops = {
7218 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7219 .write_elf32_note = ppc32_cpu_write_elf32_note,
7220 .write_elf64_note = ppc64_cpu_write_elf64_note,
7221 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7222 .legacy_vmsd = &vmstate_ppc_cpu,
7223 };
7224 #endif
7225
7226 #ifdef CONFIG_TCG
7227 #include "hw/core/tcg-cpu-ops.h"
7228
7229 static const struct TCGCPUOps ppc_tcg_ops = {
7230 .initialize = ppc_translate_init,
7231 .restore_state_to_opc = ppc_restore_state_to_opc,
7232
7233 #ifdef CONFIG_USER_ONLY
7234 .record_sigsegv = ppc_cpu_record_sigsegv,
7235 #else
7236 .tlb_fill = ppc_cpu_tlb_fill,
7237 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7238 .do_interrupt = ppc_cpu_do_interrupt,
7239 .cpu_exec_enter = ppc_cpu_exec_enter,
7240 .cpu_exec_exit = ppc_cpu_exec_exit,
7241 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7242 #endif /* !CONFIG_USER_ONLY */
7243 };
7244 #endif /* CONFIG_TCG */
7245
7246 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
7247 {
7248 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7249 CPUClass *cc = CPU_CLASS(oc);
7250 DeviceClass *dc = DEVICE_CLASS(oc);
7251 ResettableClass *rc = RESETTABLE_CLASS(oc);
7252
7253 device_class_set_parent_realize(dc, ppc_cpu_realize,
7254 &pcc->parent_realize);
7255 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7256 &pcc->parent_unrealize);
7257 pcc->pvr_match = ppc_pvr_match_default;
7258 device_class_set_props(dc, ppc_cpu_properties);
7259
7260 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL,
7261 &pcc->parent_phases);
7262
7263 cc->class_by_name = ppc_cpu_class_by_name;
7264 cc->has_work = ppc_cpu_has_work;
7265 cc->dump_state = ppc_cpu_dump_state;
7266 cc->set_pc = ppc_cpu_set_pc;
7267 cc->get_pc = ppc_cpu_get_pc;
7268 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7269 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7270 #ifndef CONFIG_USER_ONLY
7271 cc->sysemu_ops = &ppc_sysemu_ops;
7272 #endif
7273
7274 cc->gdb_num_core_regs = 71;
7275 #ifndef CONFIG_USER_ONLY
7276 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
7277 #endif
7278 #ifdef USE_APPLE_GDB
7279 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7280 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7281 cc->gdb_num_core_regs = 71 + 32;
7282 #endif
7283
7284 cc->gdb_arch_name = ppc_gdb_arch_name;
7285 #if defined(TARGET_PPC64)
7286 cc->gdb_core_xml_file = "power64-core.xml";
7287 #else
7288 cc->gdb_core_xml_file = "power-core.xml";
7289 #endif
7290 cc->disas_set_info = ppc_disas_set_info;
7291
7292 dc->fw_name = "PowerPC,UNKNOWN";
7293
7294 #ifdef CONFIG_TCG
7295 cc->tcg_ops = &ppc_tcg_ops;
7296 #endif /* CONFIG_TCG */
7297 }
7298
7299 static const TypeInfo ppc_cpu_type_info = {
7300 .name = TYPE_POWERPC_CPU,
7301 .parent = TYPE_CPU,
7302 .instance_size = sizeof(PowerPCCPU),
7303 .instance_align = __alignof__(PowerPCCPU),
7304 .instance_init = ppc_cpu_instance_init,
7305 .instance_finalize = ppc_cpu_instance_finalize,
7306 .abstract = true,
7307 .class_size = sizeof(PowerPCCPUClass),
7308 .class_init = ppc_cpu_class_init,
7309 };
7310
7311 #ifndef CONFIG_USER_ONLY
7312 static const TypeInfo ppc_vhyp_type_info = {
7313 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7314 .parent = TYPE_INTERFACE,
7315 .class_size = sizeof(PPCVirtualHypervisorClass),
7316 };
7317 #endif
7318
7319 static void ppc_cpu_register_types(void)
7320 {
7321 type_register_static(&ppc_cpu_type_info);
7322 #ifndef CONFIG_USER_ONLY
7323 type_register_static(&ppc_vhyp_type_info);
7324 #endif
7325 }
7326
7327 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7328 {
7329 #define RGPL 4
7330 #define RFPL 4
7331
7332 PowerPCCPU *cpu = POWERPC_CPU(cs);
7333 CPUPPCState *env = &cpu->env;
7334 int i;
7335
7336 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7337 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7338 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7339 cs->cpu_index);
7340 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7341 "%08x iidx %d didx %d\n",
7342 env->msr, env->spr[SPR_HID0], env->hflags,
7343 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
7344 #if !defined(CONFIG_USER_ONLY)
7345 if (env->tb_env) {
7346 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7347 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
7348 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
7349 }
7350 #else
7351 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
7352 cpu_ppc_load_tbl(env));
7353 #endif
7354 for (i = 0; i < 32; i++) {
7355 if ((i & (RGPL - 1)) == 0) {
7356 qemu_fprintf(f, "GPR%02d", i);
7357 }
7358 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7359 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7360 qemu_fprintf(f, "\n");
7361 }
7362 }
7363 qemu_fprintf(f, "CR ");
7364 for (i = 0; i < 8; i++)
7365 qemu_fprintf(f, "%01x", env->crf[i]);
7366 qemu_fprintf(f, " [");
7367 for (i = 0; i < 8; i++) {
7368 char a = '-';
7369 if (env->crf[i] & 0x08) {
7370 a = 'L';
7371 } else if (env->crf[i] & 0x04) {
7372 a = 'G';
7373 } else if (env->crf[i] & 0x02) {
7374 a = 'E';
7375 }
7376 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7377 }
7378 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7379 env->reserve_addr);
7380
7381 if (flags & CPU_DUMP_FPU) {
7382 for (i = 0; i < 32; i++) {
7383 if ((i & (RFPL - 1)) == 0) {
7384 qemu_fprintf(f, "FPR%02d", i);
7385 }
7386 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7387 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7388 qemu_fprintf(f, "\n");
7389 }
7390 }
7391 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7392 }
7393
7394 #if !defined(CONFIG_USER_ONLY)
7395 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7396 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7397 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7398 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7399
7400 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7401 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7402 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7403 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7404
7405 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7406 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7407 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7408 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7409
7410 switch (env->excp_model) {
7411 #if defined(TARGET_PPC64)
7412 case POWERPC_EXCP_POWER7:
7413 case POWERPC_EXCP_POWER8:
7414 case POWERPC_EXCP_POWER9:
7415 case POWERPC_EXCP_POWER10:
7416 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7417 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7418 break;
7419 #endif
7420 case POWERPC_EXCP_BOOKE:
7421 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7422 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7423 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7424 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7425
7426 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7427 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7428 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7429 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7430
7431 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7432 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7433 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7434 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7435
7436 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7437 " EPR " TARGET_FMT_lx "\n",
7438 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7439 env->spr[SPR_BOOKE_EPR]);
7440
7441 /* FSL-specific */
7442 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7443 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7444 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7445 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7446
7447 /*
7448 * IVORs are left out as they are large and do not change often --
7449 * they can be read with "p $ivor0", "p $ivor1", etc.
7450 */
7451 break;
7452 case POWERPC_EXCP_40x:
7453 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7454 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7455 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
7456 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
7457
7458 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
7459 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7460 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
7461 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
7462 break;
7463 default:
7464 break;
7465 }
7466
7467 #if defined(TARGET_PPC64)
7468 if (env->flags & POWERPC_FLAG_CFAR) {
7469 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7470 }
7471 #endif
7472
7473 if (env->spr_cb[SPR_LPCR].name) {
7474 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7475 }
7476
7477 switch (env->mmu_model) {
7478 case POWERPC_MMU_32B:
7479 case POWERPC_MMU_SOFT_6xx:
7480 #if defined(TARGET_PPC64)
7481 case POWERPC_MMU_64B:
7482 case POWERPC_MMU_2_03:
7483 case POWERPC_MMU_2_06:
7484 case POWERPC_MMU_2_07:
7485 case POWERPC_MMU_3_00:
7486 #endif
7487 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7488 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7489 }
7490 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7491 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7492 }
7493 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7494 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7495 break;
7496 case POWERPC_MMU_BOOKE206:
7497 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7498 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7499 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7500 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7501
7502 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7503 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7504 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7505 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7506
7507 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7508 " TLB1CFG " TARGET_FMT_lx "\n",
7509 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7510 env->spr[SPR_BOOKE_TLB1CFG]);
7511 break;
7512 default:
7513 break;
7514 }
7515 #endif
7516
7517 #undef RGPL
7518 #undef RFPL
7519 }
7520 type_init(ppc_cpu_register_types)
armbru's QEMU hackery