target/xtensa/core-sample_controller/core-isa.h

   1 /*
   2  * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
   3  *                              processor CORE configuration
   4  *
   5  *  See <xtensa/config/core.h>, which includes this file, for more details.
   6  */
   7
   8 /* Xtensa processor core configuration information.
   9
  10    Copyright (c) 1999-2016 Tensilica Inc.
  11
  12    Permission is hereby granted, free of charge, to any person obtaining
  13    a copy of this software and associated documentation files (the
  14    "Software"), to deal in the Software without restriction, including
  15    without limitation the rights to use, copy, modify, merge, publish,
  16    distribute, sublicense, and/or sell copies of the Software, and to
  17    permit persons to whom the Software is furnished to do so, subject to
  18    the following conditions:
  19
  20    The above copyright notice and this permission notice shall be included
  21    in all copies or substantial portions of the Software.
  22
  23    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  26    IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
  27    CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  28    TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  29    SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
  30
  31 #ifndef XTENSA_CORE_SAMPLE_CONTROLLER_CORE_ISA_H
  32 #define XTENSA_CORE_SAMPLE_CONTROLLER_CORE_ISA_H
  33
  34 /****************************************************************************
  35             Parameters Useful for Any Code, USER or PRIVILEGED
  36  ****************************************************************************/
  37
  38 /*
  39  *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
  40  *  configured, and a value of 0 otherwise.  These macros are always defined.
  41  */
  42
  43
  44 /*----------------------------------------------------------------------
  45                                 ISA
  46   ----------------------------------------------------------------------*/
  47
  48 #define XCHAL_HAVE_BE                   0       /* big-endian byte ordering */
  49 #define XCHAL_HAVE_WINDOWED             1       /* windowed registers option */
  50 #define XCHAL_NUM_AREGS                 32      /* num of physical addr regs */
  51 #define XCHAL_NUM_AREGS_LOG2            5       /* log2(XCHAL_NUM_AREGS) */
  52 #define XCHAL_MAX_INSTRUCTION_SIZE      3       /* max instr bytes (3..8) */
  53 #define XCHAL_HAVE_DEBUG                1       /* debug option */
  54 #define XCHAL_HAVE_DENSITY              1       /* 16-bit instructions */
  55 #define XCHAL_HAVE_LOOPS                0       /* zero-overhead loops */
  56 #define XCHAL_LOOP_BUFFER_SIZE          0       /* zero-ov. loop instr buffer size */
  57 #define XCHAL_HAVE_NSA                  1       /* NSA/NSAU instructions */
  58 #define XCHAL_HAVE_MINMAX               1       /* MIN/MAX instructions */
  59 #define XCHAL_HAVE_SEXT                 1       /* SEXT instruction */
  60 #define XCHAL_HAVE_DEPBITS              0       /* DEPBITS instruction */
  61 #define XCHAL_HAVE_CLAMPS               0       /* CLAMPS instruction */
  62 #define XCHAL_HAVE_MUL16                1       /* MUL16S/MUL16U instructions */
  63 #define XCHAL_HAVE_MUL32                1       /* MULL instruction */
  64 #define XCHAL_HAVE_MUL32_HIGH           0       /* MULUH/MULSH instructions */
  65 #define XCHAL_HAVE_DIV32                1       /* QUOS/QUOU/REMS/REMU instructions */
  66 #define XCHAL_HAVE_L32R                 1       /* L32R instruction */
  67 #define XCHAL_HAVE_ABSOLUTE_LITERALS    0       /* non-PC-rel (extended) L32R */
  68 #define XCHAL_HAVE_CONST16              0       /* CONST16 instruction */
  69 #define XCHAL_HAVE_ADDX                 1       /* ADDX#/SUBX# instructions */
  70 #define XCHAL_HAVE_EXCLUSIVE            0       /* L32EX/S32EX instructions */
  71 #define XCHAL_HAVE_WIDE_BRANCHES        0       /* B*.W18 or B*.W15 instr's */
  72 #define XCHAL_HAVE_PREDICTED_BRANCHES   0       /* B[EQ/EQZ/NE/NEZ]T instr's */
  73 #define XCHAL_HAVE_CALL4AND12           1       /* (obsolete option) */
  74 #define XCHAL_HAVE_ABS                  1       /* ABS instruction */
  75 /*#define XCHAL_HAVE_POPC               0*/     /* POPC instruction */
  76 /*#define XCHAL_HAVE_CRC                0*/     /* CRC instruction */
  77 #define XCHAL_HAVE_RELEASE_SYNC         1       /* L32AI/S32RI instructions */
  78 #define XCHAL_HAVE_S32C1I               1       /* S32C1I instruction */
  79 #define XCHAL_HAVE_SPECULATION          0       /* speculation */
  80 #define XCHAL_HAVE_FULL_RESET           1       /* all regs/state reset */
  81 #define XCHAL_NUM_CONTEXTS              1       /* */
  82 #define XCHAL_NUM_MISC_REGS             2       /* num of scratch regs (0..4) */
  83 #define XCHAL_HAVE_TAP_MASTER           0       /* JTAG TAP control instr's */
  84 #define XCHAL_HAVE_PRID                 1       /* processor ID register */
  85 #define XCHAL_HAVE_EXTERN_REGS          1       /* WER/RER instructions */
  86 #define XCHAL_HAVE_MX                   0       /* MX core (Tensilica internal) */
  87 #define XCHAL_HAVE_MP_INTERRUPTS        0       /* interrupt distributor port */
  88 #define XCHAL_HAVE_MP_RUNSTALL          0       /* core RunStall control port */
  89 #define XCHAL_HAVE_PSO                  0       /* Power Shut-Off */
  90 #define XCHAL_HAVE_PSO_CDM              0       /* core/debug/mem pwr domains */
  91 #define XCHAL_HAVE_PSO_FULL_RETENTION   0       /* all regs preserved on PSO */
  92 #define XCHAL_HAVE_THREADPTR            0       /* THREADPTR register */
  93 #define XCHAL_HAVE_BOOLEANS             0       /* boolean registers */
  94 #define XCHAL_HAVE_CP                   0       /* CPENABLE reg (coprocessor) */
  95 #define XCHAL_CP_MAXCFG                 0       /* max allowed cp id plus one */
  96 #define XCHAL_HAVE_MAC16                0       /* MAC16 package */
  97
  98 #define XCHAL_HAVE_FUSION               0       /* Fusion*/
  99 #define XCHAL_HAVE_FUSION_FP            0       /* Fusion FP option */
 100 #define XCHAL_HAVE_FUSION_LOW_POWER     0       /* Fusion Low Power option */
 101 #define XCHAL_HAVE_FUSION_AES           0       /* Fusion BLE/Wifi AES-128 CCM option */
 102 #define XCHAL_HAVE_FUSION_CONVENC       0       /* Fusion Conv Encode option */
 103 #define XCHAL_HAVE_FUSION_LFSR_CRC      0       /* Fusion LFSR-CRC option */
 104 #define XCHAL_HAVE_FUSION_BITOPS        0       /* Fusion Bit Operations Support option */
 105 #define XCHAL_HAVE_FUSION_AVS           0       /* Fusion AVS option */
 106 #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0      /* Fusion 16-bit Baseband option */
 107 #define XCHAL_HAVE_FUSION_VITERBI       0       /* Fusion Viterbi option */
 108 #define XCHAL_HAVE_FUSION_SOFTDEMAP     0       /* Fusion Soft Bit Demap option */
 109 #define XCHAL_HAVE_HIFIPRO              0       /* HiFiPro Audio Engine pkg */
 110 #define XCHAL_HAVE_HIFI4                0       /* HiFi4 Audio Engine pkg */
 111 #define XCHAL_HAVE_HIFI4_VFPU           0       /* HiFi4 Audio Engine VFPU option */
 112 #define XCHAL_HAVE_HIFI3                0       /* HiFi3 Audio Engine pkg */
 113 #define XCHAL_HAVE_HIFI3_VFPU           0       /* HiFi3 Audio Engine VFPU option */
 114 #define XCHAL_HAVE_HIFI2                0       /* HiFi2 Audio Engine pkg */
 115 #define XCHAL_HAVE_HIFI2EP              0       /* HiFi2EP */
 116 #define XCHAL_HAVE_HIFI_MINI            0
 117
 118
 119
 120 #define XCHAL_HAVE_VECTORFPU2005        0       /* vector floating-point pkg */
 121 #define XCHAL_HAVE_USER_DPFPU           0       /* user DP floating-point pkg */
 122 #define XCHAL_HAVE_USER_SPFPU           0       /* user DP floating-point pkg */
 123 #define XCHAL_HAVE_FP                   0       /* single prec floating point */
 124 #define XCHAL_HAVE_FP_DIV               0       /* FP with DIV instructions */
 125 #define XCHAL_HAVE_FP_RECIP             0       /* FP with RECIP instructions */
 126 #define XCHAL_HAVE_FP_SQRT              0       /* FP with SQRT instructions */
 127 #define XCHAL_HAVE_FP_RSQRT             0       /* FP with RSQRT instructions */
 128 #define XCHAL_HAVE_DFP                  0       /* double precision FP pkg */
 129 #define XCHAL_HAVE_DFP_DIV              0       /* DFP with DIV instructions */
 130 #define XCHAL_HAVE_DFP_RECIP            0       /* DFP with RECIP instructions*/
 131 #define XCHAL_HAVE_DFP_SQRT             0       /* DFP with SQRT instructions */
 132 #define XCHAL_HAVE_DFP_RSQRT            0       /* DFP with RSQRT instructions*/
 133 #define XCHAL_HAVE_DFP_ACCEL            0       /* double precision FP acceleration pkg */
 134 #define XCHAL_HAVE_DFP_accel            XCHAL_HAVE_DFP_ACCEL    /* for backward compatibility */
 135
 136 #define XCHAL_HAVE_DFPU_SINGLE_ONLY     0       /* DFPU Coprocessor, single precision only */
 137 #define XCHAL_HAVE_DFPU_SINGLE_DOUBLE   0       /* DFPU Coprocessor, single and double precision */
 138 #define XCHAL_HAVE_VECTRA1              0       /* Vectra I  pkg */
 139 #define XCHAL_HAVE_VECTRALX             0       /* Vectra LX pkg */
 140
 141 #define XCHAL_HAVE_FUSIONG              0       /* FusionG */
 142 #define XCHAL_HAVE_FUSIONG3             0       /* FusionG3 */
 143 #define XCHAL_HAVE_FUSIONG_SP_VFPU      0      /* sp_vfpu option on FusionG */
 144 #define XCHAL_HAVE_FUSIONG_DP_VFPU      0      /* dp_vfpu option on FusionG */
 145 #define XCHAL_FUSIONG_SIMD32            0     /* simd32 for FusionG */
 146
 147 #define XCHAL_HAVE_PDX                  0       /* PDX */
 148 #define XCHAL_PDX_SIMD32                0     /* simd32 for PDX */
 149 #define XCHAL_HAVE_PDX4                 0       /* PDX4 */
 150 #define XCHAL_HAVE_PDX8                 0       /* PDX8 */
 151 #define XCHAL_HAVE_PDX16                0       /* PDX16 */
 152
 153 #define XCHAL_HAVE_CONNXD2              0       /* ConnX D2 pkg */
 154 #define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0       /* ConnX D2 & Dual LoadStore Flix */
 155 #define XCHAL_HAVE_BBE16                0       /* ConnX BBE16 pkg */
 156 #define XCHAL_HAVE_BBE16_RSQRT          0       /* BBE16 & vector recip sqrt */
 157 #define XCHAL_HAVE_BBE16_VECDIV         0       /* BBE16 & vector divide */
 158 #define XCHAL_HAVE_BBE16_DESPREAD       0       /* BBE16 & despread */
 159 #define XCHAL_HAVE_BBENEP               0       /* ConnX BBENEP pkgs */
 160 #define XCHAL_HAVE_BBENEP_SP_VFPU       0      /* sp_vfpu option on BBE-EP */
 161 #define XCHAL_HAVE_BSP3                 0       /* ConnX BSP3 pkg */
 162 #define XCHAL_HAVE_BSP3_TRANSPOSE       0       /* BSP3 & transpose32x32 */
 163 #define XCHAL_HAVE_SSP16                0       /* ConnX SSP16 pkg */
 164 #define XCHAL_HAVE_SSP16_VITERBI        0       /* SSP16 & viterbi */
 165 #define XCHAL_HAVE_TURBO16              0       /* ConnX Turbo16 pkg */
 166 #define XCHAL_HAVE_BBP16                0       /* ConnX BBP16 pkg */
 167 #define XCHAL_HAVE_FLIX3                0       /* basic 3-way FLIX option */
 168 #define XCHAL_HAVE_GRIVPEP              0       /* General Release of IVPEP */
 169 #define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0       /* Histogram option on GRIVPEP */
 170
 171 #define XCHAL_HAVE_VISION               0     /* Vision P5/P6 */
 172 #define XCHAL_VISION_SIMD16             0     /* simd16 for Vision P5/P6 */
 173 #define XCHAL_VISION_TYPE               0     /* Vision P5, P6, or P3 */
 174 #define XCHAL_VISION_QUAD_MAC_TYPE      0     /* quad_mac option on Vision P6 */
 175 #define XCHAL_HAVE_VISION_HISTOGRAM     0     /* histogram option on Vision P5/P6 */
 176 #define XCHAL_HAVE_VISION_SP_VFPU       0     /* sp_vfpu option on Vision P5/P6 */
 177 #define XCHAL_HAVE_VISION_HP_VFPU       0     /* hp_vfpu option on Vision P6 */
 178
 179 /*----------------------------------------------------------------------
 180                                 MISC
 181   ----------------------------------------------------------------------*/
 182
 183 #define XCHAL_NUM_LOADSTORE_UNITS       1       /* load/store units */
 184 #define XCHAL_NUM_WRITEBUFFER_ENTRIES   4       /* size of write buffer */
 185 #define XCHAL_INST_FETCH_WIDTH          4       /* instr-fetch width in bytes */
 186 #define XCHAL_DATA_WIDTH                4       /* data width in bytes */
 187 #define XCHAL_DATA_PIPE_DELAY           1       /* d-side pipeline delay
 188                                                    (1 = 5-stage, 2 = 7-stage) */
 189 #define XCHAL_CLOCK_GATING_GLOBAL       1       /* global clock gating */
 190 #define XCHAL_CLOCK_GATING_FUNCUNIT     1       /* funct. unit clock gating */
 191 /*  In T1050, applies to selected core load and store instructions (see ISA): */
 192 #define XCHAL_UNALIGNED_LOAD_EXCEPTION  1       /* unaligned loads cause exc. */
 193 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1       /* unaligned stores cause exc.*/
 194 #define XCHAL_UNALIGNED_LOAD_HW         0       /* unaligned loads work in hw */
 195 #define XCHAL_UNALIGNED_STORE_HW        0       /* unaligned stores work in hw*/
 196
 197 #define XCHAL_SW_VERSION                1200004 /* sw version of this header */
 198
 199 #define XCHAL_CORE_ID                   "sample_controller"     /* alphanum core name
 200                                                    (CoreID) set in the Xtensa
 201                                                    Processor Generator */
 202
 203 #define XCHAL_BUILD_UNIQUE_ID           0x00064D47      /* 22-bit sw build ID */
 204
 205 /*
 206  *  These definitions describe the hardware targeted by this software.
 207  */
 208 #define XCHAL_HW_CONFIGID0              0xC280DAFE      /* ConfigID hi 32 bits*/
 209 #define XCHAL_HW_CONFIGID1              0x21064D47      /* ConfigID lo 32 bits*/
 210 #define XCHAL_HW_VERSION_NAME           "LX7.0.4"       /* full version name */
 211 #define XCHAL_HW_VERSION_MAJOR          2700    /* major ver# of targeted hw */
 212 #define XCHAL_HW_VERSION_MINOR          4       /* minor ver# of targeted hw */
 213 #define XCHAL_HW_VERSION                270004  /* major*100+minor */
 214 #define XCHAL_HW_REL_LX7                1
 215 #define XCHAL_HW_REL_LX7_0              1
 216 #define XCHAL_HW_REL_LX7_0_4            1
 217 #define XCHAL_HW_CONFIGID_RELIABLE      1
 218 /*  If software targets a *range* of hardware versions, these are the bounds: */
 219 #define XCHAL_HW_MIN_VERSION_MAJOR      2700    /* major v of earliest tgt hw */
 220 #define XCHAL_HW_MIN_VERSION_MINOR      4       /* minor v of earliest tgt hw */
 221 #define XCHAL_HW_MIN_VERSION            270004  /* earliest targeted hw */
 222 #define XCHAL_HW_MAX_VERSION_MAJOR      2700    /* major v of latest tgt hw */
 223 #define XCHAL_HW_MAX_VERSION_MINOR      4       /* minor v of latest tgt hw */
 224 #define XCHAL_HW_MAX_VERSION            270004  /* latest targeted hw */
 225
 226
 227 /*----------------------------------------------------------------------
 228                                 CACHE
 229   ----------------------------------------------------------------------*/
 230
 231 #define XCHAL_ICACHE_LINESIZE           4       /* I-cache line size in bytes */
 232 #define XCHAL_DCACHE_LINESIZE           4       /* D-cache line size in bytes */
 233 #define XCHAL_ICACHE_LINEWIDTH          2       /* log2(I line size in bytes) */
 234 #define XCHAL_DCACHE_LINEWIDTH          2       /* log2(D line size in bytes) */
 235
 236 #define XCHAL_ICACHE_SIZE               0       /* I-cache size in bytes or 0 */
 237 #define XCHAL_DCACHE_SIZE               0       /* D-cache size in bytes or 0 */
 238
 239 #define XCHAL_DCACHE_IS_WRITEBACK       0       /* writeback feature */
 240 #define XCHAL_DCACHE_IS_COHERENT        0       /* MP coherence feature */
 241
 242 #define XCHAL_HAVE_PREFETCH             0       /* PREFCTL register */
 243 #define XCHAL_HAVE_PREFETCH_L1          0       /* prefetch to L1 dcache */
 244 #define XCHAL_PREFETCH_CASTOUT_LINES    0       /* dcache pref. castout bufsz */
 245 #define XCHAL_PREFETCH_ENTRIES          0       /* cache prefetch entries */
 246 #define XCHAL_PREFETCH_BLOCK_ENTRIES    0       /* prefetch block streams */
 247 #define XCHAL_HAVE_CACHE_BLOCKOPS       0       /* block prefetch for caches */
 248 #define XCHAL_HAVE_ICACHE_TEST          0       /* Icache test instructions */
 249 #define XCHAL_HAVE_DCACHE_TEST          0       /* Dcache test instructions */
 250 #define XCHAL_HAVE_ICACHE_DYN_WAYS      0       /* Icache dynamic way support */
 251 #define XCHAL_HAVE_DCACHE_DYN_WAYS      0       /* Dcache dynamic way support */
 252
 253
 254
 255
 256 /****************************************************************************
 257     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
 258  ****************************************************************************/
 259
 260
 261 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
 262
 263 /*----------------------------------------------------------------------
 264                                 CACHE
 265   ----------------------------------------------------------------------*/
 266
 267 #define XCHAL_HAVE_PIF                  1       /* any outbound bus present */
 268
 269 #define XCHAL_HAVE_AXI                  0       /* AXI bus */
 270 #define XCHAL_HAVE_AXI_ECC              0       /* ECC on AXI bus */
 271 #define XCHAL_HAVE_ACELITE              0       /* ACELite bus */
 272
 273 #define XCHAL_HAVE_PIF_WR_RESP                  0       /* pif write response */
 274 #define XCHAL_HAVE_PIF_REQ_ATTR                 0       /* pif attribute */
 275
 276 /*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
 277
 278 /*  Number of cache sets in log2(lines per way):  */
 279 #define XCHAL_ICACHE_SETWIDTH           0
 280 #define XCHAL_DCACHE_SETWIDTH           0
 281
 282 /*  Cache set associativity (number of ways):  */
 283 #define XCHAL_ICACHE_WAYS               1
 284 #define XCHAL_DCACHE_WAYS               1
 285
 286 /*  Cache features:  */
 287 #define XCHAL_ICACHE_LINE_LOCKABLE      0
 288 #define XCHAL_DCACHE_LINE_LOCKABLE      0
 289 #define XCHAL_ICACHE_ECC_PARITY         0
 290 #define XCHAL_DCACHE_ECC_PARITY         0
 291
 292 /*  Cache access size in bytes (affects operation of SICW instruction):  */
 293 #define XCHAL_ICACHE_ACCESS_SIZE        1
 294 #define XCHAL_DCACHE_ACCESS_SIZE        1
 295
 296 #define XCHAL_DCACHE_BANKS              0       /* number of banks */
 297
 298 /*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
 299 #define XCHAL_CA_BITS                   4
 300
 301
 302 /*----------------------------------------------------------------------
 303                         INTERNAL I/D RAM/ROMs and XLMI
 304   ----------------------------------------------------------------------*/
 305 #define XCHAL_NUM_INSTROM               0       /* number of core instr. ROMs */
 306 #define XCHAL_NUM_INSTRAM               1       /* number of core instr. RAMs */
 307 #define XCHAL_NUM_DATAROM               0       /* number of core data ROMs */
 308 #define XCHAL_NUM_DATARAM               2       /* number of core data RAMs */
 309 #define XCHAL_NUM_URAM                  0       /* number of core unified RAMs*/
 310 #define XCHAL_NUM_XLMI                  0       /* number of core XLMI ports */
 311
 312 /*  Instruction RAM 0:  */
 313 #define XCHAL_INSTRAM0_VADDR            0x40000000      /* virtual address */
 314 #define XCHAL_INSTRAM0_PADDR            0x40000000      /* physical address */
 315 #define XCHAL_INSTRAM0_SIZE             131072  /* size in bytes */
 316 #define XCHAL_INSTRAM0_ECC_PARITY       0       /* ECC/parity type, 0=none */
 317 #define XCHAL_HAVE_INSTRAM0
 318 #define XCHAL_INSTRAM0_HAVE_IDMA        0       /* idma supported by this local memory */
 319
 320 /*  Data RAM 0:  */
 321 #define XCHAL_DATARAM0_VADDR            0x3FFE0000      /* virtual address */
 322 #define XCHAL_DATARAM0_PADDR            0x3FFE0000      /* physical address */
 323 #define XCHAL_DATARAM0_SIZE             131072  /* size in bytes */
 324 #define XCHAL_DATARAM0_ECC_PARITY       0       /* ECC/parity type, 0=none */
 325 #define XCHAL_DATARAM0_BANKS            1       /* number of banks */
 326 #define XCHAL_HAVE_DATARAM0
 327 #define XCHAL_DATARAM0_HAVE_IDMA        0       /* idma supported by this local memory */
 328
 329 /*  Data RAM 1:  */
 330 #define XCHAL_DATARAM1_VADDR            0x3FFC0000      /* virtual address */
 331 #define XCHAL_DATARAM1_PADDR            0x3FFC0000      /* physical address */
 332 #define XCHAL_DATARAM1_SIZE             131072  /* size in bytes */
 333 #define XCHAL_DATARAM1_ECC_PARITY       0       /* ECC/parity type, 0=none */
 334 #define XCHAL_DATARAM1_BANKS            1       /* number of banks */
 335 #define XCHAL_HAVE_DATARAM1
 336 #define XCHAL_DATARAM1_HAVE_IDMA        0       /* idma supported by this local memory */
 337
 338 #define XCHAL_HAVE_IDMA                 0
 339 #define XCHAL_HAVE_IDMA_TRANSPOSE       0
 340
 341 #define XCHAL_HAVE_IMEM_LOADSTORE       1       /* can load/store to IROM/IRAM*/
 342
 343
 344 /*----------------------------------------------------------------------
 345                         INTERRUPTS and TIMERS
 346   ----------------------------------------------------------------------*/
 347
 348 #define XCHAL_HAVE_INTERRUPTS           1       /* interrupt option */
 349 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS   1       /* med/high-pri. interrupts */
 350 #define XCHAL_HAVE_NMI                  1       /* non-maskable interrupt */
 351 #define XCHAL_HAVE_CCOUNT               1       /* CCOUNT reg. (timer option) */
 352 #define XCHAL_NUM_TIMERS                3       /* number of CCOMPAREn regs */
 353 #define XCHAL_NUM_INTERRUPTS            22      /* number of interrupts */
 354 #define XCHAL_NUM_INTERRUPTS_LOG2       5       /* ceil(log2(NUM_INTERRUPTS)) */
 355 #define XCHAL_NUM_EXTINTERRUPTS         17      /* num of external interrupts */
 356 #define XCHAL_NUM_INTLEVELS             6       /* number of interrupt levels
 357                                                    (not including level zero) */
 358 #define XCHAL_EXCM_LEVEL                3       /* level masked by PS.EXCM */
 359         /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
 360
 361 /*  Masks of interrupts at each interrupt level:  */
 362 #define XCHAL_INTLEVEL1_MASK            0x001F80FF
 363 #define XCHAL_INTLEVEL2_MASK            0x00000100
 364 #define XCHAL_INTLEVEL3_MASK            0x00200E00
 365 #define XCHAL_INTLEVEL4_MASK            0x00001000
 366 #define XCHAL_INTLEVEL5_MASK            0x00002000
 367 #define XCHAL_INTLEVEL6_MASK            0x00000000
 368 #define XCHAL_INTLEVEL7_MASK            0x00004000
 369
 370 /*  Masks of interrupts at each range 1..n of interrupt levels:  */
 371 #define XCHAL_INTLEVEL1_ANDBELOW_MASK   0x001F80FF
 372 #define XCHAL_INTLEVEL2_ANDBELOW_MASK   0x001F81FF
 373 #define XCHAL_INTLEVEL3_ANDBELOW_MASK   0x003F8FFF
 374 #define XCHAL_INTLEVEL4_ANDBELOW_MASK   0x003F9FFF
 375 #define XCHAL_INTLEVEL5_ANDBELOW_MASK   0x003FBFFF
 376 #define XCHAL_INTLEVEL6_ANDBELOW_MASK   0x003FBFFF
 377 #define XCHAL_INTLEVEL7_ANDBELOW_MASK   0x003FFFFF
 378
 379 /*  Level of each interrupt:  */
 380 #define XCHAL_INT0_LEVEL                1
 381 #define XCHAL_INT1_LEVEL                1
 382 #define XCHAL_INT2_LEVEL                1
 383 #define XCHAL_INT3_LEVEL                1
 384 #define XCHAL_INT4_LEVEL                1
 385 #define XCHAL_INT5_LEVEL                1
 386 #define XCHAL_INT6_LEVEL                1
 387 #define XCHAL_INT7_LEVEL                1
 388 #define XCHAL_INT8_LEVEL                2
 389 #define XCHAL_INT9_LEVEL                3
 390 #define XCHAL_INT10_LEVEL               3
 391 #define XCHAL_INT11_LEVEL               3
 392 #define XCHAL_INT12_LEVEL               4
 393 #define XCHAL_INT13_LEVEL               5
 394 #define XCHAL_INT14_LEVEL               7
 395 #define XCHAL_INT15_LEVEL               1
 396 #define XCHAL_INT16_LEVEL               1
 397 #define XCHAL_INT17_LEVEL               1
 398 #define XCHAL_INT18_LEVEL               1
 399 #define XCHAL_INT19_LEVEL               1
 400 #define XCHAL_INT20_LEVEL               1
 401 #define XCHAL_INT21_LEVEL               3
 402 #define XCHAL_DEBUGLEVEL                6       /* debug interrupt level */
 403 #define XCHAL_HAVE_DEBUG_EXTERN_INT     1       /* OCD external db interrupt */
 404 #define XCHAL_NMILEVEL                  7       /* NMI "level" (for use with
 405                                                    EXCSAVE/EPS/EPC_n, RFI n) */
 406
 407 /*  Type of each interrupt:  */
 408 #define XCHAL_INT0_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 409 #define XCHAL_INT1_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 410 #define XCHAL_INT2_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 411 #define XCHAL_INT3_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 412 #define XCHAL_INT4_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 413 #define XCHAL_INT5_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 414 #define XCHAL_INT6_TYPE         XTHAL_INTTYPE_TIMER
 415 #define XCHAL_INT7_TYPE         XTHAL_INTTYPE_SOFTWARE
 416 #define XCHAL_INT8_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 417 #define XCHAL_INT9_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 418 #define XCHAL_INT10_TYPE        XTHAL_INTTYPE_TIMER
 419 #define XCHAL_INT11_TYPE        XTHAL_INTTYPE_SOFTWARE
 420 #define XCHAL_INT12_TYPE        XTHAL_INTTYPE_EXTERN_LEVEL
 421 #define XCHAL_INT13_TYPE        XTHAL_INTTYPE_TIMER
 422 #define XCHAL_INT14_TYPE        XTHAL_INTTYPE_NMI
 423 #define XCHAL_INT15_TYPE        XTHAL_INTTYPE_EXTERN_EDGE
 424 #define XCHAL_INT16_TYPE        XTHAL_INTTYPE_EXTERN_EDGE
 425 #define XCHAL_INT17_TYPE        XTHAL_INTTYPE_EXTERN_EDGE
 426 #define XCHAL_INT18_TYPE        XTHAL_INTTYPE_EXTERN_EDGE
 427 #define XCHAL_INT19_TYPE        XTHAL_INTTYPE_EXTERN_EDGE
 428 #define XCHAL_INT20_TYPE        XTHAL_INTTYPE_EXTERN_EDGE
 429 #define XCHAL_INT21_TYPE        XTHAL_INTTYPE_EXTERN_EDGE
 430
 431 /*  Masks of interrupts for each type of interrupt:  */
 432 #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
 433 #define XCHAL_INTTYPE_MASK_SOFTWARE     0x00000880
 434 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE  0x003F8000
 435 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
 436 #define XCHAL_INTTYPE_MASK_TIMER        0x00002440
 437 #define XCHAL_INTTYPE_MASK_NMI          0x00004000
 438 #define XCHAL_INTTYPE_MASK_WRITE_ERROR  0x00000000
 439 #define XCHAL_INTTYPE_MASK_PROFILING    0x00000000
 440 #define XCHAL_INTTYPE_MASK_IDMA_DONE    0x00000000
 441 #define XCHAL_INTTYPE_MASK_IDMA_ERR     0x00000000
 442 #define XCHAL_INTTYPE_MASK_GS_ERR       0x00000000
 443
 444 /*  Interrupt numbers assigned to specific interrupt sources:  */
 445 #define XCHAL_TIMER0_INTERRUPT          6       /* CCOMPARE0 */
 446 #define XCHAL_TIMER1_INTERRUPT          10      /* CCOMPARE1 */
 447 #define XCHAL_TIMER2_INTERRUPT          13      /* CCOMPARE2 */
 448 #define XCHAL_TIMER3_INTERRUPT          XTHAL_TIMER_UNCONFIGURED
 449 #define XCHAL_NMI_INTERRUPT             14      /* non-maskable interrupt */
 450
 451 /*  Interrupt numbers for levels at which only one interrupt is configured:  */
 452 #define XCHAL_INTLEVEL2_NUM             8
 453 #define XCHAL_INTLEVEL4_NUM             12
 454 #define XCHAL_INTLEVEL5_NUM             13
 455 #define XCHAL_INTLEVEL7_NUM             14
 456 /*  (There are many interrupts each at level(s) 1, 3.)  */
 457
 458
 459 /*
 460  *  External interrupt mapping.
 461  *  These macros describe how Xtensa processor interrupt numbers
 462  *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
 463  *  map to external BInterrupt<n> pins, for those interrupts
 464  *  configured as external (level-triggered, edge-triggered, or NMI).
 465  *  See the Xtensa processor databook for more details.
 466  */
 467
 468 /*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
 469 #define XCHAL_EXTINT0_NUM               0       /* (intlevel 1) */
 470 #define XCHAL_EXTINT1_NUM               1       /* (intlevel 1) */
 471 #define XCHAL_EXTINT2_NUM               2       /* (intlevel 1) */
 472 #define XCHAL_EXTINT3_NUM               3       /* (intlevel 1) */
 473 #define XCHAL_EXTINT4_NUM               4       /* (intlevel 1) */
 474 #define XCHAL_EXTINT5_NUM               5       /* (intlevel 1) */
 475 #define XCHAL_EXTINT6_NUM               8       /* (intlevel 2) */
 476 #define XCHAL_EXTINT7_NUM               9       /* (intlevel 3) */
 477 #define XCHAL_EXTINT8_NUM               12      /* (intlevel 4) */
 478 #define XCHAL_EXTINT9_NUM               14      /* (intlevel 7) */
 479 #define XCHAL_EXTINT10_NUM              15      /* (intlevel 1) */
 480 #define XCHAL_EXTINT11_NUM              16      /* (intlevel 1) */
 481 #define XCHAL_EXTINT12_NUM              17      /* (intlevel 1) */
 482 #define XCHAL_EXTINT13_NUM              18      /* (intlevel 1) */
 483 #define XCHAL_EXTINT14_NUM              19      /* (intlevel 1) */
 484 #define XCHAL_EXTINT15_NUM              20      /* (intlevel 1) */
 485 #define XCHAL_EXTINT16_NUM              21      /* (intlevel 3) */
 486 /*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
 487 #define XCHAL_INT0_EXTNUM               0       /* (intlevel 1) */
 488 #define XCHAL_INT1_EXTNUM               1       /* (intlevel 1) */
 489 #define XCHAL_INT2_EXTNUM               2       /* (intlevel 1) */
 490 #define XCHAL_INT3_EXTNUM               3       /* (intlevel 1) */
 491 #define XCHAL_INT4_EXTNUM               4       /* (intlevel 1) */
 492 #define XCHAL_INT5_EXTNUM               5       /* (intlevel 1) */
 493 #define XCHAL_INT8_EXTNUM               6       /* (intlevel 2) */
 494 #define XCHAL_INT9_EXTNUM               7       /* (intlevel 3) */
 495 #define XCHAL_INT12_EXTNUM              8       /* (intlevel 4) */
 496 #define XCHAL_INT14_EXTNUM              9       /* (intlevel 7) */
 497 #define XCHAL_INT15_EXTNUM              10      /* (intlevel 1) */
 498 #define XCHAL_INT16_EXTNUM              11      /* (intlevel 1) */
 499 #define XCHAL_INT17_EXTNUM              12      /* (intlevel 1) */
 500 #define XCHAL_INT18_EXTNUM              13      /* (intlevel 1) */
 501 #define XCHAL_INT19_EXTNUM              14      /* (intlevel 1) */
 502 #define XCHAL_INT20_EXTNUM              15      /* (intlevel 1) */
 503 #define XCHAL_INT21_EXTNUM              16      /* (intlevel 3) */
 504
 505
 506 /*----------------------------------------------------------------------
 507                         EXCEPTIONS and VECTORS
 508   ----------------------------------------------------------------------*/
 509
 510 #define XCHAL_XEA_VERSION               2       /* Xtensa Exception Architecture
 511                                                    number: 1 == XEA1 (old)
 512                                                            2 == XEA2 (new)
 513                                                            0 == XEAX (extern) or TX */
 514 #define XCHAL_HAVE_XEA1                 0       /* Exception Architecture 1 */
 515 #define XCHAL_HAVE_XEA2                 1       /* Exception Architecture 2 */
 516 #define XCHAL_HAVE_XEAX                 0       /* External Exception Arch. */
 517 #define XCHAL_HAVE_EXCEPTIONS           1       /* exception option */
 518 #define XCHAL_HAVE_HALT                 0       /* halt architecture option */
 519 #define XCHAL_HAVE_BOOTLOADER           0       /* boot loader (for TX) */
 520 #define XCHAL_HAVE_MEM_ECC_PARITY       0       /* local memory ECC/parity */
 521 #define XCHAL_HAVE_VECTOR_SELECT        1       /* relocatable vectors */
 522 #define XCHAL_HAVE_VECBASE              1       /* relocatable vectors */
 523 #define XCHAL_VECBASE_RESET_VADDR       0x40000000  /* VECBASE reset value */
 524 #define XCHAL_VECBASE_RESET_PADDR       0x40000000
 525 #define XCHAL_RESET_VECBASE_OVERLAP     0
 526
 527 #define XCHAL_RESET_VECTOR0_VADDR       0x50000000
 528 #define XCHAL_RESET_VECTOR0_PADDR       0x50000000
 529 #define XCHAL_RESET_VECTOR1_VADDR       0x40000400
 530 #define XCHAL_RESET_VECTOR1_PADDR       0x40000400
 531 #define XCHAL_RESET_VECTOR_VADDR        0x50000000
 532 #define XCHAL_RESET_VECTOR_PADDR        0x50000000
 533 #define XCHAL_USER_VECOFS               0x00000340
 534 #define XCHAL_USER_VECTOR_VADDR         0x40000340
 535 #define XCHAL_USER_VECTOR_PADDR         0x40000340
 536 #define XCHAL_KERNEL_VECOFS             0x00000300
 537 #define XCHAL_KERNEL_VECTOR_VADDR       0x40000300
 538 #define XCHAL_KERNEL_VECTOR_PADDR       0x40000300
 539 #define XCHAL_DOUBLEEXC_VECOFS          0x000003C0
 540 #define XCHAL_DOUBLEEXC_VECTOR_VADDR    0x400003C0
 541 #define XCHAL_DOUBLEEXC_VECTOR_PADDR    0x400003C0
 542 #define XCHAL_WINDOW_OF4_VECOFS         0x00000000
 543 #define XCHAL_WINDOW_UF4_VECOFS         0x00000040
 544 #define XCHAL_WINDOW_OF8_VECOFS         0x00000080
 545 #define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
 546 #define XCHAL_WINDOW_OF12_VECOFS        0x00000100
 547 #define XCHAL_WINDOW_UF12_VECOFS        0x00000140
 548 #define XCHAL_WINDOW_VECTORS_VADDR      0x40000000
 549 #define XCHAL_WINDOW_VECTORS_PADDR      0x40000000
 550 #define XCHAL_INTLEVEL2_VECOFS          0x00000180
 551 #define XCHAL_INTLEVEL2_VECTOR_VADDR    0x40000180
 552 #define XCHAL_INTLEVEL2_VECTOR_PADDR    0x40000180
 553 #define XCHAL_INTLEVEL3_VECOFS          0x000001C0
 554 #define XCHAL_INTLEVEL3_VECTOR_VADDR    0x400001C0
 555 #define XCHAL_INTLEVEL3_VECTOR_PADDR    0x400001C0
 556 #define XCHAL_INTLEVEL4_VECOFS          0x00000200
 557 #define XCHAL_INTLEVEL4_VECTOR_VADDR    0x40000200
 558 #define XCHAL_INTLEVEL4_VECTOR_PADDR    0x40000200
 559 #define XCHAL_INTLEVEL5_VECOFS          0x00000240
 560 #define XCHAL_INTLEVEL5_VECTOR_VADDR    0x40000240
 561 #define XCHAL_INTLEVEL5_VECTOR_PADDR    0x40000240
 562 #define XCHAL_INTLEVEL6_VECOFS          0x00000280
 563 #define XCHAL_INTLEVEL6_VECTOR_VADDR    0x40000280
 564 #define XCHAL_INTLEVEL6_VECTOR_PADDR    0x40000280
 565 #define XCHAL_DEBUG_VECOFS              XCHAL_INTLEVEL6_VECOFS
 566 #define XCHAL_DEBUG_VECTOR_VADDR        XCHAL_INTLEVEL6_VECTOR_VADDR
 567 #define XCHAL_DEBUG_VECTOR_PADDR        XCHAL_INTLEVEL6_VECTOR_PADDR
 568 #define XCHAL_NMI_VECOFS                0x000002C0
 569 #define XCHAL_NMI_VECTOR_VADDR          0x400002C0
 570 #define XCHAL_NMI_VECTOR_PADDR          0x400002C0
 571 #define XCHAL_INTLEVEL7_VECOFS          XCHAL_NMI_VECOFS
 572 #define XCHAL_INTLEVEL7_VECTOR_VADDR    XCHAL_NMI_VECTOR_VADDR
 573 #define XCHAL_INTLEVEL7_VECTOR_PADDR    XCHAL_NMI_VECTOR_PADDR
 574
 575
 576 /*----------------------------------------------------------------------
 577                                 DEBUG MODULE
 578   ----------------------------------------------------------------------*/
 579
 580 /*  Misc  */
 581 #define XCHAL_HAVE_DEBUG_ERI            0       /* ERI to debug module */
 582 #define XCHAL_HAVE_DEBUG_APB            0       /* APB to debug module */
 583 #define XCHAL_HAVE_DEBUG_JTAG           1       /* JTAG to debug module */
 584
 585 /*  On-Chip Debug (OCD)  */
 586 #define XCHAL_HAVE_OCD                  1       /* OnChipDebug option */
 587 #define XCHAL_NUM_IBREAK                2       /* number of IBREAKn regs */
 588 #define XCHAL_NUM_DBREAK                2       /* number of DBREAKn regs */
 589 #define XCHAL_HAVE_OCD_DIR_ARRAY        0       /* faster OCD option (to LX4) */
 590 #define XCHAL_HAVE_OCD_LS32DDR          1       /* L32DDR/S32DDR (faster OCD) */
 591
 592 /*  TRAX (in core)  */
 593 #define XCHAL_HAVE_TRAX                 0       /* TRAX in debug module */
 594 #define XCHAL_TRAX_MEM_SIZE             0       /* TRAX memory size in bytes */
 595 #define XCHAL_TRAX_MEM_SHAREABLE        0       /* start/end regs; ready sig. */
 596 #define XCHAL_TRAX_ATB_WIDTH            0       /* ATB width (bits), 0=no ATB */
 597 #define XCHAL_TRAX_TIME_WIDTH           0       /* timestamp bitwidth, 0=none */
 598
 599 /*  Perf counters  */
 600 #define XCHAL_NUM_PERF_COUNTERS         0       /* performance counters */
 601
 602
 603 /*----------------------------------------------------------------------
 604                                 MMU
 605   ----------------------------------------------------------------------*/
 606
 607 /*  See core-matmap.h header file for more details.  */
 608
 609 #define XCHAL_HAVE_TLBS                 1       /* inverse of HAVE_CACHEATTR */
 610 #define XCHAL_HAVE_SPANNING_WAY         1       /* one way maps I+D 4GB vaddr */
 611 #define XCHAL_SPANNING_WAY              0       /* TLB spanning way number */
 612 #define XCHAL_HAVE_IDENTITY_MAP         1       /* vaddr == paddr always */
 613 #define XCHAL_HAVE_CACHEATTR            0       /* CACHEATTR register present */
 614 #define XCHAL_HAVE_MIMIC_CACHEATTR      1       /* region protection */
 615 #define XCHAL_HAVE_XLT_CACHEATTR        0       /* region prot. w/translation */
 616 #define XCHAL_HAVE_PTP_MMU              0       /* full MMU (with page table
 617                                                    [autorefill] and protection)
 618                                                    usable for an MMU-based OS */
 619
 620 /*  If none of the above last 5 are set, it's a custom TLB configuration.  */
 621
 622 #define XCHAL_MMU_ASID_BITS             0       /* number of bits in ASIDs */
 623 #define XCHAL_MMU_RINGS                 1       /* number of rings (1..4) */
 624 #define XCHAL_MMU_RING_BITS             0       /* num of bits in RING field */
 625
 626 /*----------------------------------------------------------------------
 627                                 MPU
 628   ----------------------------------------------------------------------*/
 629 #define XCHAL_HAVE_MPU                  0
 630 #define XCHAL_MPU_ENTRIES               0
 631
 632 #define XCHAL_MPU_ALIGN_REQ             1       /* MPU requires alignment of entries to background map */
 633 #define XCHAL_MPU_BACKGROUND_ENTRIES    0       /* number of entries in bg map*/
 634 #define XCHAL_MPU_BG_CACHEADRDIS        0       /* default CACHEADRDIS for bg */
 635
 636 #define XCHAL_MPU_ALIGN_BITS            0
 637 #define XCHAL_MPU_ALIGN                 0
 638
 639 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
 640
 641
 642 #endif /* XTENSA_CORE_SAMPLE_CONTROLLER_CORE_ISA_H */