target-arm/cpu64.c

   1 /*
   2  * QEMU AArch64 CPU
   3  *
   4  * Copyright (c) 2013 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "qemu-common.h"
  24 #if !defined(CONFIG_USER_ONLY)
  25 #include "hw/loader.h"
  26 #endif
  27 #include "hw/arm/arm.h"
  28 #include "sysemu/sysemu.h"
  29 #include "sysemu/kvm.h"
  30
  31 static inline void set_feature(CPUARMState *env, int feature)
  32 {
  33     env->features |= 1ULL << feature;
  34 }
  35
  36 static inline void unset_feature(CPUARMState *env, int feature)
  37 {
  38     env->features &= ~(1ULL << feature);
  39 }
  40
  41 #ifndef CONFIG_USER_ONLY
  42 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  43 {
  44     /* Number of processors is in [25:24]; otherwise we RAZ */
  45     return (smp_cpus - 1) << 24;
  46 }
  47 #endif
  48
  49 static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
  50 #ifndef CONFIG_USER_ONLY
  51     { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
  52       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
  53       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  54       .writefn = arm_cp_write_ignore },
  55     { .name = "L2CTLR",
  56       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
  57       .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  58       .writefn = arm_cp_write_ignore },
  59 #endif
  60     { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
  61       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
  62       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  63     { .name = "L2ECTLR",
  64       .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
  65       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  66     { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
  67       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
  68       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  69     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
  70       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
  71       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  72     { .name = "CPUACTLR",
  73       .cp = 15, .opc1 = 0, .crm = 15,
  74       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  75     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
  76       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
  77       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  78     { .name = "CPUECTLR",
  79       .cp = 15, .opc1 = 1, .crm = 15,
  80       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  81     { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
  82       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
  83       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  84     { .name = "CPUMERRSR",
  85       .cp = 15, .opc1 = 2, .crm = 15,
  86       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  87     { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
  88       .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
  89       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  90     { .name = "L2MERRSR",
  91       .cp = 15, .opc1 = 3, .crm = 15,
  92       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  93     REGINFO_SENTINEL
  94 };
  95
  96 static void aarch64_a57_initfn(Object *obj)
  97 {
  98     ARMCPU *cpu = ARM_CPU(obj);
  99
 100     cpu->dtb_compatible = "arm,cortex-a57";
 101     set_feature(&cpu->env, ARM_FEATURE_V8);
 102     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 103     set_feature(&cpu->env, ARM_FEATURE_NEON);
 104     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 105     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 106     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 107     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 108     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 109     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 110     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 111     set_feature(&cpu->env, ARM_FEATURE_CRC);
 112     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 113     cpu->midr = 0x411fd070;
 114     cpu->revidr = 0x00000000;
 115     cpu->reset_fpsid = 0x41034070;
 116     cpu->mvfr0 = 0x10110222;
 117     cpu->mvfr1 = 0x12111111;
 118     cpu->mvfr2 = 0x00000043;
 119     cpu->ctr = 0x8444c004;
 120     cpu->reset_sctlr = 0x00c50838;
 121     cpu->id_pfr0 = 0x00000131;
 122     cpu->id_pfr1 = 0x00011011;
 123     cpu->id_dfr0 = 0x03010066;
 124     cpu->id_afr0 = 0x00000000;
 125     cpu->id_mmfr0 = 0x10101105;
 126     cpu->id_mmfr1 = 0x40000000;
 127     cpu->id_mmfr2 = 0x01260000;
 128     cpu->id_mmfr3 = 0x02102211;
 129     cpu->id_isar0 = 0x02101110;
 130     cpu->id_isar1 = 0x13112111;
 131     cpu->id_isar2 = 0x21232042;
 132     cpu->id_isar3 = 0x01112131;
 133     cpu->id_isar4 = 0x00011142;
 134     cpu->id_isar5 = 0x00011121;
 135     cpu->id_aa64pfr0 = 0x00002222;
 136     cpu->id_aa64dfr0 = 0x10305106;
 137     cpu->id_aa64isar0 = 0x00011120;
 138     cpu->id_aa64mmfr0 = 0x00001124;
 139     cpu->dbgdidr = 0x3516d000;
 140     cpu->clidr = 0x0a200023;
 141     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 142     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 143     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 144     cpu->dcz_blocksize = 4; /* 64 bytes */
 145     define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 146 }
 147
 148 static void aarch64_a53_initfn(Object *obj)
 149 {
 150     ARMCPU *cpu = ARM_CPU(obj);
 151
 152     cpu->dtb_compatible = "arm,cortex-a53";
 153     set_feature(&cpu->env, ARM_FEATURE_V8);
 154     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 155     set_feature(&cpu->env, ARM_FEATURE_NEON);
 156     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 157     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 158     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 159     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 160     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 161     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 162     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 163     set_feature(&cpu->env, ARM_FEATURE_CRC);
 164     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 165     cpu->midr = 0x410fd034;
 166     cpu->revidr = 0x00000000;
 167     cpu->reset_fpsid = 0x41034070;
 168     cpu->mvfr0 = 0x10110222;
 169     cpu->mvfr1 = 0x12111111;
 170     cpu->mvfr2 = 0x00000043;
 171     cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 172     cpu->reset_sctlr = 0x00c50838;
 173     cpu->id_pfr0 = 0x00000131;
 174     cpu->id_pfr1 = 0x00011011;
 175     cpu->id_dfr0 = 0x03010066;
 176     cpu->id_afr0 = 0x00000000;
 177     cpu->id_mmfr0 = 0x10101105;
 178     cpu->id_mmfr1 = 0x40000000;
 179     cpu->id_mmfr2 = 0x01260000;
 180     cpu->id_mmfr3 = 0x02102211;
 181     cpu->id_isar0 = 0x02101110;
 182     cpu->id_isar1 = 0x13112111;
 183     cpu->id_isar2 = 0x21232042;
 184     cpu->id_isar3 = 0x01112131;
 185     cpu->id_isar4 = 0x00011142;
 186     cpu->id_isar5 = 0x00011121;
 187     cpu->id_aa64pfr0 = 0x00002222;
 188     cpu->id_aa64dfr0 = 0x10305106;
 189     cpu->id_aa64isar0 = 0x00011120;
 190     cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 191     cpu->dbgdidr = 0x3516d000;
 192     cpu->clidr = 0x0a200023;
 193     cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 194     cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 195     cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 196     cpu->dcz_blocksize = 4; /* 64 bytes */
 197     define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 198 }
 199
 200 #ifdef CONFIG_USER_ONLY
 201 static void aarch64_any_initfn(Object *obj)
 202 {
 203     ARMCPU *cpu = ARM_CPU(obj);
 204
 205     set_feature(&cpu->env, ARM_FEATURE_V8);
 206     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 207     set_feature(&cpu->env, ARM_FEATURE_NEON);
 208     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 209     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
 210     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
 211     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
 212     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
 213     set_feature(&cpu->env, ARM_FEATURE_CRC);
 214     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
 215     cpu->dcz_blocksize = 7; /*  512 bytes */
 216 }
 217 #endif
 218
 219 typedef struct ARMCPUInfo {
 220     const char *name;
 221     void (*initfn)(Object *obj);
 222     void (*class_init)(ObjectClass *oc, void *data);
 223 } ARMCPUInfo;
 224
 225 static const ARMCPUInfo aarch64_cpus[] = {
 226     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
 227     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
 228 #ifdef CONFIG_USER_ONLY
 229     { .name = "any",         .initfn = aarch64_any_initfn },
 230 #endif
 231     { .name = NULL }
 232 };
 233
 234 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
 235 {
 236     ARMCPU *cpu = ARM_CPU(obj);
 237
 238     return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
 239 }
 240
 241 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
 242 {
 243     ARMCPU *cpu = ARM_CPU(obj);
 244
 245     /* At this time, this property is only allowed if KVM is enabled.  This
 246      * restriction allows us to avoid fixing up functionality that assumes a
 247      * uniform execution state like do_interrupt.
 248      */
 249     if (!kvm_enabled()) {
 250         error_setg(errp, "'aarch64' feature cannot be disabled "
 251                          "unless KVM is enabled");
 252         return;
 253     }
 254
 255     if (value == false) {
 256         unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
 257     } else {
 258         set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 259     }
 260 }
 261
 262 static void aarch64_cpu_initfn(Object *obj)
 263 {
 264     object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
 265                              aarch64_cpu_set_aarch64, NULL);
 266     object_property_set_description(obj, "aarch64",
 267                                     "Set on/off to enable/disable aarch64 "
 268                                     "execution state ",
 269                                     NULL);
 270 }
 271
 272 static void aarch64_cpu_finalizefn(Object *obj)
 273 {
 274 }
 275
 276 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
 277 {
 278     ARMCPU *cpu = ARM_CPU(cs);
 279     /* It's OK to look at env for the current mode here, because it's
 280      * never possible for an AArch64 TB to chain to an AArch32 TB.
 281      * (Otherwise we would need to use synchronize_from_tb instead.)
 282      */
 283     if (is_a64(&cpu->env)) {
 284         cpu->env.pc = value;
 285     } else {
 286         cpu->env.regs[15] = value;
 287     }
 288 }
 289
 290 static gchar *aarch64_gdb_arch_name(CPUState *cs)
 291 {
 292     return g_strdup("aarch64");
 293 }
 294
 295 static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
 296 {
 297     CPUClass *cc = CPU_CLASS(oc);
 298
 299     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
 300     cc->set_pc = aarch64_cpu_set_pc;
 301     cc->gdb_read_register = aarch64_cpu_gdb_read_register;
 302     cc->gdb_write_register = aarch64_cpu_gdb_write_register;
 303     cc->gdb_num_core_regs = 34;
 304     cc->gdb_core_xml_file = "aarch64-core.xml";
 305     cc->gdb_arch_name = aarch64_gdb_arch_name;
 306 }
 307
 308 static void aarch64_cpu_register(const ARMCPUInfo *info)
 309 {
 310     TypeInfo type_info = {
 311         .parent = TYPE_AARCH64_CPU,
 312         .instance_size = sizeof(ARMCPU),
 313         .instance_init = info->initfn,
 314         .class_size = sizeof(ARMCPUClass),
 315         .class_init = info->class_init,
 316     };
 317
 318     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 319     type_register(&type_info);
 320     g_free((void *)type_info.name);
 321 }
 322
 323 static const TypeInfo aarch64_cpu_type_info = {
 324     .name = TYPE_AARCH64_CPU,
 325     .parent = TYPE_ARM_CPU,
 326     .instance_size = sizeof(ARMCPU),
 327     .instance_init = aarch64_cpu_initfn,
 328     .instance_finalize = aarch64_cpu_finalizefn,
 329     .abstract = true,
 330     .class_size = sizeof(AArch64CPUClass),
 331     .class_init = aarch64_cpu_class_init,
 332 };
 333
 334 static void aarch64_cpu_register_types(void)
 335 {
 336     const ARMCPUInfo *info = aarch64_cpus;
 337
 338     type_register_static(&aarch64_cpu_type_info);
 339
 340     while (info->name) {
 341         aarch64_cpu_register(info);
 342         info++;
 343     }
 344 }
 345
 346 type_init(aarch64_cpu_register_types)