hw/arm/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu-common.h"
  22 #include "qapi/error.h"
  23 #include "hw/sysbus.h"
  24 #include "migration/vmstate.h"
  25 #include "hw/arm/boot.h"
  26 #include "hw/loader.h"
  27 #include "net/net.h"
  28 #include "sysemu/kvm.h"
  29 #include "sysemu/runstate.h"
  30 #include "sysemu/sysemu.h"
  31 #include "hw/boards.h"
  32 #include "exec/address-spaces.h"
  33 #include "qemu/error-report.h"
  34 #include "hw/char/pl011.h"
  35 #include "hw/ide/ahci.h"
  36 #include "hw/cpu/a9mpcore.h"
  37 #include "hw/cpu/a15mpcore.h"
  38 #include "qemu/log.h"
  39
  40 #define SMP_BOOT_ADDR           0x100
  41 #define SMP_BOOT_REG            0x40
  42 #define MPCORE_PERIPHBASE       0xfff10000
  43
  44 #define MVBAR_ADDR              0x200
  45 #define BOARD_SETUP_ADDR        (MVBAR_ADDR + 8 * sizeof(uint32_t))
  46
  47 #define NIRQ_GIC                160
  48
  49 /* Board init.  */
  50
  51 static void hb_write_board_setup(ARMCPU *cpu,
  52                                  const struct arm_boot_info *info)
  53 {
  54     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
  55 }
  56
  57 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  58 {
  59     int n;
  60     uint32_t smpboot[] = {
  61         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  62         0xe210000f, /* ands r0, r0, #0x0f */
  63         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  64         0xe0830200, /* add r0, r3, r0, lsl #4 */
  65         0xe59f2024, /* ldr r2, privbase */
  66         0xe3a01001, /* mov r1, #1 */
  67         0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
  68         0xe3a010ff, /* mov r1, #0xff */
  69         0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
  70         0xf57ff04f, /* dsb */
  71         0xe320f003, /* wfi */
  72         0xe5901000, /* ldr     r1, [r0] */
  73         0xe1110001, /* tst     r1, r1 */
  74         0x0afffffb, /* beq     <wfi> */
  75         0xe12fff11, /* bx      r1 */
  76         MPCORE_PERIPHBASE   /* privbase: MPCore peripheral base address.  */
  77     };
  78     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  79         smpboot[n] = tswap32(smpboot[n]);
  80     }
  81     rom_add_blob_fixed_as("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR,
  82                           arm_boot_address_space(cpu, info));
  83 }
  84
  85 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  86 {
  87     CPUARMState *env = &cpu->env;
  88
  89     switch (info->nb_cpus) {
  90     case 4:
  91         address_space_stl_notdirty(&address_space_memory,
  92                                    SMP_BOOT_REG + 0x30, 0,
  93                                    MEMTXATTRS_UNSPECIFIED, NULL);
  94     case 3:
  95         address_space_stl_notdirty(&address_space_memory,
  96                                    SMP_BOOT_REG + 0x20, 0,
  97                                    MEMTXATTRS_UNSPECIFIED, NULL);
  98     case 2:
  99         address_space_stl_notdirty(&address_space_memory,
 100                                    SMP_BOOT_REG + 0x10, 0,
 101                                    MEMTXATTRS_UNSPECIFIED, NULL);
 102         env->regs[15] = SMP_BOOT_ADDR;
 103         break;
 104     default:
 105         break;
 106     }
 107 }
 108
 109 #define NUM_REGS      0x200
 110 static void hb_regs_write(void *opaque, hwaddr offset,
 111                           uint64_t value, unsigned size)
 112 {
 113     uint32_t *regs = opaque;
 114
 115     if (offset == 0xf00) {
 116         if (value == 1 || value == 2) {
 117             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 118         } else if (value == 3) {
 119             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 120         }
 121     }
 122
 123     if (offset / 4 >= NUM_REGS) {
 124         qemu_log_mask(LOG_GUEST_ERROR,
 125                   "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
 126         return;
 127     }
 128     regs[offset / 4] = value;
 129 }
 130
 131 static uint64_t hb_regs_read(void *opaque, hwaddr offset,
 132                              unsigned size)
 133 {
 134     uint32_t value;
 135     uint32_t *regs = opaque;
 136
 137     if (offset / 4 >= NUM_REGS) {
 138         qemu_log_mask(LOG_GUEST_ERROR,
 139                   "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
 140         return 0;
 141     }
 142     value = regs[offset / 4];
 143
 144     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 145         value |= 0x30000000;
 146     }
 147
 148     return value;
 149 }
 150
 151 static const MemoryRegionOps hb_mem_ops = {
 152     .read = hb_regs_read,
 153     .write = hb_regs_write,
 154     .endianness = DEVICE_NATIVE_ENDIAN,
 155 };
 156
 157 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
 158 #define HIGHBANK_REGISTERS(obj) \
 159     OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
 160
 161 typedef struct {
 162     /*< private >*/
 163     SysBusDevice parent_obj;
 164     /*< public >*/
 165
 166     MemoryRegion iomem;
 167     uint32_t regs[NUM_REGS];
 168 } HighbankRegsState;
 169
 170 static VMStateDescription vmstate_highbank_regs = {
 171     .name = "highbank-regs",
 172     .version_id = 0,
 173     .minimum_version_id = 0,
 174     .fields = (VMStateField[]) {
 175         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 176         VMSTATE_END_OF_LIST(),
 177     },
 178 };
 179
 180 static void highbank_regs_reset(DeviceState *dev)
 181 {
 182     HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
 183
 184     s->regs[0x40] = 0x05F20121;
 185     s->regs[0x41] = 0x2;
 186     s->regs[0x42] = 0x05F30121;
 187     s->regs[0x43] = 0x05F40121;
 188 }
 189
 190 static void highbank_regs_init(Object *obj)
 191 {
 192     HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
 193     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 194
 195     memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
 196                           "highbank_regs", 0x1000);
 197     sysbus_init_mmio(dev, &s->iomem);
 198 }
 199
 200 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 201 {
 202     DeviceClass *dc = DEVICE_CLASS(klass);
 203
 204     dc->desc = "Calxeda Highbank registers";
 205     dc->vmsd = &vmstate_highbank_regs;
 206     dc->reset = highbank_regs_reset;
 207 }
 208
 209 static const TypeInfo highbank_regs_info = {
 210     .name          = TYPE_HIGHBANK_REGISTERS,
 211     .parent        = TYPE_SYS_BUS_DEVICE,
 212     .instance_size = sizeof(HighbankRegsState),
 213     .instance_init = highbank_regs_init,
 214     .class_init    = highbank_regs_class_init,
 215 };
 216
 217 static void highbank_regs_register_types(void)
 218 {
 219     type_register_static(&highbank_regs_info);
 220 }
 221
 222 type_init(highbank_regs_register_types)
 223
 224 static struct arm_boot_info highbank_binfo;
 225
 226 enum cxmachines {
 227     CALXEDA_HIGHBANK,
 228     CALXEDA_MIDWAY,
 229 };
 230
 231 /* ram_size must be set to match the upper bound of memory in the
 232  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 233  * normally 0xff900000 or -m 4089. When running this board on a
 234  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 235  * device tree and pass -m 2047 to QEMU.
 236  */
 237 static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
 238 {
 239     DeviceState *dev = NULL;
 240     SysBusDevice *busdev;
 241     qemu_irq pic[128];
 242     int n;
 243     unsigned int smp_cpus = machine->smp.cpus;
 244     qemu_irq cpu_irq[4];
 245     qemu_irq cpu_fiq[4];
 246     qemu_irq cpu_virq[4];
 247     qemu_irq cpu_vfiq[4];
 248     MemoryRegion *sysram;
 249     MemoryRegion *sysmem;
 250     char *sysboot_filename;
 251
 252     switch (machine_id) {
 253     case CALXEDA_HIGHBANK:
 254         machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 255         break;
 256     case CALXEDA_MIDWAY:
 257         machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
 258         break;
 259     default:
 260         assert(0);
 261     }
 262
 263     for (n = 0; n < smp_cpus; n++) {
 264         Object *cpuobj;
 265         ARMCPU *cpu;
 266
 267         cpuobj = object_new(machine->cpu_type);
 268         cpu = ARM_CPU(cpuobj);
 269
 270         object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_SMC,
 271                                 &error_abort);
 272
 273         if (n) {
 274             /* Secondary CPUs start in PSCI powered-down state */
 275             object_property_set_bool(cpuobj, "start-powered-off", true,
 276                                      &error_abort);
 277         }
 278
 279         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 280             object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,
 281                                     &error_abort);
 282         }
 283         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 284         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
 285         cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
 286         cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
 287         cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ);
 288     }
 289
 290     sysmem = get_system_memory();
 291     /* SDRAM at address zero.  */
 292     memory_region_add_subregion(sysmem, 0, machine->ram);
 293
 294     sysram = g_new(MemoryRegion, 1);
 295     memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
 296                            &error_fatal);
 297     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 298     if (bios_name != NULL) {
 299         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 300         if (sysboot_filename != NULL) {
 301             if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
 302                 error_report("Unable to load %s", bios_name);
 303                 exit(1);
 304             }
 305             g_free(sysboot_filename);
 306         } else {
 307             error_report("Unable to find %s", bios_name);
 308             exit(1);
 309         }
 310     }
 311
 312     switch (machine_id) {
 313     case CALXEDA_HIGHBANK:
 314         dev = qdev_new("l2x0");
 315         busdev = SYS_BUS_DEVICE(dev);
 316         sysbus_realize_and_unref(busdev, &error_fatal);
 317         sysbus_mmio_map(busdev, 0, 0xfff12000);
 318
 319         dev = qdev_new(TYPE_A9MPCORE_PRIV);
 320         break;
 321     case CALXEDA_MIDWAY:
 322         dev = qdev_new(TYPE_A15MPCORE_PRIV);
 323         break;
 324     }
 325     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 326     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 327     busdev = SYS_BUS_DEVICE(dev);
 328     sysbus_realize_and_unref(busdev, &error_fatal);
 329     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 330     for (n = 0; n < smp_cpus; n++) {
 331         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 332         sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
 333         sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]);
 334         sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
 335     }
 336
 337     for (n = 0; n < 128; n++) {
 338         pic[n] = qdev_get_gpio_in(dev, n);
 339     }
 340
 341     dev = qdev_new("sp804");
 342     qdev_prop_set_uint32(dev, "freq0", 150000000);
 343     qdev_prop_set_uint32(dev, "freq1", 150000000);
 344     busdev = SYS_BUS_DEVICE(dev);
 345     sysbus_realize_and_unref(busdev, &error_fatal);
 346     sysbus_mmio_map(busdev, 0, 0xfff34000);
 347     sysbus_connect_irq(busdev, 0, pic[18]);
 348     pl011_create(0xfff36000, pic[20], serial_hd(0));
 349
 350     dev = qdev_new(TYPE_HIGHBANK_REGISTERS);
 351     busdev = SYS_BUS_DEVICE(dev);
 352     sysbus_realize_and_unref(busdev, &error_fatal);
 353     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 354
 355     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 356     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 357     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 358     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 359     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 360     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 361
 362     sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
 363
 364     if (nd_table[0].used) {
 365         qemu_check_nic_model(&nd_table[0], "xgmac");
 366         dev = qdev_new("xgmac");
 367         qdev_set_nic_properties(dev, &nd_table[0]);
 368         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 369         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
 370         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
 371         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
 372         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
 373
 374         qemu_check_nic_model(&nd_table[1], "xgmac");
 375         dev = qdev_new("xgmac");
 376         qdev_set_nic_properties(dev, &nd_table[1]);
 377         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 378         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
 379         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
 380         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
 381         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
 382     }
 383
 384     /* TODO create and connect IDE devices for ide_drive_get() */
 385
 386     highbank_binfo.ram_size = machine->ram_size;
 387     /* highbank requires a dtb in order to boot, and the dtb will override
 388      * the board ID. The following value is ignored, so set it to -1 to be
 389      * clear that the value is meaningless.
 390      */
 391     highbank_binfo.board_id = -1;
 392     highbank_binfo.nb_cpus = smp_cpus;
 393     highbank_binfo.loader_start = 0;
 394     highbank_binfo.write_secondary_boot = hb_write_secondary;
 395     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 396     if (!kvm_enabled()) {
 397         highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
 398         highbank_binfo.write_board_setup = hb_write_board_setup;
 399         highbank_binfo.secure_board_setup = true;
 400     } else {
 401         warn_report("cannot load built-in Monitor support "
 402                     "if KVM is enabled. Some guests (such as Linux) "
 403                     "may not boot.");
 404     }
 405
 406     arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
 407 }
 408
 409 static void highbank_init(MachineState *machine)
 410 {
 411     calxeda_init(machine, CALXEDA_HIGHBANK);
 412 }
 413
 414 static void midway_init(MachineState *machine)
 415 {
 416     calxeda_init(machine, CALXEDA_MIDWAY);
 417 }
 418
 419 static void highbank_class_init(ObjectClass *oc, void *data)
 420 {
 421     MachineClass *mc = MACHINE_CLASS(oc);
 422
 423     mc->desc = "Calxeda Highbank (ECX-1000)";
 424     mc->init = highbank_init;
 425     mc->block_default_type = IF_IDE;
 426     mc->units_per_default_bus = 1;
 427     mc->max_cpus = 4;
 428     mc->ignore_memory_transaction_failures = true;
 429     mc->default_ram_id = "highbank.dram";
 430 }
 431
 432 static const TypeInfo highbank_type = {
 433     .name = MACHINE_TYPE_NAME("highbank"),
 434     .parent = TYPE_MACHINE,
 435     .class_init = highbank_class_init,
 436 };
 437
 438 static void midway_class_init(ObjectClass *oc, void *data)
 439 {
 440     MachineClass *mc = MACHINE_CLASS(oc);
 441
 442     mc->desc = "Calxeda Midway (ECX-2000)";
 443     mc->init = midway_init;
 444     mc->block_default_type = IF_IDE;
 445     mc->units_per_default_bus = 1;
 446     mc->max_cpus = 4;
 447     mc->ignore_memory_transaction_failures = true;
 448     mc->default_ram_id = "highbank.dram";
 449 }
 450
 451 static const TypeInfo midway_type = {
 452     .name = MACHINE_TYPE_NAME("midway"),
 453     .parent = TYPE_MACHINE,
 454     .class_init = midway_class_init,
 455 };
 456
 457 static void calxeda_machines_init(void)
 458 {
 459     type_register_static(&highbank_type);
 460     type_register_static(&midway_type);
 461 }
 462
 463 type_init(calxeda_machines_init)