hw/arm/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "cpu.h"
  13 #include "hw/sysbus.h"
  14 #include "migration/vmstate.h"
  15 #include "hw/boards.h"
  16 #include "hw/arm/boot.h"
  17 #include "hw/misc/arm_integrator_debug.h"
  18 #include "hw/net/smc91c111.h"
  19 #include "net/net.h"
  20 #include "exec/address-spaces.h"
  21 #include "sysemu/runstate.h"
  22 #include "sysemu/sysemu.h"
  23 #include "qemu/log.h"
  24 #include "qemu/error-report.h"
  25 #include "hw/char/pl011.h"
  26 #include "hw/hw.h"
  27 #include "hw/irq.h"
  28
  29 #define TYPE_INTEGRATOR_CM "integrator_core"
  30 #define INTEGRATOR_CM(obj) \
  31     OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
  32
  33 typedef struct IntegratorCMState {
  34     /*< private >*/
  35     SysBusDevice parent_obj;
  36     /*< public >*/
  37
  38     MemoryRegion iomem;
  39     uint32_t memsz;
  40     MemoryRegion flash;
  41     uint32_t cm_osc;
  42     uint32_t cm_ctrl;
  43     uint32_t cm_lock;
  44     uint32_t cm_auxosc;
  45     uint32_t cm_sdram;
  46     uint32_t cm_init;
  47     uint32_t cm_flags;
  48     uint32_t cm_nvflags;
  49     uint32_t cm_refcnt_offset;
  50     uint32_t int_level;
  51     uint32_t irq_enabled;
  52     uint32_t fiq_enabled;
  53 } IntegratorCMState;
  54
  55 static uint8_t integrator_spd[128] = {
  56    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  57    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  58 };
  59
  60 static const VMStateDescription vmstate_integratorcm = {
  61     .name = "integratorcm",
  62     .version_id = 1,
  63     .minimum_version_id = 1,
  64     .fields      = (VMStateField[]) {
  65         VMSTATE_UINT32(cm_osc, IntegratorCMState),
  66         VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
  67         VMSTATE_UINT32(cm_lock, IntegratorCMState),
  68         VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
  69         VMSTATE_UINT32(cm_sdram, IntegratorCMState),
  70         VMSTATE_UINT32(cm_init, IntegratorCMState),
  71         VMSTATE_UINT32(cm_flags, IntegratorCMState),
  72         VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
  73         VMSTATE_UINT32(int_level, IntegratorCMState),
  74         VMSTATE_UINT32(irq_enabled, IntegratorCMState),
  75         VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
  76         VMSTATE_END_OF_LIST()
  77     }
  78 };
  79
  80 static uint64_t integratorcm_read(void *opaque, hwaddr offset,
  81                                   unsigned size)
  82 {
  83     IntegratorCMState *s = opaque;
  84     if (offset >= 0x100 && offset < 0x200) {
  85         /* CM_SPD */
  86         if (offset >= 0x180)
  87             return 0;
  88         return integrator_spd[offset >> 2];
  89     }
  90     switch (offset >> 2) {
  91     case 0: /* CM_ID */
  92         return 0x411a3001;
  93     case 1: /* CM_PROC */
  94         return 0;
  95     case 2: /* CM_OSC */
  96         return s->cm_osc;
  97     case 3: /* CM_CTRL */
  98         return s->cm_ctrl;
  99     case 4: /* CM_STAT */
 100         return 0x00100000;
 101     case 5: /* CM_LOCK */
 102         if (s->cm_lock == 0xa05f) {
 103             return 0x1a05f;
 104         } else {
 105             return s->cm_lock;
 106         }
 107     case 6: /* CM_LMBUSCNT */
 108         /* ??? High frequency timer.  */
 109         hw_error("integratorcm_read: CM_LMBUSCNT");
 110     case 7: /* CM_AUXOSC */
 111         return s->cm_auxosc;
 112     case 8: /* CM_SDRAM */
 113         return s->cm_sdram;
 114     case 9: /* CM_INIT */
 115         return s->cm_init;
 116     case 10: /* CM_REFCNT */
 117         /* This register, CM_REFCNT, provides a 32-bit count value.
 118          * The count increments at the fixed reference clock frequency of 24MHz
 119          * and can be used as a real-time counter.
 120          */
 121         return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
 122                                   1000) - s->cm_refcnt_offset;
 123     case 12: /* CM_FLAGS */
 124         return s->cm_flags;
 125     case 14: /* CM_NVFLAGS */
 126         return s->cm_nvflags;
 127     case 16: /* CM_IRQ_STAT */
 128         return s->int_level & s->irq_enabled;
 129     case 17: /* CM_IRQ_RSTAT */
 130         return s->int_level;
 131     case 18: /* CM_IRQ_ENSET */
 132         return s->irq_enabled;
 133     case 20: /* CM_SOFT_INTSET */
 134         return s->int_level & 1;
 135     case 24: /* CM_FIQ_STAT */
 136         return s->int_level & s->fiq_enabled;
 137     case 25: /* CM_FIQ_RSTAT */
 138         return s->int_level;
 139     case 26: /* CM_FIQ_ENSET */
 140         return s->fiq_enabled;
 141     case 32: /* CM_VOLTAGE_CTL0 */
 142     case 33: /* CM_VOLTAGE_CTL1 */
 143     case 34: /* CM_VOLTAGE_CTL2 */
 144     case 35: /* CM_VOLTAGE_CTL3 */
 145         /* ??? Voltage control unimplemented.  */
 146         return 0;
 147     default:
 148         qemu_log_mask(LOG_UNIMP,
 149                       "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
 150                       __func__, offset);
 151         return 0;
 152     }
 153 }
 154
 155 static void integratorcm_do_remap(IntegratorCMState *s)
 156 {
 157     /* Sync memory region state with CM_CTRL REMAP bit:
 158      * bit 0 => flash at address 0; bit 1 => RAM
 159      */
 160     memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
 161 }
 162
 163 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
 164 {
 165     if (value & 8) {
 166         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 167     }
 168     if ((s->cm_ctrl ^ value) & 1) {
 169         /* (value & 1) != 0 means the green "MISC LED" is lit.
 170          * We don't have any nice place to display LEDs. printf is a bad
 171          * idea because Linux uses the LED as a heartbeat and the output
 172          * will swamp anything else on the terminal.
 173          */
 174     }
 175     /* Note that the RESET bit [3] always reads as zero */
 176     s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
 177     integratorcm_do_remap(s);
 178 }
 179
 180 static void integratorcm_update(IntegratorCMState *s)
 181 {
 182     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 183        are active.  */
 184     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 185         hw_error("Core module interrupt\n");
 186 }
 187
 188 static void integratorcm_write(void *opaque, hwaddr offset,
 189                                uint64_t value, unsigned size)
 190 {
 191     IntegratorCMState *s = opaque;
 192     switch (offset >> 2) {
 193     case 2: /* CM_OSC */
 194         if (s->cm_lock == 0xa05f)
 195             s->cm_osc = value;
 196         break;
 197     case 3: /* CM_CTRL */
 198         integratorcm_set_ctrl(s, value);
 199         break;
 200     case 5: /* CM_LOCK */
 201         s->cm_lock = value & 0xffff;
 202         break;
 203     case 7: /* CM_AUXOSC */
 204         if (s->cm_lock == 0xa05f)
 205             s->cm_auxosc = value;
 206         break;
 207     case 8: /* CM_SDRAM */
 208         s->cm_sdram = value;
 209         break;
 210     case 9: /* CM_INIT */
 211         /* ??? This can change the memory bus frequency.  */
 212         s->cm_init = value;
 213         break;
 214     case 12: /* CM_FLAGSS */
 215         s->cm_flags |= value;
 216         break;
 217     case 13: /* CM_FLAGSC */
 218         s->cm_flags &= ~value;
 219         break;
 220     case 14: /* CM_NVFLAGSS */
 221         s->cm_nvflags |= value;
 222         break;
 223     case 15: /* CM_NVFLAGSS */
 224         s->cm_nvflags &= ~value;
 225         break;
 226     case 18: /* CM_IRQ_ENSET */
 227         s->irq_enabled |= value;
 228         integratorcm_update(s);
 229         break;
 230     case 19: /* CM_IRQ_ENCLR */
 231         s->irq_enabled &= ~value;
 232         integratorcm_update(s);
 233         break;
 234     case 20: /* CM_SOFT_INTSET */
 235         s->int_level |= (value & 1);
 236         integratorcm_update(s);
 237         break;
 238     case 21: /* CM_SOFT_INTCLR */
 239         s->int_level &= ~(value & 1);
 240         integratorcm_update(s);
 241         break;
 242     case 26: /* CM_FIQ_ENSET */
 243         s->fiq_enabled |= value;
 244         integratorcm_update(s);
 245         break;
 246     case 27: /* CM_FIQ_ENCLR */
 247         s->fiq_enabled &= ~value;
 248         integratorcm_update(s);
 249         break;
 250     case 32: /* CM_VOLTAGE_CTL0 */
 251     case 33: /* CM_VOLTAGE_CTL1 */
 252     case 34: /* CM_VOLTAGE_CTL2 */
 253     case 35: /* CM_VOLTAGE_CTL3 */
 254         /* ??? Voltage control unimplemented.  */
 255         break;
 256     default:
 257         qemu_log_mask(LOG_UNIMP,
 258                       "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
 259                       __func__, offset);
 260         break;
 261     }
 262 }
 263
 264 /* Integrator/CM control registers.  */
 265
 266 static const MemoryRegionOps integratorcm_ops = {
 267     .read = integratorcm_read,
 268     .write = integratorcm_write,
 269     .endianness = DEVICE_NATIVE_ENDIAN,
 270 };
 271
 272 static void integratorcm_init(Object *obj)
 273 {
 274     IntegratorCMState *s = INTEGRATOR_CM(obj);
 275
 276     s->cm_osc = 0x01000048;
 277     /* ??? What should the high bits of this value be?  */
 278     s->cm_auxosc = 0x0007feff;
 279     s->cm_sdram = 0x00011122;
 280     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 281     s->cm_init = 0x00000112;
 282     s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
 283                                    1000);
 284
 285     /* ??? Save/restore.  */
 286 }
 287
 288 static void integratorcm_realize(DeviceState *d, Error **errp)
 289 {
 290     IntegratorCMState *s = INTEGRATOR_CM(d);
 291     SysBusDevice *dev = SYS_BUS_DEVICE(d);
 292     Error *local_err = NULL;
 293
 294     memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000,
 295                            &local_err);
 296     if (local_err) {
 297         error_propagate(errp, local_err);
 298         return;
 299     }
 300
 301     memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s,
 302                           "integratorcm", 0x00800000);
 303     sysbus_init_mmio(dev, &s->iomem);
 304
 305     integratorcm_do_remap(s);
 306
 307     if (s->memsz >= 256) {
 308         integrator_spd[31] = 64;
 309         s->cm_sdram |= 0x10;
 310     } else if (s->memsz >= 128) {
 311         integrator_spd[31] = 32;
 312         s->cm_sdram |= 0x0c;
 313     } else if (s->memsz >= 64) {
 314         integrator_spd[31] = 16;
 315         s->cm_sdram |= 0x08;
 316     } else if (s->memsz >= 32) {
 317         integrator_spd[31] = 4;
 318         s->cm_sdram |= 0x04;
 319     } else {
 320         integrator_spd[31] = 2;
 321     }
 322 }
 323
 324 /* Integrator/CP hardware emulation.  */
 325 /* Primary interrupt controller.  */
 326
 327 #define TYPE_INTEGRATOR_PIC "integrator_pic"
 328 #define INTEGRATOR_PIC(obj) \
 329    OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
 330
 331 typedef struct icp_pic_state {
 332     /*< private >*/
 333     SysBusDevice parent_obj;
 334     /*< public >*/
 335
 336     MemoryRegion iomem;
 337     uint32_t level;
 338     uint32_t irq_enabled;
 339     uint32_t fiq_enabled;
 340     qemu_irq parent_irq;
 341     qemu_irq parent_fiq;
 342 } icp_pic_state;
 343
 344 static const VMStateDescription vmstate_icp_pic = {
 345     .name = "icp_pic",
 346     .version_id = 1,
 347     .minimum_version_id = 1,
 348     .fields      = (VMStateField[]) {
 349         VMSTATE_UINT32(level, icp_pic_state),
 350         VMSTATE_UINT32(irq_enabled, icp_pic_state),
 351         VMSTATE_UINT32(fiq_enabled, icp_pic_state),
 352         VMSTATE_END_OF_LIST()
 353     }
 354 };
 355
 356 static void icp_pic_update(icp_pic_state *s)
 357 {
 358     uint32_t flags;
 359
 360     flags = (s->level & s->irq_enabled);
 361     qemu_set_irq(s->parent_irq, flags != 0);
 362     flags = (s->level & s->fiq_enabled);
 363     qemu_set_irq(s->parent_fiq, flags != 0);
 364 }
 365
 366 static void icp_pic_set_irq(void *opaque, int irq, int level)
 367 {
 368     icp_pic_state *s = (icp_pic_state *)opaque;
 369     if (level)
 370         s->level |= 1 << irq;
 371     else
 372         s->level &= ~(1 << irq);
 373     icp_pic_update(s);
 374 }
 375
 376 static uint64_t icp_pic_read(void *opaque, hwaddr offset,
 377                              unsigned size)
 378 {
 379     icp_pic_state *s = (icp_pic_state *)opaque;
 380
 381     switch (offset >> 2) {
 382     case 0: /* IRQ_STATUS */
 383         return s->level & s->irq_enabled;
 384     case 1: /* IRQ_RAWSTAT */
 385         return s->level;
 386     case 2: /* IRQ_ENABLESET */
 387         return s->irq_enabled;
 388     case 4: /* INT_SOFTSET */
 389         return s->level & 1;
 390     case 8: /* FRQ_STATUS */
 391         return s->level & s->fiq_enabled;
 392     case 9: /* FRQ_RAWSTAT */
 393         return s->level;
 394     case 10: /* FRQ_ENABLESET */
 395         return s->fiq_enabled;
 396     case 3: /* IRQ_ENABLECLR */
 397     case 5: /* INT_SOFTCLR */
 398     case 11: /* FRQ_ENABLECLR */
 399     default:
 400         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 401                       __func__, offset);
 402         return 0;
 403     }
 404 }
 405
 406 static void icp_pic_write(void *opaque, hwaddr offset,
 407                           uint64_t value, unsigned size)
 408 {
 409     icp_pic_state *s = (icp_pic_state *)opaque;
 410
 411     switch (offset >> 2) {
 412     case 2: /* IRQ_ENABLESET */
 413         s->irq_enabled |= value;
 414         break;
 415     case 3: /* IRQ_ENABLECLR */
 416         s->irq_enabled &= ~value;
 417         break;
 418     case 4: /* INT_SOFTSET */
 419         if (value & 1)
 420             icp_pic_set_irq(s, 0, 1);
 421         break;
 422     case 5: /* INT_SOFTCLR */
 423         if (value & 1)
 424             icp_pic_set_irq(s, 0, 0);
 425         break;
 426     case 10: /* FRQ_ENABLESET */
 427         s->fiq_enabled |= value;
 428         break;
 429     case 11: /* FRQ_ENABLECLR */
 430         s->fiq_enabled &= ~value;
 431         break;
 432     case 0: /* IRQ_STATUS */
 433     case 1: /* IRQ_RAWSTAT */
 434     case 8: /* FRQ_STATUS */
 435     case 9: /* FRQ_RAWSTAT */
 436     default:
 437         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 438                       __func__, offset);
 439         return;
 440     }
 441     icp_pic_update(s);
 442 }
 443
 444 static const MemoryRegionOps icp_pic_ops = {
 445     .read = icp_pic_read,
 446     .write = icp_pic_write,
 447     .endianness = DEVICE_NATIVE_ENDIAN,
 448 };
 449
 450 static void icp_pic_init(Object *obj)
 451 {
 452     DeviceState *dev = DEVICE(obj);
 453     icp_pic_state *s = INTEGRATOR_PIC(obj);
 454     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 455
 456     qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
 457     sysbus_init_irq(sbd, &s->parent_irq);
 458     sysbus_init_irq(sbd, &s->parent_fiq);
 459     memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s,
 460                           "icp-pic", 0x00800000);
 461     sysbus_init_mmio(sbd, &s->iomem);
 462 }
 463
 464 /* CP control registers.  */
 465
 466 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
 467 #define ICP_CONTROL_REGS(obj) \
 468     OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
 469
 470 typedef struct ICPCtrlRegsState {
 471     /*< private >*/
 472     SysBusDevice parent_obj;
 473     /*< public >*/
 474
 475     MemoryRegion iomem;
 476
 477     qemu_irq mmc_irq;
 478     uint32_t intreg_state;
 479 } ICPCtrlRegsState;
 480
 481 #define ICP_GPIO_MMC_WPROT      "mmc-wprot"
 482 #define ICP_GPIO_MMC_CARDIN     "mmc-cardin"
 483
 484 #define ICP_INTREG_WPROT        (1 << 0)
 485 #define ICP_INTREG_CARDIN       (1 << 3)
 486
 487 static const VMStateDescription vmstate_icp_control = {
 488     .name = "icp_control",
 489     .version_id = 1,
 490     .minimum_version_id = 1,
 491     .fields      = (VMStateField[]) {
 492         VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
 493         VMSTATE_END_OF_LIST()
 494     }
 495 };
 496
 497 static uint64_t icp_control_read(void *opaque, hwaddr offset,
 498                                  unsigned size)
 499 {
 500     ICPCtrlRegsState *s = opaque;
 501
 502     switch (offset >> 2) {
 503     case 0: /* CP_IDFIELD */
 504         return 0x41034003;
 505     case 1: /* CP_FLASHPROG */
 506         return 0;
 507     case 2: /* CP_INTREG */
 508         return s->intreg_state;
 509     case 3: /* CP_DECODE */
 510         return 0x11;
 511     default:
 512         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 513                       __func__, offset);
 514         return 0;
 515     }
 516 }
 517
 518 static void icp_control_write(void *opaque, hwaddr offset,
 519                           uint64_t value, unsigned size)
 520 {
 521     ICPCtrlRegsState *s = opaque;
 522
 523     switch (offset >> 2) {
 524     case 2: /* CP_INTREG */
 525         s->intreg_state &= ~(value & ICP_INTREG_CARDIN);
 526         qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN));
 527         break;
 528     case 1: /* CP_FLASHPROG */
 529     case 3: /* CP_DECODE */
 530         /* Nothing interesting implemented yet.  */
 531         break;
 532     default:
 533         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 534                       __func__, offset);
 535     }
 536 }
 537
 538 static const MemoryRegionOps icp_control_ops = {
 539     .read = icp_control_read,
 540     .write = icp_control_write,
 541     .endianness = DEVICE_NATIVE_ENDIAN,
 542 };
 543
 544 static void icp_control_mmc_wprot(void *opaque, int line, int level)
 545 {
 546     ICPCtrlRegsState *s = opaque;
 547
 548     s->intreg_state &= ~ICP_INTREG_WPROT;
 549     if (level) {
 550         s->intreg_state |= ICP_INTREG_WPROT;
 551     }
 552 }
 553
 554 static void icp_control_mmc_cardin(void *opaque, int line, int level)
 555 {
 556     ICPCtrlRegsState *s = opaque;
 557
 558     /* line is released by writing to CP_INTREG */
 559     if (level) {
 560         s->intreg_state |= ICP_INTREG_CARDIN;
 561         qemu_set_irq(s->mmc_irq, 1);
 562     }
 563 }
 564
 565 static void icp_control_init(Object *obj)
 566 {
 567     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 568     ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
 569     DeviceState *dev = DEVICE(obj);
 570
 571     memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
 572                           "icp_ctrl_regs", 0x00800000);
 573     sysbus_init_mmio(sbd, &s->iomem);
 574
 575     qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1);
 576     qdev_init_gpio_in_named(dev, icp_control_mmc_cardin,
 577                             ICP_GPIO_MMC_CARDIN, 1);
 578     sysbus_init_irq(sbd, &s->mmc_irq);
 579 }
 580
 581
 582 /* Board init.  */
 583
 584 static struct arm_boot_info integrator_binfo = {
 585     .loader_start = 0x0,
 586     .board_id = 0x113,
 587 };
 588
 589 static void integratorcp_init(MachineState *machine)
 590 {
 591     ram_addr_t ram_size = machine->ram_size;
 592     Object *cpuobj;
 593     ARMCPU *cpu;
 594     MemoryRegion *address_space_mem = get_system_memory();
 595     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
 596     qemu_irq pic[32];
 597     DeviceState *dev, *sic, *icp;
 598     int i;
 599
 600     cpuobj = object_new(machine->cpu_type);
 601
 602     /* By default ARM1176 CPUs have EL3 enabled.  This board does not
 603      * currently support EL3 so the CPU EL3 property is disabled before
 604      * realization.
 605      */
 606     if (object_property_find(cpuobj, "has_el3", NULL)) {
 607         object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
 608     }
 609
 610     qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 611
 612     cpu = ARM_CPU(cpuobj);
 613
 614     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 615     /* ??? RAM should repeat to fill physical memory space.  */
 616     /* SDRAM at address zero*/
 617     memory_region_add_subregion(address_space_mem, 0, machine->ram);
 618     /* And again at address 0x80000000 */
 619     memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram,
 620                              0, ram_size);
 621     memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
 622
 623     dev = qdev_new(TYPE_INTEGRATOR_CM);
 624     qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
 625     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 626     sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
 627
 628     dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
 629                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
 630                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
 631                                 NULL);
 632     for (i = 0; i < 32; i++) {
 633         pic[i] = qdev_get_gpio_in(dev, i);
 634     }
 635     sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
 636     sysbus_create_varargs("integrator_pit", 0x13000000,
 637                           pic[5], pic[6], pic[7], NULL);
 638     sysbus_create_simple("pl031", 0x15000000, pic[8]);
 639     pl011_create(0x16000000, pic[1], serial_hd(0));
 640     pl011_create(0x17000000, pic[2], serial_hd(1));
 641     icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,
 642                                qdev_get_gpio_in(sic, 3));
 643     sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
 644     sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
 645     sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
 646
 647     dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
 648     qdev_connect_gpio_out(dev, 0,
 649                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
 650     qdev_connect_gpio_out(dev, 1,
 651                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
 652     sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);
 653
 654     if (nd_table[0].used)
 655         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
 656
 657     sysbus_create_simple("pl110", 0xc0000000, pic[22]);
 658
 659     integrator_binfo.ram_size = ram_size;
 660     arm_load_kernel(cpu, machine, &integrator_binfo);
 661 }
 662
 663 static void integratorcp_machine_init(MachineClass *mc)
 664 {
 665     mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
 666     mc->init = integratorcp_init;
 667     mc->ignore_memory_transaction_failures = true;
 668     mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
 669     mc->default_ram_id = "integrator.ram";
 670 }
 671
 672 DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
 673
 674 static Property core_properties[] = {
 675     DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
 676     DEFINE_PROP_END_OF_LIST(),
 677 };
 678
 679 static void core_class_init(ObjectClass *klass, void *data)
 680 {
 681     DeviceClass *dc = DEVICE_CLASS(klass);
 682
 683     device_class_set_props(dc, core_properties);
 684     dc->realize = integratorcm_realize;
 685     dc->vmsd = &vmstate_integratorcm;
 686 }
 687
 688 static void icp_pic_class_init(ObjectClass *klass, void *data)
 689 {
 690     DeviceClass *dc = DEVICE_CLASS(klass);
 691
 692     dc->vmsd = &vmstate_icp_pic;
 693 }
 694
 695 static void icp_control_class_init(ObjectClass *klass, void *data)
 696 {
 697     DeviceClass *dc = DEVICE_CLASS(klass);
 698
 699     dc->vmsd = &vmstate_icp_control;
 700 }
 701
 702 static const TypeInfo core_info = {
 703     .name          = TYPE_INTEGRATOR_CM,
 704     .parent        = TYPE_SYS_BUS_DEVICE,
 705     .instance_size = sizeof(IntegratorCMState),
 706     .instance_init = integratorcm_init,
 707     .class_init    = core_class_init,
 708 };
 709
 710 static const TypeInfo icp_pic_info = {
 711     .name          = TYPE_INTEGRATOR_PIC,
 712     .parent        = TYPE_SYS_BUS_DEVICE,
 713     .instance_size = sizeof(icp_pic_state),
 714     .instance_init = icp_pic_init,
 715     .class_init    = icp_pic_class_init,
 716 };
 717
 718 static const TypeInfo icp_ctrl_regs_info = {
 719     .name          = TYPE_ICP_CONTROL_REGS,
 720     .parent        = TYPE_SYS_BUS_DEVICE,
 721     .instance_size = sizeof(ICPCtrlRegsState),
 722     .instance_init = icp_control_init,
 723     .class_init    = icp_control_class_init,
 724 };
 725
 726 static void integratorcp_register_types(void)
 727 {
 728     type_register_static(&icp_pic_info);
 729     type_register_static(&core_info);
 730     type_register_static(&icp_ctrl_regs_info);
 731 }
 732
 733 type_init(integratorcp_register_types)