sd/milkymist-memcard: Fix format string
[qemu/armbru.git] / hw / arm / msf2-soc.c
blob33ea7df342c2b8e20a3b863450851550342b42d7
1 /*
2 * SmartFusion2 SoC emulation.
4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "exec/address-spaces.h"
29 #include "hw/char/serial.h"
30 #include "hw/irq.h"
31 #include "hw/arm/msf2-soc.h"
32 #include "hw/misc/unimp.h"
33 #include "sysemu/runstate.h"
34 #include "sysemu/sysemu.h"
36 #define MSF2_TIMER_BASE 0x40004000
37 #define MSF2_SYSREG_BASE 0x40038000
38 #define MSF2_EMAC_BASE 0x40041000
40 #define ENVM_BASE_ADDRESS 0x60000000
42 #define SRAM_BASE_ADDRESS 0x20000000
44 #define MSF2_EMAC_IRQ 12
46 #define MSF2_ENVM_MAX_SIZE (512 * KiB)
49 * eSRAM max size is 80k without SECDED(Single error correction and
50 * dual error detection) feature and 64k with SECDED.
51 * We do not support SECDED now.
53 #define MSF2_ESRAM_MAX_SIZE (80 * KiB)
55 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
56 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
58 static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
59 static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
60 static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
62 static void do_sys_reset(void *opaque, int n, int level)
64 if (level) {
65 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
69 static void m2sxxx_soc_initfn(Object *obj)
71 MSF2State *s = MSF2_SOC(obj);
72 int i;
74 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
76 object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG);
78 object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER);
80 for (i = 0; i < MSF2_NUM_SPIS; i++) {
81 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI);
84 object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC);
87 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
89 MSF2State *s = MSF2_SOC(dev_soc);
90 DeviceState *dev, *armv7m;
91 SysBusDevice *busdev;
92 int i;
94 MemoryRegion *system_memory = get_system_memory();
95 MemoryRegion *nvm = g_new(MemoryRegion, 1);
96 MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
97 MemoryRegion *sram = g_new(MemoryRegion, 1);
99 memory_region_init_rom(nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
100 &error_fatal);
102 * On power-on, the eNVM region 0x60000000 is automatically
103 * remapped to the Cortex-M3 processor executable region
104 * start address (0x0). We do not support remapping other eNVM,
105 * eSRAM and DDR regions by guest(via Sysreg) currently.
107 memory_region_init_alias(nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", nvm, 0,
108 s->envm_size);
110 memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
111 memory_region_add_subregion(system_memory, 0, nvm_alias);
113 memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
114 &error_fatal);
115 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
117 armv7m = DEVICE(&s->armv7m);
118 qdev_prop_set_uint32(armv7m, "num-irq", 81);
119 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
120 qdev_prop_set_bit(armv7m, "enable-bitband", true);
121 object_property_set_link(OBJECT(&s->armv7m), "memory",
122 OBJECT(get_system_memory()), &error_abort);
123 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
124 return;
127 if (!s->m3clk) {
128 error_setg(errp, "Invalid m3clk value");
129 error_append_hint(errp, "m3clk can not be zero\n");
130 return;
133 qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
134 qemu_allocate_irq(&do_sys_reset, NULL, 0));
136 system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
138 for (i = 0; i < MSF2_NUM_UARTS; i++) {
139 if (serial_hd(i)) {
140 serial_mm_init(get_system_memory(), uart_addr[i], 2,
141 qdev_get_gpio_in(armv7m, uart_irq[i]),
142 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
146 dev = DEVICE(&s->timer);
147 /* APB0 clock is the timer input clock */
148 qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
149 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
150 return;
152 busdev = SYS_BUS_DEVICE(dev);
153 sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
154 sysbus_connect_irq(busdev, 0,
155 qdev_get_gpio_in(armv7m, timer_irq[0]));
156 sysbus_connect_irq(busdev, 1,
157 qdev_get_gpio_in(armv7m, timer_irq[1]));
159 dev = DEVICE(&s->sysreg);
160 qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
161 qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
162 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp)) {
163 return;
165 busdev = SYS_BUS_DEVICE(dev);
166 sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
168 for (i = 0; i < MSF2_NUM_SPIS; i++) {
169 gchar *bus_name;
171 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
172 return;
175 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
176 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
177 qdev_get_gpio_in(armv7m, spi_irq[i]));
179 /* Alias controller SPI bus to the SoC itself */
180 bus_name = g_strdup_printf("spi%d", i);
181 object_property_add_alias(OBJECT(s), bus_name,
182 OBJECT(&s->spi[i]), "spi");
183 g_free(bus_name);
186 /* FIXME use qdev NIC properties instead of nd_table[] */
187 if (nd_table[0].used) {
188 qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
189 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
191 dev = DEVICE(&s->emac);
192 object_property_set_link(OBJECT(&s->emac), "ahb-bus",
193 OBJECT(get_system_memory()), &error_abort);
194 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
195 return;
197 busdev = SYS_BUS_DEVICE(dev);
198 sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE);
199 sysbus_connect_irq(busdev, 0,
200 qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ));
202 /* Below devices are not modelled yet. */
203 create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
204 create_unimplemented_device("dma", 0x40003000, 0x1000);
205 create_unimplemented_device("watchdog", 0x40005000, 0x1000);
206 create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
207 create_unimplemented_device("gpio", 0x40013000, 0x1000);
208 create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
209 create_unimplemented_device("can", 0x40015000, 0x1000);
210 create_unimplemented_device("rtc", 0x40017000, 0x1000);
211 create_unimplemented_device("apb_config", 0x40020000, 0x10000);
212 create_unimplemented_device("usb", 0x40043000, 0x1000);
215 static Property m2sxxx_soc_properties[] = {
217 * part name specifies the type of SmartFusion2 device variant(this
218 * property is for information purpose only.
220 DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
221 DEFINE_PROP_STRING("part-name", MSF2State, part_name),
222 DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
223 DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
224 MSF2_ESRAM_MAX_SIZE),
225 /* Libero GUI shows 100Mhz as default for clocks */
226 DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
227 /* default divisors in Libero GUI */
228 DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
229 DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
230 DEFINE_PROP_END_OF_LIST(),
233 static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
235 DeviceClass *dc = DEVICE_CLASS(klass);
237 dc->realize = m2sxxx_soc_realize;
238 device_class_set_props(dc, m2sxxx_soc_properties);
241 static const TypeInfo m2sxxx_soc_info = {
242 .name = TYPE_MSF2_SOC,
243 .parent = TYPE_SYS_BUS_DEVICE,
244 .instance_size = sizeof(MSF2State),
245 .instance_init = m2sxxx_soc_initfn,
246 .class_init = m2sxxx_soc_class_init,
249 static void m2sxxx_soc_types(void)
251 type_register_static(&m2sxxx_soc_info);
254 type_init(m2sxxx_soc_types)