2 * Xilinx Versal SoC model.
4 * Copyright (c) 2018 Xilinx Inc.
5 * Written by Edgar E. Iglesias
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
15 #include "qemu/module.h"
16 #include "hw/sysbus.h"
18 #include "sysemu/sysemu.h"
19 #include "sysemu/kvm.h"
20 #include "hw/arm/boot.h"
22 #include "hw/misc/unimp.h"
23 #include "hw/arm/xlnx-versal.h"
25 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
26 #define GEM_REVISION 0x40070106
28 static void versal_create_apu_cpus(Versal
*s
)
32 for (i
= 0; i
< ARRAY_SIZE(s
->fpd
.apu
.cpu
); i
++) {
35 object_initialize_child(OBJECT(s
), "apu-cpu[*]", &s
->fpd
.apu
.cpu
[i
],
36 XLNX_VERSAL_ACPU_TYPE
);
37 obj
= OBJECT(&s
->fpd
.apu
.cpu
[i
]);
38 object_property_set_int(obj
, "psci-conduit", s
->cfg
.psci_conduit
,
41 /* Secondary CPUs start in PSCI powered-down state */
42 object_property_set_bool(obj
, "start-powered-off", true,
46 object_property_set_int(obj
, "core-count", ARRAY_SIZE(s
->fpd
.apu
.cpu
),
48 object_property_set_link(obj
, "memory", OBJECT(&s
->fpd
.apu
.mr
),
50 qdev_realize(DEVICE(obj
), NULL
, &error_fatal
);
54 static void versal_create_apu_gic(Versal
*s
, qemu_irq
*pic
)
56 static const uint64_t addrs
[] = {
60 SysBusDevice
*gicbusdev
;
62 int nr_apu_cpus
= ARRAY_SIZE(s
->fpd
.apu
.cpu
);
65 object_initialize_child(OBJECT(s
), "apu-gic", &s
->fpd
.apu
.gic
,
67 gicbusdev
= SYS_BUS_DEVICE(&s
->fpd
.apu
.gic
);
68 gicdev
= DEVICE(&s
->fpd
.apu
.gic
);
69 qdev_prop_set_uint32(gicdev
, "revision", 3);
70 qdev_prop_set_uint32(gicdev
, "num-cpu", 2);
71 qdev_prop_set_uint32(gicdev
, "num-irq", XLNX_VERSAL_NR_IRQS
+ 32);
72 qdev_prop_set_uint32(gicdev
, "len-redist-region-count", 1);
73 qdev_prop_set_uint32(gicdev
, "redist-region-count[0]", 2);
74 qdev_prop_set_bit(gicdev
, "has-security-extensions", true);
76 sysbus_realize(SYS_BUS_DEVICE(&s
->fpd
.apu
.gic
), &error_fatal
);
78 for (i
= 0; i
< ARRAY_SIZE(addrs
); i
++) {
81 mr
= sysbus_mmio_get_region(gicbusdev
, i
);
82 memory_region_add_subregion(&s
->fpd
.apu
.mr
, addrs
[i
], mr
);
85 for (i
= 0; i
< nr_apu_cpus
; i
++) {
86 DeviceState
*cpudev
= DEVICE(&s
->fpd
.apu
.cpu
[i
]);
87 int ppibase
= XLNX_VERSAL_NR_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
90 /* Mapping from the output timer irq lines from the CPU to the
93 const int timer_irq
[] = {
94 [GTIMER_PHYS
] = VERSAL_TIMER_NS_EL1_IRQ
,
95 [GTIMER_VIRT
] = VERSAL_TIMER_VIRT_IRQ
,
96 [GTIMER_HYP
] = VERSAL_TIMER_NS_EL2_IRQ
,
97 [GTIMER_SEC
] = VERSAL_TIMER_S_EL1_IRQ
,
100 for (ti
= 0; ti
< ARRAY_SIZE(timer_irq
); ti
++) {
101 qdev_connect_gpio_out(cpudev
, ti
,
102 qdev_get_gpio_in(gicdev
,
103 ppibase
+ timer_irq
[ti
]));
105 maint_irq
= qdev_get_gpio_in(gicdev
,
106 ppibase
+ VERSAL_GIC_MAINT_IRQ
);
107 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
109 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
110 sysbus_connect_irq(gicbusdev
, i
+ nr_apu_cpus
,
111 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
112 sysbus_connect_irq(gicbusdev
, i
+ 2 * nr_apu_cpus
,
113 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
114 sysbus_connect_irq(gicbusdev
, i
+ 3 * nr_apu_cpus
,
115 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
118 for (i
= 0; i
< XLNX_VERSAL_NR_IRQS
; i
++) {
119 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
123 static void versal_create_uarts(Versal
*s
, qemu_irq
*pic
)
127 for (i
= 0; i
< ARRAY_SIZE(s
->lpd
.iou
.uart
); i
++) {
128 static const int irqs
[] = { VERSAL_UART0_IRQ_0
, VERSAL_UART1_IRQ_0
};
129 static const uint64_t addrs
[] = { MM_UART0
, MM_UART1
};
130 char *name
= g_strdup_printf("uart%d", i
);
134 object_initialize_child(OBJECT(s
), name
, &s
->lpd
.iou
.uart
[i
],
136 dev
= DEVICE(&s
->lpd
.iou
.uart
[i
]);
137 qdev_prop_set_chr(dev
, "chardev", serial_hd(i
));
138 sysbus_realize(SYS_BUS_DEVICE(dev
), &error_fatal
);
140 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
141 memory_region_add_subregion(&s
->mr_ps
, addrs
[i
], mr
);
143 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[irqs
[i
]]);
148 static void versal_create_gems(Versal
*s
, qemu_irq
*pic
)
152 for (i
= 0; i
< ARRAY_SIZE(s
->lpd
.iou
.gem
); i
++) {
153 static const int irqs
[] = { VERSAL_GEM0_IRQ_0
, VERSAL_GEM1_IRQ_0
};
154 static const uint64_t addrs
[] = { MM_GEM0
, MM_GEM1
};
155 char *name
= g_strdup_printf("gem%d", i
);
156 NICInfo
*nd
= &nd_table
[i
];
160 object_initialize_child(OBJECT(s
), name
, &s
->lpd
.iou
.gem
[i
],
162 dev
= DEVICE(&s
->lpd
.iou
.gem
[i
]);
163 /* FIXME use qdev NIC properties instead of nd_table[] */
165 qemu_check_nic_model(nd
, "cadence_gem");
166 qdev_set_nic_properties(dev
, nd
);
168 object_property_set_int(OBJECT(dev
), "num-priority-queues", 2,
170 object_property_set_link(OBJECT(dev
), "dma", OBJECT(&s
->mr_ps
),
172 sysbus_realize(SYS_BUS_DEVICE(dev
), &error_fatal
);
174 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
175 memory_region_add_subregion(&s
->mr_ps
, addrs
[i
], mr
);
177 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[irqs
[i
]]);
182 static void versal_create_admas(Versal
*s
, qemu_irq
*pic
)
186 for (i
= 0; i
< ARRAY_SIZE(s
->lpd
.iou
.adma
); i
++) {
187 char *name
= g_strdup_printf("adma%d", i
);
191 object_initialize_child(OBJECT(s
), name
, &s
->lpd
.iou
.adma
[i
],
193 dev
= DEVICE(&s
->lpd
.iou
.adma
[i
]);
194 object_property_set_int(OBJECT(dev
), "bus-width", 128, &error_abort
);
195 sysbus_realize(SYS_BUS_DEVICE(dev
), &error_fatal
);
197 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
198 memory_region_add_subregion(&s
->mr_ps
,
199 MM_ADMA_CH0
+ i
* MM_ADMA_CH0_SIZE
, mr
);
201 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[VERSAL_ADMA_IRQ_0
+ i
]);
206 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */
207 static void versal_create_sds(Versal
*s
, qemu_irq
*pic
)
211 for (i
= 0; i
< ARRAY_SIZE(s
->pmc
.iou
.sd
); i
++) {
215 object_initialize_child(OBJECT(s
), "sd[*]", &s
->pmc
.iou
.sd
[i
],
217 dev
= DEVICE(&s
->pmc
.iou
.sd
[i
]);
219 object_property_set_uint(OBJECT(dev
), "sd-spec-version", 3,
221 object_property_set_uint(OBJECT(dev
), "capareg", SDHCI_CAPABILITIES
,
223 object_property_set_uint(OBJECT(dev
), "uhs", UHS_I
, &error_fatal
);
224 sysbus_realize(SYS_BUS_DEVICE(dev
), &error_fatal
);
226 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
227 memory_region_add_subregion(&s
->mr_ps
,
228 MM_PMC_SD0
+ i
* MM_PMC_SD0_SIZE
, mr
);
230 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0,
231 pic
[VERSAL_SD0_IRQ_0
+ i
* 2]);
235 static void versal_create_rtc(Versal
*s
, qemu_irq
*pic
)
240 object_initialize_child(OBJECT(s
), "rtc", &s
->pmc
.rtc
,
241 TYPE_XLNX_ZYNQMP_RTC
);
242 sbd
= SYS_BUS_DEVICE(&s
->pmc
.rtc
);
243 sysbus_realize(SYS_BUS_DEVICE(sbd
), &error_fatal
);
245 mr
= sysbus_mmio_get_region(sbd
, 0);
246 memory_region_add_subregion(&s
->mr_ps
, MM_PMC_RTC
, mr
);
249 * TODO: Connect the ALARM and SECONDS interrupts once our RTC model
252 sysbus_connect_irq(sbd
, 1, pic
[VERSAL_RTC_APB_ERR_IRQ
]);
255 /* This takes the board allocated linear DDR memory and creates aliases
256 * for each split DDR range/aperture on the Versal address map.
258 static void versal_map_ddr(Versal
*s
)
260 uint64_t size
= memory_region_size(s
->cfg
.mr_ddr
);
261 /* Describes the various split DDR access regions. */
262 static const struct {
266 { MM_TOP_DDR
, MM_TOP_DDR_SIZE
},
267 { MM_TOP_DDR_2
, MM_TOP_DDR_2_SIZE
},
268 { MM_TOP_DDR_3
, MM_TOP_DDR_3_SIZE
},
269 { MM_TOP_DDR_4
, MM_TOP_DDR_4_SIZE
}
274 assert(ARRAY_SIZE(addr_ranges
) == ARRAY_SIZE(s
->noc
.mr_ddr_ranges
));
275 for (i
= 0; i
< ARRAY_SIZE(addr_ranges
) && size
; i
++) {
279 mapsize
= size
< addr_ranges
[i
].size
? size
: addr_ranges
[i
].size
;
280 name
= g_strdup_printf("noc-ddr-range%d", i
);
281 /* Create the MR alias. */
282 memory_region_init_alias(&s
->noc
.mr_ddr_ranges
[i
], OBJECT(s
),
286 /* Map it onto the NoC MR. */
287 memory_region_add_subregion(&s
->mr_ps
, addr_ranges
[i
].base
,
288 &s
->noc
.mr_ddr_ranges
[i
]);
295 static void versal_unimp_area(Versal
*s
, const char *name
,
297 hwaddr base
, hwaddr size
)
299 DeviceState
*dev
= qdev_new(TYPE_UNIMPLEMENTED_DEVICE
);
300 MemoryRegion
*mr_dev
;
302 qdev_prop_set_string(dev
, "name", name
);
303 qdev_prop_set_uint64(dev
, "size", size
);
304 object_property_add_child(OBJECT(s
), name
, OBJECT(dev
));
305 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
307 mr_dev
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
308 memory_region_add_subregion(mr
, base
, mr_dev
);
311 static void versal_unimp(Versal
*s
)
313 versal_unimp_area(s
, "psm", &s
->mr_ps
,
314 MM_PSM_START
, MM_PSM_END
- MM_PSM_START
);
315 versal_unimp_area(s
, "crl", &s
->mr_ps
,
316 MM_CRL
, MM_CRL_SIZE
);
317 versal_unimp_area(s
, "crf", &s
->mr_ps
,
318 MM_FPD_CRF
, MM_FPD_CRF_SIZE
);
319 versal_unimp_area(s
, "crp", &s
->mr_ps
,
320 MM_PMC_CRP
, MM_PMC_CRP_SIZE
);
321 versal_unimp_area(s
, "iou-scntr", &s
->mr_ps
,
322 MM_IOU_SCNTR
, MM_IOU_SCNTR_SIZE
);
323 versal_unimp_area(s
, "iou-scntr-seucre", &s
->mr_ps
,
324 MM_IOU_SCNTRS
, MM_IOU_SCNTRS_SIZE
);
327 static void versal_realize(DeviceState
*dev
, Error
**errp
)
329 Versal
*s
= XLNX_VERSAL(dev
);
330 qemu_irq pic
[XLNX_VERSAL_NR_IRQS
];
332 versal_create_apu_cpus(s
);
333 versal_create_apu_gic(s
, pic
);
334 versal_create_uarts(s
, pic
);
335 versal_create_gems(s
, pic
);
336 versal_create_admas(s
, pic
);
337 versal_create_sds(s
, pic
);
338 versal_create_rtc(s
, pic
);
342 /* Create the On Chip Memory (OCM). */
343 memory_region_init_ram(&s
->lpd
.mr_ocm
, OBJECT(s
), "ocm",
344 MM_OCM_SIZE
, &error_fatal
);
346 memory_region_add_subregion_overlap(&s
->mr_ps
, MM_OCM
, &s
->lpd
.mr_ocm
, 0);
347 memory_region_add_subregion_overlap(&s
->fpd
.apu
.mr
, 0, &s
->mr_ps
, 0);
350 static void versal_init(Object
*obj
)
352 Versal
*s
= XLNX_VERSAL(obj
);
354 memory_region_init(&s
->fpd
.apu
.mr
, obj
, "mr-apu", UINT64_MAX
);
355 memory_region_init(&s
->mr_ps
, obj
, "mr-ps-switch", UINT64_MAX
);
358 static Property versal_properties
[] = {
359 DEFINE_PROP_LINK("ddr", Versal
, cfg
.mr_ddr
, TYPE_MEMORY_REGION
,
361 DEFINE_PROP_UINT32("psci-conduit", Versal
, cfg
.psci_conduit
, 0),
362 DEFINE_PROP_END_OF_LIST()
365 static void versal_class_init(ObjectClass
*klass
, void *data
)
367 DeviceClass
*dc
= DEVICE_CLASS(klass
);
369 dc
->realize
= versal_realize
;
370 device_class_set_props(dc
, versal_properties
);
371 /* No VMSD since we haven't got any top-level SoC state to save. */
374 static const TypeInfo versal_info
= {
375 .name
= TYPE_XLNX_VERSAL
,
376 .parent
= TYPE_SYS_BUS_DEVICE
,
377 .instance_size
= sizeof(Versal
),
378 .instance_init
= versal_init
,
379 .class_init
= versal_class_init
,
382 static void versal_register_types(void)
384 type_register_static(&versal_info
);
387 type_init(versal_register_types
);