hw/net/mipsnet.c

   1 #include "qemu/osdep.h"
   2 #include "hw/irq.h"
   3 #include "hw/qdev-properties.h"
   4 #include "net/net.h"
   5 #include "qemu/module.h"
   6 #include "trace.h"
   7 #include "hw/sysbus.h"
   8 #include "migration/vmstate.h"
   9
  10 /* MIPSnet register offsets */
  11
  12 #define MIPSNET_DEV_ID          0x00
  13 #define MIPSNET_BUSY            0x08
  14 #define MIPSNET_RX_DATA_COUNT   0x0c
  15 #define MIPSNET_TX_DATA_COUNT   0x10
  16 #define MIPSNET_INT_CTL         0x14
  17 # define MIPSNET_INTCTL_TXDONE          0x00000001
  18 # define MIPSNET_INTCTL_RXDONE          0x00000002
  19 # define MIPSNET_INTCTL_TESTBIT         0x80000000
  20 #define MIPSNET_INTERRUPT_INFO  0x18
  21 #define MIPSNET_RX_DATA_BUFFER  0x1c
  22 #define MIPSNET_TX_DATA_BUFFER  0x20
  23
  24 #define MAX_ETH_FRAME_SIZE      1514
  25
  26 #define TYPE_MIPS_NET "mipsnet"
  27 #define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET)
  28
  29 typedef struct MIPSnetState {
  30     SysBusDevice parent_obj;
  31
  32     uint32_t busy;
  33     uint32_t rx_count;
  34     uint32_t rx_read;
  35     uint32_t tx_count;
  36     uint32_t tx_written;
  37     uint32_t intctl;
  38     uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
  39     uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
  40     MemoryRegion io;
  41     qemu_irq irq;
  42     NICState *nic;
  43     NICConf conf;
  44 } MIPSnetState;
  45
  46 static void mipsnet_reset(MIPSnetState *s)
  47 {
  48     s->busy = 1;
  49     s->rx_count = 0;
  50     s->rx_read = 0;
  51     s->tx_count = 0;
  52     s->tx_written = 0;
  53     s->intctl = 0;
  54     memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
  55     memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
  56 }
  57
  58 static void mipsnet_update_irq(MIPSnetState *s)
  59 {
  60     int isr = !!s->intctl;
  61     trace_mipsnet_irq(isr, s->intctl);
  62     qemu_set_irq(s->irq, isr);
  63 }
  64
  65 static int mipsnet_buffer_full(MIPSnetState *s)
  66 {
  67     if (s->rx_count >= MAX_ETH_FRAME_SIZE) {
  68         return 1;
  69     }
  70     return 0;
  71 }
  72
  73 static int mipsnet_can_receive(NetClientState *nc)
  74 {
  75     MIPSnetState *s = qemu_get_nic_opaque(nc);
  76
  77     if (s->busy) {
  78         return 0;
  79     }
  80     return !mipsnet_buffer_full(s);
  81 }
  82
  83 static ssize_t mipsnet_receive(NetClientState *nc,
  84                                const uint8_t *buf, size_t size)
  85 {
  86     MIPSnetState *s = qemu_get_nic_opaque(nc);
  87
  88     trace_mipsnet_receive(size);
  89     if (!mipsnet_can_receive(nc)) {
  90         return 0;
  91     }
  92
  93     if (size >= sizeof(s->rx_buffer)) {
  94         return 0;
  95     }
  96     s->busy = 1;
  97
  98     /* Just accept everything. */
  99
 100     /* Write packet data. */
 101     memcpy(s->rx_buffer, buf, size);
 102
 103     s->rx_count = size;
 104     s->rx_read = 0;
 105
 106     /* Now we can signal we have received something. */
 107     s->intctl |= MIPSNET_INTCTL_RXDONE;
 108     mipsnet_update_irq(s);
 109
 110     return size;
 111 }
 112
 113 static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
 114                                     unsigned int size)
 115 {
 116     MIPSnetState *s = opaque;
 117     int ret = 0;
 118
 119     addr &= 0x3f;
 120     switch (addr) {
 121     case MIPSNET_DEV_ID:
 122         ret = be32_to_cpu(0x4d495053);          /* MIPS */
 123         break;
 124     case MIPSNET_DEV_ID + 4:
 125         ret = be32_to_cpu(0x4e455430);          /* NET0 */
 126         break;
 127     case MIPSNET_BUSY:
 128         ret = s->busy;
 129         break;
 130     case MIPSNET_RX_DATA_COUNT:
 131         ret = s->rx_count;
 132         break;
 133     case MIPSNET_TX_DATA_COUNT:
 134         ret = s->tx_count;
 135         break;
 136     case MIPSNET_INT_CTL:
 137         ret = s->intctl;
 138         s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
 139         break;
 140     case MIPSNET_INTERRUPT_INFO:
 141         /* XXX: This seems to be a per-VPE interrupt number. */
 142         ret = 0;
 143         break;
 144     case MIPSNET_RX_DATA_BUFFER:
 145         if (s->rx_count) {
 146             s->rx_count--;
 147             ret = s->rx_buffer[s->rx_read++];
 148             if (mipsnet_can_receive(s->nic->ncs)) {
 149                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
 150             }
 151         }
 152         break;
 153     /* Reads as zero. */
 154     case MIPSNET_TX_DATA_BUFFER:
 155     default:
 156         break;
 157     }
 158     trace_mipsnet_read(addr, ret);
 159     return ret;
 160 }
 161
 162 static void mipsnet_ioport_write(void *opaque, hwaddr addr,
 163                                  uint64_t val, unsigned int size)
 164 {
 165     MIPSnetState *s = opaque;
 166
 167     addr &= 0x3f;
 168     trace_mipsnet_write(addr, val);
 169     switch (addr) {
 170     case MIPSNET_TX_DATA_COUNT:
 171         s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
 172         s->tx_written = 0;
 173         break;
 174     case MIPSNET_INT_CTL:
 175         if (val & MIPSNET_INTCTL_TXDONE) {
 176             s->intctl &= ~MIPSNET_INTCTL_TXDONE;
 177         } else if (val & MIPSNET_INTCTL_RXDONE) {
 178             s->intctl &= ~MIPSNET_INTCTL_RXDONE;
 179         } else if (val & MIPSNET_INTCTL_TESTBIT) {
 180             mipsnet_reset(s);
 181             s->intctl |= MIPSNET_INTCTL_TESTBIT;
 182         } else if (!val) {
 183             /* ACK testbit interrupt, flag was cleared on read. */
 184         }
 185         s->busy = !!s->intctl;
 186         mipsnet_update_irq(s);
 187         if (mipsnet_can_receive(s->nic->ncs)) {
 188             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 189         }
 190         break;
 191     case MIPSNET_TX_DATA_BUFFER:
 192         s->tx_buffer[s->tx_written++] = val;
 193         if ((s->tx_written >= MAX_ETH_FRAME_SIZE)
 194             || (s->tx_written == s->tx_count)) {
 195             /* Send buffer. */
 196             trace_mipsnet_send(s->tx_written);
 197             qemu_send_packet(qemu_get_queue(s->nic),
 198                                 s->tx_buffer, s->tx_written);
 199             s->tx_count = s->tx_written = 0;
 200             s->intctl |= MIPSNET_INTCTL_TXDONE;
 201             s->busy = 1;
 202             mipsnet_update_irq(s);
 203         }
 204         break;
 205     /* Read-only registers */
 206     case MIPSNET_DEV_ID:
 207     case MIPSNET_BUSY:
 208     case MIPSNET_RX_DATA_COUNT:
 209     case MIPSNET_INTERRUPT_INFO:
 210     case MIPSNET_RX_DATA_BUFFER:
 211     default:
 212         break;
 213     }
 214 }
 215
 216 static const VMStateDescription vmstate_mipsnet = {
 217     .name = "mipsnet",
 218     .version_id = 0,
 219     .minimum_version_id = 0,
 220     .fields = (VMStateField[]) {
 221         VMSTATE_UINT32(busy, MIPSnetState),
 222         VMSTATE_UINT32(rx_count, MIPSnetState),
 223         VMSTATE_UINT32(rx_read, MIPSnetState),
 224         VMSTATE_UINT32(tx_count, MIPSnetState),
 225         VMSTATE_UINT32(tx_written, MIPSnetState),
 226         VMSTATE_UINT32(intctl, MIPSnetState),
 227         VMSTATE_BUFFER(rx_buffer, MIPSnetState),
 228         VMSTATE_BUFFER(tx_buffer, MIPSnetState),
 229         VMSTATE_END_OF_LIST()
 230     }
 231 };
 232
 233 static NetClientInfo net_mipsnet_info = {
 234     .type = NET_CLIENT_DRIVER_NIC,
 235     .size = sizeof(NICState),
 236     .receive = mipsnet_receive,
 237 };
 238
 239 static const MemoryRegionOps mipsnet_ioport_ops = {
 240     .read = mipsnet_ioport_read,
 241     .write = mipsnet_ioport_write,
 242     .impl.min_access_size = 1,
 243     .impl.max_access_size = 4,
 244 };
 245
 246 static void mipsnet_realize(DeviceState *dev, Error **errp)
 247 {
 248     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 249     MIPSnetState *s = MIPS_NET(dev);
 250
 251     memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s,
 252                           "mipsnet-io", 36);
 253     sysbus_init_mmio(sbd, &s->io);
 254     sysbus_init_irq(sbd, &s->irq);
 255
 256     s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
 257                           object_get_typename(OBJECT(dev)), dev->id, s);
 258     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 259 }
 260
 261 static void mipsnet_sysbus_reset(DeviceState *dev)
 262 {
 263     MIPSnetState *s = MIPS_NET(dev);
 264     mipsnet_reset(s);
 265 }
 266
 267 static Property mipsnet_properties[] = {
 268     DEFINE_NIC_PROPERTIES(MIPSnetState, conf),
 269     DEFINE_PROP_END_OF_LIST(),
 270 };
 271
 272 static void mipsnet_class_init(ObjectClass *klass, void *data)
 273 {
 274     DeviceClass *dc = DEVICE_CLASS(klass);
 275
 276     dc->realize = mipsnet_realize;
 277     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 278     dc->desc = "MIPS Simulator network device";
 279     dc->reset = mipsnet_sysbus_reset;
 280     dc->vmsd = &vmstate_mipsnet;
 281     device_class_set_props(dc, mipsnet_properties);
 282 }
 283
 284 static const TypeInfo mipsnet_info = {
 285     .name          = TYPE_MIPS_NET,
 286     .parent        = TYPE_SYS_BUS_DEVICE,
 287     .instance_size = sizeof(MIPSnetState),
 288     .class_init    = mipsnet_class_init,
 289 };
 290
 291 static void mipsnet_register_types(void)
 292 {
 293     type_register_static(&mipsnet_info);
 294 }
 295
 296 type_init(mipsnet_register_types)