hw/pci-host/uninorth.c

   1 /*
   2  * QEMU Uninorth PCI host (for all Mac99 and newer machines)
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/irq.h"
  27 #include "hw/ppc/mac.h"
  28 #include "hw/qdev-properties.h"
  29 #include "qemu/module.h"
  30 #include "hw/pci/pci.h"
  31 #include "hw/pci/pci_host.h"
  32 #include "hw/pci-host/uninorth.h"
  33 #include "trace.h"
  34
  35 static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
  36
  37 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
  38 {
  39     return (irq_num + (pci_dev->devfn >> 3)) & 3;
  40 }
  41
  42 static void pci_unin_set_irq(void *opaque, int irq_num, int level)
  43 {
  44     UNINHostState *s = opaque;
  45
  46     trace_unin_set_irq(unin_irq_line[irq_num], level);
  47     qemu_set_irq(s->irqs[irq_num], level);
  48 }
  49
  50 static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
  51 {
  52     uint32_t retval;
  53
  54     if (reg & (1u << 31)) {
  55         /* XXX OpenBIOS compatibility hack */
  56         retval = reg | (addr & 3);
  57     } else if (reg & 1) {
  58         /* CFA1 style */
  59         retval = (reg & ~7u) | (addr & 7);
  60     } else {
  61         uint32_t slot, func;
  62
  63         /* Grab CFA0 style values */
  64         slot = ctz32(reg & 0xfffff800);
  65         if (slot == 32) {
  66             slot = -1; /* XXX: should this be 0? */
  67         }
  68         func = (reg >> 8) & 7;
  69
  70         /* ... and then convert them to x86 format */
  71         /* config pointer */
  72         retval = (reg & (0xff - 7)) | (addr & 7);
  73         /* slot */
  74         retval |= slot << 11;
  75         /* fn */
  76         retval |= func << 8;
  77     }
  78
  79     trace_unin_get_config_reg(reg, addr, retval);
  80
  81     return retval;
  82 }
  83
  84 static void unin_data_write(void *opaque, hwaddr addr,
  85                             uint64_t val, unsigned len)
  86 {
  87     UNINHostState *s = opaque;
  88     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  89     trace_unin_data_write(addr, len, val);
  90     pci_data_write(phb->bus,
  91                    unin_get_config_reg(phb->config_reg, addr),
  92                    val, len);
  93 }
  94
  95 static uint64_t unin_data_read(void *opaque, hwaddr addr,
  96                                unsigned len)
  97 {
  98     UNINHostState *s = opaque;
  99     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 100     uint32_t val;
 101
 102     val = pci_data_read(phb->bus,
 103                         unin_get_config_reg(phb->config_reg, addr),
 104                         len);
 105     trace_unin_data_read(addr, len, val);
 106     return val;
 107 }
 108
 109 static const MemoryRegionOps unin_data_ops = {
 110     .read = unin_data_read,
 111     .write = unin_data_write,
 112     .endianness = DEVICE_LITTLE_ENDIAN,
 113 };
 114
 115 static void pci_unin_init_irqs(UNINHostState *s)
 116 {
 117     int i;
 118
 119     for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
 120         s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]);
 121     }
 122 }
 123
 124 static char *pci_unin_main_ofw_unit_address(const SysBusDevice *dev)
 125 {
 126     UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
 127
 128     return g_strdup_printf("%x", s->ofw_addr);
 129 }
 130
 131 static void pci_unin_main_realize(DeviceState *dev, Error **errp)
 132 {
 133     UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
 134     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 135
 136     h->bus = pci_register_root_bus(dev, NULL,
 137                                    pci_unin_set_irq, pci_unin_map_irq,
 138                                    s,
 139                                    &s->pci_mmio,
 140                                    &s->pci_io,
 141                                    PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
 142
 143     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
 144     pci_unin_init_irqs(s);
 145
 146     /* DEC 21154 bridge */
 147 #if 0
 148     /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
 149     pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
 150 #endif
 151 }
 152
 153 static void pci_unin_main_init(Object *obj)
 154 {
 155     UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj);
 156     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 157     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 158
 159     /* Use values found on a real PowerMac */
 160     /* Uninorth main bus */
 161     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
 162                           obj, "unin-pci-conf-idx", 0x1000);
 163     memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
 164                           "unin-pci-conf-data", 0x1000);
 165
 166     memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
 167                        0x100000000ULL);
 168     memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
 169                           "unin-pci-isa-mmio", 0x00800000);
 170
 171     memory_region_init_alias(&s->pci_hole, OBJECT(s),
 172                              "unin-pci-hole", &s->pci_mmio,
 173                              0x80000000ULL, 0x10000000ULL);
 174
 175     object_property_add_link(obj, "pic", TYPE_OPENPIC,
 176                              (Object **) &s->pic,
 177                              qdev_prop_allow_set_link_before_realize,
 178                              0);
 179
 180     sysbus_init_mmio(sbd, &h->conf_mem);
 181     sysbus_init_mmio(sbd, &h->data_mem);
 182     sysbus_init_mmio(sbd, &s->pci_hole);
 183     sysbus_init_mmio(sbd, &s->pci_io);
 184 }
 185
 186 static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
 187 {
 188     UNINHostState *s = U3_AGP_HOST_BRIDGE(dev);
 189     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 190
 191     h->bus = pci_register_root_bus(dev, NULL,
 192                                    pci_unin_set_irq, pci_unin_map_irq,
 193                                    s,
 194                                    &s->pci_mmio,
 195                                    &s->pci_io,
 196                                    PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
 197
 198     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
 199     pci_unin_init_irqs(s);
 200 }
 201
 202 static void pci_u3_agp_init(Object *obj)
 203 {
 204     UNINHostState *s = U3_AGP_HOST_BRIDGE(obj);
 205     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 206     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 207
 208     /* Uninorth U3 AGP bus */
 209     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
 210                           obj, "unin-pci-conf-idx", 0x1000);
 211     memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
 212                           "unin-pci-conf-data", 0x1000);
 213
 214     memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
 215                        0x100000000ULL);
 216     memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
 217                           "unin-pci-isa-mmio", 0x00800000);
 218
 219     memory_region_init_alias(&s->pci_hole, OBJECT(s),
 220                              "unin-pci-hole", &s->pci_mmio,
 221                              0x80000000ULL, 0x70000000ULL);
 222
 223     object_property_add_link(obj, "pic", TYPE_OPENPIC,
 224                              (Object **) &s->pic,
 225                              qdev_prop_allow_set_link_before_realize,
 226                              0);
 227
 228     sysbus_init_mmio(sbd, &h->conf_mem);
 229     sysbus_init_mmio(sbd, &h->data_mem);
 230     sysbus_init_mmio(sbd, &s->pci_hole);
 231     sysbus_init_mmio(sbd, &s->pci_io);
 232 }
 233
 234 static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
 235 {
 236     UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev);
 237     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 238
 239     h->bus = pci_register_root_bus(dev, NULL,
 240                                    pci_unin_set_irq, pci_unin_map_irq,
 241                                    s,
 242                                    &s->pci_mmio,
 243                                    &s->pci_io,
 244                                    PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
 245
 246     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
 247     pci_unin_init_irqs(s);
 248 }
 249
 250 static void pci_unin_agp_init(Object *obj)
 251 {
 252     UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj);
 253     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 254     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 255
 256     /* Uninorth AGP bus */
 257     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
 258                           obj, "unin-agp-conf-idx", 0x1000);
 259     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
 260                           obj, "unin-agp-conf-data", 0x1000);
 261
 262     object_property_add_link(obj, "pic", TYPE_OPENPIC,
 263                              (Object **) &s->pic,
 264                              qdev_prop_allow_set_link_before_realize,
 265                              0);
 266
 267     sysbus_init_mmio(sbd, &h->conf_mem);
 268     sysbus_init_mmio(sbd, &h->data_mem);
 269 }
 270
 271 static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
 272 {
 273     UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev);
 274     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 275
 276     h->bus = pci_register_root_bus(dev, NULL,
 277                                    pci_unin_set_irq, pci_unin_map_irq,
 278                                    s,
 279                                    &s->pci_mmio,
 280                                    &s->pci_io,
 281                                    PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);
 282
 283     pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
 284     pci_unin_init_irqs(s);
 285 }
 286
 287 static void pci_unin_internal_init(Object *obj)
 288 {
 289     UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj);
 290     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 291     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 292
 293     /* Uninorth internal bus */
 294     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
 295                           obj, "unin-pci-conf-idx", 0x1000);
 296     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
 297                           obj, "unin-pci-conf-data", 0x1000);
 298
 299     object_property_add_link(obj, "pic", TYPE_OPENPIC,
 300                              (Object **) &s->pic,
 301                              qdev_prop_allow_set_link_before_realize,
 302                              0);
 303
 304     sysbus_init_mmio(sbd, &h->conf_mem);
 305     sysbus_init_mmio(sbd, &h->data_mem);
 306 }
 307
 308 static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
 309 {
 310     /* cache_line_size */
 311     d->config[0x0C] = 0x08;
 312     /* latency_timer */
 313     d->config[0x0D] = 0x10;
 314     /* capabilities_pointer */
 315     d->config[0x34] = 0x00;
 316
 317     /*
 318      * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
 319      * memory space with base 0x80000000, size 0x10000000 for Apple's
 320      * AppleMacRiscPCI driver
 321      */
 322     d->config[0x48] = 0x0;
 323     d->config[0x49] = 0x0;
 324     d->config[0x4a] = 0x0;
 325     d->config[0x4b] = 0x1;
 326 }
 327
 328 static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
 329 {
 330     /* cache_line_size */
 331     d->config[0x0C] = 0x08;
 332     /* latency_timer */
 333     d->config[0x0D] = 0x10;
 334     /* capabilities_pointer
 335     d->config[0x34] = 0x80; */
 336 }
 337
 338 static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
 339 {
 340     /* cache line size */
 341     d->config[0x0C] = 0x08;
 342     /* latency timer */
 343     d->config[0x0D] = 0x10;
 344 }
 345
 346 static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
 347 {
 348     /* cache_line_size */
 349     d->config[0x0C] = 0x08;
 350     /* latency_timer */
 351     d->config[0x0D] = 0x10;
 352     /* capabilities_pointer */
 353     d->config[0x34] = 0x00;
 354 }
 355
 356 static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
 357 {
 358     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 359     DeviceClass *dc = DEVICE_CLASS(klass);
 360
 361     k->realize   = unin_main_pci_host_realize;
 362     k->vendor_id = PCI_VENDOR_ID_APPLE;
 363     k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
 364     k->revision  = 0x00;
 365     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 366     /*
 367      * PCI-facing part of the host bridge, not usable without the
 368      * host-facing part, which can't be device_add'ed, yet.
 369      */
 370     dc->user_creatable = false;
 371 }
 372
 373 static const TypeInfo unin_main_pci_host_info = {
 374     .name = "uni-north-pci",
 375     .parent = TYPE_PCI_DEVICE,
 376     .instance_size = sizeof(PCIDevice),
 377     .class_init = unin_main_pci_host_class_init,
 378     .interfaces = (InterfaceInfo[]) {
 379         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 380         { },
 381     },
 382 };
 383
 384 static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
 385 {
 386     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 387     DeviceClass *dc = DEVICE_CLASS(klass);
 388
 389     k->realize   = u3_agp_pci_host_realize;
 390     k->vendor_id = PCI_VENDOR_ID_APPLE;
 391     k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
 392     k->revision  = 0x00;
 393     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 394     /*
 395      * PCI-facing part of the host bridge, not usable without the
 396      * host-facing part, which can't be device_add'ed, yet.
 397      */
 398     dc->user_creatable = false;
 399 }
 400
 401 static const TypeInfo u3_agp_pci_host_info = {
 402     .name = "u3-agp",
 403     .parent = TYPE_PCI_DEVICE,
 404     .instance_size = sizeof(PCIDevice),
 405     .class_init = u3_agp_pci_host_class_init,
 406     .interfaces = (InterfaceInfo[]) {
 407         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 408         { },
 409     },
 410 };
 411
 412 static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
 413 {
 414     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 415     DeviceClass *dc = DEVICE_CLASS(klass);
 416
 417     k->realize   = unin_agp_pci_host_realize;
 418     k->vendor_id = PCI_VENDOR_ID_APPLE;
 419     k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
 420     k->revision  = 0x00;
 421     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 422     /*
 423      * PCI-facing part of the host bridge, not usable without the
 424      * host-facing part, which can't be device_add'ed, yet.
 425      */
 426     dc->user_creatable = false;
 427 }
 428
 429 static const TypeInfo unin_agp_pci_host_info = {
 430     .name = "uni-north-agp",
 431     .parent = TYPE_PCI_DEVICE,
 432     .instance_size = sizeof(PCIDevice),
 433     .class_init = unin_agp_pci_host_class_init,
 434     .interfaces = (InterfaceInfo[]) {
 435         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 436         { },
 437     },
 438 };
 439
 440 static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
 441 {
 442     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 443     DeviceClass *dc = DEVICE_CLASS(klass);
 444
 445     k->realize   = unin_internal_pci_host_realize;
 446     k->vendor_id = PCI_VENDOR_ID_APPLE;
 447     k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
 448     k->revision  = 0x00;
 449     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 450     /*
 451      * PCI-facing part of the host bridge, not usable without the
 452      * host-facing part, which can't be device_add'ed, yet.
 453      */
 454     dc->user_creatable = false;
 455 }
 456
 457 static const TypeInfo unin_internal_pci_host_info = {
 458     .name = "uni-north-internal-pci",
 459     .parent = TYPE_PCI_DEVICE,
 460     .instance_size = sizeof(PCIDevice),
 461     .class_init = unin_internal_pci_host_class_init,
 462     .interfaces = (InterfaceInfo[]) {
 463         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 464         { },
 465     },
 466 };
 467
 468 static Property pci_unin_main_pci_host_props[] = {
 469     DEFINE_PROP_UINT32("ofw-addr", UNINHostState, ofw_addr, -1),
 470     DEFINE_PROP_END_OF_LIST()
 471 };
 472
 473 static void pci_unin_main_class_init(ObjectClass *klass, void *data)
 474 {
 475     DeviceClass *dc = DEVICE_CLASS(klass);
 476     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 477
 478     dc->realize = pci_unin_main_realize;
 479     device_class_set_props(dc, pci_unin_main_pci_host_props);
 480     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 481     dc->fw_name = "pci";
 482     sbc->explicit_ofw_unit_address = pci_unin_main_ofw_unit_address;
 483 }
 484
 485 static const TypeInfo pci_unin_main_info = {
 486     .name          = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
 487     .parent        = TYPE_PCI_HOST_BRIDGE,
 488     .instance_size = sizeof(UNINHostState),
 489     .instance_init = pci_unin_main_init,
 490     .class_init    = pci_unin_main_class_init,
 491 };
 492
 493 static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
 494 {
 495     DeviceClass *dc = DEVICE_CLASS(klass);
 496
 497     dc->realize = pci_u3_agp_realize;
 498     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 499 }
 500
 501 static const TypeInfo pci_u3_agp_info = {
 502     .name          = TYPE_U3_AGP_HOST_BRIDGE,
 503     .parent        = TYPE_PCI_HOST_BRIDGE,
 504     .instance_size = sizeof(UNINHostState),
 505     .instance_init = pci_u3_agp_init,
 506     .class_init    = pci_u3_agp_class_init,
 507 };
 508
 509 static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
 510 {
 511     DeviceClass *dc = DEVICE_CLASS(klass);
 512
 513     dc->realize = pci_unin_agp_realize;
 514     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 515 }
 516
 517 static const TypeInfo pci_unin_agp_info = {
 518     .name          = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
 519     .parent        = TYPE_PCI_HOST_BRIDGE,
 520     .instance_size = sizeof(UNINHostState),
 521     .instance_init = pci_unin_agp_init,
 522     .class_init    = pci_unin_agp_class_init,
 523 };
 524
 525 static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
 526 {
 527     DeviceClass *dc = DEVICE_CLASS(klass);
 528
 529     dc->realize = pci_unin_internal_realize;
 530     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 531 }
 532
 533 static const TypeInfo pci_unin_internal_info = {
 534     .name          = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
 535     .parent        = TYPE_PCI_HOST_BRIDGE,
 536     .instance_size = sizeof(UNINHostState),
 537     .instance_init = pci_unin_internal_init,
 538     .class_init    = pci_unin_internal_class_init,
 539 };
 540
 541 /* UniN device */
 542 static void unin_write(void *opaque, hwaddr addr, uint64_t value,
 543                        unsigned size)
 544 {
 545     trace_unin_write(addr, value);
 546 }
 547
 548 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
 549 {
 550     uint32_t value;
 551
 552     switch (addr) {
 553     case 0:
 554         value = UNINORTH_VERSION_10A;
 555         break;
 556     default:
 557         value = 0;
 558     }
 559
 560     trace_unin_read(addr, value);
 561
 562     return value;
 563 }
 564
 565 static const MemoryRegionOps unin_ops = {
 566     .read = unin_read,
 567     .write = unin_write,
 568     .endianness = DEVICE_BIG_ENDIAN,
 569 };
 570
 571 static void unin_init(Object *obj)
 572 {
 573     UNINState *s = UNI_NORTH(obj);
 574     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 575
 576     memory_region_init_io(&s->mem, obj, &unin_ops, s, "unin", 0x1000);
 577
 578     sysbus_init_mmio(sbd, &s->mem);
 579 }
 580
 581 static void unin_class_init(ObjectClass *klass, void *data)
 582 {
 583     DeviceClass *dc = DEVICE_CLASS(klass);
 584
 585     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 586 }
 587
 588 static const TypeInfo unin_info = {
 589     .name          = TYPE_UNI_NORTH,
 590     .parent        = TYPE_SYS_BUS_DEVICE,
 591     .instance_size = sizeof(UNINState),
 592     .instance_init = unin_init,
 593     .class_init    = unin_class_init,
 594 };
 595
 596 static void unin_register_types(void)
 597 {
 598     type_register_static(&unin_main_pci_host_info);
 599     type_register_static(&u3_agp_pci_host_info);
 600     type_register_static(&unin_agp_pci_host_info);
 601     type_register_static(&unin_internal_pci_host_info);
 602
 603     type_register_static(&pci_unin_main_info);
 604     type_register_static(&pci_u3_agp_info);
 605     type_register_static(&pci_unin_agp_info);
 606     type_register_static(&pci_unin_internal_info);
 607
 608     type_register_static(&unin_info);
 609 }
 610
 611 type_init(unin_register_types)