include/hw/arm/xlnx-zynqmp.h

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #ifndef XLNX_ZYNQMP_H
  19
  20 #include "qemu-common.h"
  21 #include "hw/arm/arm.h"
  22 #include "hw/intc/arm_gic.h"
  23 #include "hw/net/cadence_gem.h"
  24 #include "hw/char/cadence_uart.h"
  25 #include "hw/ide/pci.h"
  26 #include "hw/ide/ahci.h"
  27 #include "hw/sd/sdhci.h"
  28 #include "hw/ssi/xilinx_spips.h"
  29 #include "hw/dma/xlnx_dpdma.h"
  30 #include "hw/dma/xlnx-zdma.h"
  31 #include "hw/display/xlnx_dp.h"
  32 #include "hw/intc/xlnx-zynqmp-ipi.h"
  33 #include "hw/timer/xlnx-zynqmp-rtc.h"
  34
  35 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
  36 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
  37                                        TYPE_XLNX_ZYNQMP)
  38
  39 #define XLNX_ZYNQMP_NUM_APU_CPUS 4
  40 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
  41 #define XLNX_ZYNQMP_NUM_GEMS 4
  42 #define XLNX_ZYNQMP_NUM_UARTS 2
  43 #define XLNX_ZYNQMP_NUM_SDHCI 2
  44 #define XLNX_ZYNQMP_NUM_SPIS 2
  45 #define XLNX_ZYNQMP_NUM_GDMA_CH 8
  46 #define XLNX_ZYNQMP_NUM_ADMA_CH 8
  47
  48 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2
  49 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
  50 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4
  51
  52 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
  53 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
  54 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
  55
  56 #define XLNX_ZYNQMP_GIC_REGIONS 2
  57
  58 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
  59  * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
  60  * aligned address in the 64k region. To implement each GIC region needs a
  61  * number of memory region aliases.
  62  */
  63
  64 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
  65 #define XLNX_ZYNQMP_GIC_ALIASES     (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
  66
  67 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE    0x80000000ull
  68
  69 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE   0x800000000ull
  70 #define XLNX_ZYNQMP_HIGH_RAM_START      0x800000000ull
  71
  72 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
  73                                   XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
  74
  75 typedef struct XlnxZynqMPState {
  76     /*< private >*/
  77     DeviceState parent_obj;
  78
  79     /*< public >*/
  80     ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
  81     ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
  82     GICState gic;
  83     MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
  84
  85     MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
  86
  87     MemoryRegion *ddr_ram;
  88     MemoryRegion ddr_ram_low, ddr_ram_high;
  89
  90     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
  91     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
  92     SysbusAHCIState sata;
  93     SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
  94     XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
  95     XlnxZynqMPQSPIPS qspi;
  96     XlnxDPState dp;
  97     XlnxDPDMAState dpdma;
  98     XlnxZynqMPIPI ipi;
  99     XlnxZynqMPRTC rtc;
 100     XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
 101     XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
 102
 103     char *boot_cpu;
 104     ARMCPU *boot_cpu_ptr;
 105
 106     /* Has the ARM Security extensions?  */
 107     bool secure;
 108     /* Has the ARM Virtualization extensions?  */
 109     bool virt;
 110     /* Has the RPU subsystem?  */
 111     bool has_rpu;
 112 }  XlnxZynqMPState;
 113
 114 #define XLNX_ZYNQMP_H
 115 #endif