monitor: Fix tracepoint crash on JSON syntax error
[qemu/armbru.git] / tests / ahci-test.c
blob1a7b761304b6546e4952b703f2afe690ab21f8ba
1 /*
2 * AHCI test cases
4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include <getopt.h>
28 #include "libqtest.h"
29 #include "libqos/libqos-pc.h"
30 #include "libqos/ahci.h"
31 #include "libqos/pci-pc.h"
33 #include "qemu-common.h"
34 #include "qapi/qmp/qdict.h"
35 #include "qemu/host-utils.h"
37 #include "hw/pci/pci_ids.h"
38 #include "hw/pci/pci_regs.h"
40 /* Test images sizes in MB */
41 #define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
42 #define TEST_IMAGE_SIZE_MB_SMALL 64
44 /*** Globals ***/
45 static char tmp_path[] = "/tmp/qtest.XXXXXX";
46 static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
47 static char mig_socket[] = "/tmp/qtest-migration.XXXXXX";
48 static bool ahci_pedantic;
49 static const char *imgfmt;
50 static unsigned test_image_size_mb;
52 /*** Function Declarations ***/
53 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
54 static void ahci_test_pci_spec(AHCIQState *ahci);
55 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
56 uint8_t offset);
57 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
58 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
59 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
61 /*** Utilities ***/
63 static uint64_t mb_to_sectors(uint64_t image_size_mb)
65 return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE;
68 static void string_bswap16(uint16_t *s, size_t bytes)
70 g_assert_cmphex((bytes & 1), ==, 0);
71 bytes /= 2;
73 while (bytes--) {
74 *s = bswap16(*s);
75 s++;
79 /**
80 * Verify that the transfer did not corrupt our state at all.
82 static void verify_state(AHCIQState *ahci, uint64_t hba_old)
84 int i, j;
85 uint32_t ahci_fingerprint;
86 uint64_t hba_base;
87 AHCICommandHeader cmd;
89 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID);
90 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint);
92 /* If we haven't initialized, this is as much as can be validated. */
93 if (!ahci->enabled) {
94 return;
97 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
98 g_assert_cmphex(hba_base, ==, hba_old);
100 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap);
101 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2);
103 for (i = 0; i < 32; i++) {
104 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==,
105 ahci->port[i].fb);
106 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==,
107 ahci->port[i].clb);
108 for (j = 0; j < 32; j++) {
109 ahci_get_command_header(ahci, i, j, &cmd);
110 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]);
111 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]);
116 static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri)
118 QOSState *tmp = to->parent;
119 QPCIDevice *dev = to->dev;
120 char *uri_local = NULL;
121 uint64_t hba_old;
123 if (uri == NULL) {
124 uri_local = g_strdup_printf("%s%s", "unix:", mig_socket);
125 uri = uri_local;
128 hba_old = (uint64_t)qpci_config_readl(from->dev, PCI_BASE_ADDRESS_5);
130 /* context will be 'to' after completion. */
131 migrate(from->parent, to->parent, uri);
133 /* We'd like for the AHCIState objects to still point
134 * to information specific to its specific parent
135 * instance, but otherwise just inherit the new data. */
136 memcpy(to, from, sizeof(AHCIQState));
137 to->parent = tmp;
138 to->dev = dev;
140 tmp = from->parent;
141 dev = from->dev;
142 memset(from, 0x00, sizeof(AHCIQState));
143 from->parent = tmp;
144 from->dev = dev;
146 verify_state(to, hba_old);
147 g_free(uri_local);
150 /*** Test Setup & Teardown ***/
153 * Start a Q35 machine and bookmark a handle to the AHCI device.
155 static AHCIQState *ahci_vboot(const char *cli, va_list ap)
157 AHCIQState *s;
159 s = g_new0(AHCIQState, 1);
160 s->parent = qtest_pc_vboot(cli, ap);
161 global_qtest = s->parent->qts;
162 alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT);
164 /* Verify that we have an AHCI device present. */
165 s->dev = get_ahci_device(s->parent->qts, &s->fingerprint);
167 return s;
171 * Start a Q35 machine and bookmark a handle to the AHCI device.
173 static AHCIQState *ahci_boot(const char *cli, ...)
175 AHCIQState *s;
176 va_list ap;
178 if (cli) {
179 va_start(ap, cli);
180 s = ahci_vboot(cli, ap);
181 va_end(ap);
182 } else {
183 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
184 ",format=%s"
185 " -M q35 "
186 "-device ide-hd,drive=drive0 "
187 "-global ide-hd.ver=%s";
188 s = ahci_boot(cli, tmp_path, "testdisk", imgfmt, "version");
191 return s;
195 * Clean up the PCI device, then terminate the QEMU instance.
197 static void ahci_shutdown(AHCIQState *ahci)
199 QOSState *qs = ahci->parent;
201 set_context(qs);
202 ahci_clean_mem(ahci);
203 free_ahci_device(ahci->dev);
204 g_free(ahci);
205 qtest_shutdown(qs);
209 * Boot and fully enable the HBA device.
210 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
212 static AHCIQState *ahci_boot_and_enable(const char *cli, ...)
214 AHCIQState *ahci;
215 va_list ap;
216 uint16_t buff[256];
217 uint8_t port;
218 uint8_t hello;
220 if (cli) {
221 va_start(ap, cli);
222 ahci = ahci_vboot(cli, ap);
223 va_end(ap);
224 } else {
225 ahci = ahci_boot(NULL);
228 ahci_pci_enable(ahci);
229 ahci_hba_enable(ahci);
230 /* Initialize test device */
231 port = ahci_port_select(ahci);
232 ahci_port_clear(ahci, port);
233 if (is_atapi(ahci, port)) {
234 hello = CMD_PACKET_ID;
235 } else {
236 hello = CMD_IDENTIFY;
238 ahci_io(ahci, port, hello, &buff, sizeof(buff), 0);
240 return ahci;
243 /*** Specification Adherence Tests ***/
246 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
248 static void ahci_test_pci_spec(AHCIQState *ahci)
250 uint8_t datab;
251 uint16_t data;
252 uint32_t datal;
254 /* Most of these bits should start cleared until we turn them on. */
255 data = qpci_config_readw(ahci->dev, PCI_COMMAND);
256 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
257 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
258 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL); /* Reserved */
259 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
260 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
261 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT); /* Reserved */
262 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
263 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
264 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
265 ASSERT_BIT_CLEAR(data, 0xF800); /* Reserved */
267 data = qpci_config_readw(ahci->dev, PCI_STATUS);
268 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04); /* Reserved */
269 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
270 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST); /* must be set */
271 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF); /* Reserved */
272 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
273 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
274 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
275 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
276 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
277 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
279 /* RID occupies the low byte, CCs occupy the high three. */
280 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
281 if (ahci_pedantic) {
282 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
283 * Though in practice this is likely seldom true. */
284 ASSERT_BIT_CLEAR(datal, 0xFF);
287 /* BCC *must* equal 0x01. */
288 g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
289 if (PCI_SCC(datal) == 0x01) {
290 /* IDE */
291 ASSERT_BIT_SET(0x80000000, datal);
292 ASSERT_BIT_CLEAR(0x60000000, datal);
293 } else if (PCI_SCC(datal) == 0x04) {
294 /* RAID */
295 g_assert_cmphex(PCI_PI(datal), ==, 0);
296 } else if (PCI_SCC(datal) == 0x06) {
297 /* AHCI */
298 g_assert_cmphex(PCI_PI(datal), ==, 0x01);
299 } else {
300 g_assert_not_reached();
303 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
304 g_assert_cmphex(datab, ==, 0);
306 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
307 g_assert_cmphex(datab, ==, 0);
309 /* Only the bottom 7 bits must be off. */
310 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
311 ASSERT_BIT_CLEAR(datab, 0x7F);
313 /* BIST is optional, but the low 7 bits must always start off regardless. */
314 datab = qpci_config_readb(ahci->dev, PCI_BIST);
315 ASSERT_BIT_CLEAR(datab, 0x7F);
317 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
318 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
319 g_assert_cmphex(datal, ==, 0);
321 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
322 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
323 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
324 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
325 ASSERT_BIT_CLEAR(datal, 0xFF);
327 /* Capability list MUST be present, */
328 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
329 /* But these bits are reserved. */
330 ASSERT_BIT_CLEAR(datal, ~0xFF);
331 g_assert_cmphex(datal, !=, 0);
333 /* Check specification adherence for capability extenstions. */
334 data = qpci_config_readw(ahci->dev, datal);
336 switch (ahci->fingerprint) {
337 case AHCI_INTEL_ICH9:
338 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
339 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
340 break;
341 default:
342 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
343 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
346 ahci_test_pci_caps(ahci, data, (uint8_t)datal);
348 /* Reserved. */
349 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
350 g_assert_cmphex(datal, ==, 0);
352 /* IPIN might vary, but ILINE must be off. */
353 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
354 g_assert_cmphex(datab, ==, 0);
358 * Test PCI capabilities for AHCI specification adherence.
360 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
361 uint8_t offset)
363 uint8_t cid = header & 0xFF;
364 uint8_t next = header >> 8;
366 g_test_message("CID: %02x; next: %02x", cid, next);
368 switch (cid) {
369 case PCI_CAP_ID_PM:
370 ahci_test_pmcap(ahci, offset);
371 break;
372 case PCI_CAP_ID_MSI:
373 ahci_test_msicap(ahci, offset);
374 break;
375 case PCI_CAP_ID_SATA:
376 ahci_test_satacap(ahci, offset);
377 break;
379 default:
380 g_test_message("Unknown CAP 0x%02x", cid);
383 if (next) {
384 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
389 * Test SATA PCI capabilitity for AHCI specification adherence.
391 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
393 uint16_t dataw;
394 uint32_t datal;
396 g_test_message("Verifying SATACAP");
398 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
399 dataw = qpci_config_readw(ahci->dev, offset + 2);
400 g_assert_cmphex(dataw, ==, 0x10);
402 /* Grab the SATACR1 register. */
403 datal = qpci_config_readw(ahci->dev, offset + 4);
405 switch (datal & 0x0F) {
406 case 0x04: /* BAR0 */
407 case 0x05: /* BAR1 */
408 case 0x06:
409 case 0x07:
410 case 0x08:
411 case 0x09: /* BAR5 */
412 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
413 break;
414 default:
415 /* Invalid BARLOC for the Index Data Pair. */
416 g_assert_not_reached();
419 /* Reserved. */
420 g_assert_cmphex((datal >> 24), ==, 0x00);
424 * Test MSI PCI capability for AHCI specification adherence.
426 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
428 uint16_t dataw;
429 uint32_t datal;
431 g_test_message("Verifying MSICAP");
433 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
434 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
435 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
436 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
438 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
439 g_assert_cmphex(datal, ==, 0);
441 if (dataw & PCI_MSI_FLAGS_64BIT) {
442 g_test_message("MSICAP is 64bit");
443 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
444 g_assert_cmphex(datal, ==, 0);
445 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
446 g_assert_cmphex(dataw, ==, 0);
447 } else {
448 g_test_message("MSICAP is 32bit");
449 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
450 g_assert_cmphex(dataw, ==, 0);
455 * Test Power Management PCI capability for AHCI specification adherence.
457 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
459 uint16_t dataw;
461 g_test_message("Verifying PMCAP");
463 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
464 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
465 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
466 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
467 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
469 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
470 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
471 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
472 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
473 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
476 static void ahci_test_hba_spec(AHCIQState *ahci)
478 unsigned i;
479 uint32_t reg;
480 uint32_t ports;
481 uint8_t nports_impl;
482 uint8_t maxports;
484 g_assert(ahci != NULL);
487 * Note that the AHCI spec does expect the BIOS to set up a few things:
488 * CAP.SSS - Support for staggered spin-up (t/f)
489 * CAP.SMPS - Support for mechanical presence switches (t/f)
490 * PI - Ports Implemented (1-32)
491 * PxCMD.HPCP - Hot Plug Capable Port
492 * PxCMD.MPSP - Mechanical Presence Switch Present
493 * PxCMD.CPD - Cold Presence Detection support
495 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
496 * Foreach Port Implemented:
497 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
498 * -PxCLB/U and PxFB/U are set to valid regions in memory
499 * -PxSUD is set to 1.
500 * -PxSSTS.DET is polled for presence; if detected, we continue:
501 * -PxSERR is cleared with 1's.
502 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
503 * the device is ready.
506 /* 1 CAP - Capabilities Register */
507 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
508 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
510 /* 2 GHC - Global Host Control */
511 reg = ahci_rreg(ahci, AHCI_GHC);
512 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
513 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
514 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
515 if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
516 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
517 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
518 } else {
519 g_test_message("Supports AHCI/Legacy mix.");
520 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
523 /* 3 IS - Interrupt Status */
524 reg = ahci_rreg(ahci, AHCI_IS);
525 g_assert_cmphex(reg, ==, 0);
527 /* 4 PI - Ports Implemented */
528 ports = ahci_rreg(ahci, AHCI_PI);
529 /* Ports Implemented must be non-zero. */
530 g_assert_cmphex(ports, !=, 0);
531 /* Ports Implemented must be <= Number of Ports. */
532 nports_impl = ctpopl(ports);
533 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
535 /* Ports must be within the proper range. Given a mapping of SIZE,
536 * 256 bytes are used for global HBA control, and the rest is used
537 * for ports data, at 0x80 bytes each. */
538 g_assert_cmphex(ahci->barsize, >, 0);
539 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
540 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
541 g_assert_cmphex((reg >> maxports), ==, 0);
543 /* 5 AHCI Version */
544 reg = ahci_rreg(ahci, AHCI_VS);
545 switch (reg) {
546 case AHCI_VERSION_0_95:
547 case AHCI_VERSION_1_0:
548 case AHCI_VERSION_1_1:
549 case AHCI_VERSION_1_2:
550 case AHCI_VERSION_1_3:
551 break;
552 default:
553 g_assert_not_reached();
556 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
557 reg = ahci_rreg(ahci, AHCI_CCCCTL);
558 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
559 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
560 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
561 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
562 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
563 } else {
564 g_assert_cmphex(reg, ==, 0);
567 /* 7 CCC_PORTS */
568 reg = ahci_rreg(ahci, AHCI_CCCPORTS);
569 /* Must be zeroes initially regardless of CAP.CCCS */
570 g_assert_cmphex(reg, ==, 0);
572 /* 8 EM_LOC */
573 reg = ahci_rreg(ahci, AHCI_EMLOC);
574 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
575 g_assert_cmphex(reg, ==, 0);
578 /* 9 EM_CTL */
579 reg = ahci_rreg(ahci, AHCI_EMCTL);
580 if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
581 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
582 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
583 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
584 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
585 } else {
586 g_assert_cmphex(reg, ==, 0);
589 /* 10 CAP2 -- Capabilities Extended */
590 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
591 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
593 /* 11 BOHC -- Bios/OS Handoff Control */
594 reg = ahci_rreg(ahci, AHCI_BOHC);
595 g_assert_cmphex(reg, ==, 0);
597 /* 12 -- 23: Reserved */
598 g_test_message("Verifying HBA reserved area is empty.");
599 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
600 reg = ahci_rreg(ahci, i);
601 g_assert_cmphex(reg, ==, 0);
604 /* 24 -- 39: NVMHCI */
605 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
606 g_test_message("Verifying HBA/NVMHCI area is empty.");
607 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
608 reg = ahci_rreg(ahci, i);
609 g_assert_cmphex(reg, ==, 0);
613 /* 40 -- 63: Vendor */
614 g_test_message("Verifying HBA/Vendor area is empty.");
615 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
616 reg = ahci_rreg(ahci, i);
617 g_assert_cmphex(reg, ==, 0);
620 /* 64 -- XX: Port Space */
621 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
622 if (BITSET(ports, 0x1)) {
623 g_test_message("Testing port %u for spec", i);
624 ahci_test_port_spec(ahci, i);
625 } else {
626 uint16_t j;
627 uint16_t low = AHCI_PORTS + (32 * i);
628 uint16_t high = AHCI_PORTS + (32 * (i + 1));
629 g_test_message("Asserting unimplemented port %u "
630 "(reg [%u-%u]) is empty.",
631 i, low, high - 1);
632 for (j = low; j < high; ++j) {
633 reg = ahci_rreg(ahci, j);
634 g_assert_cmphex(reg, ==, 0);
641 * Test the memory space for one port for specification adherence.
643 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
645 uint32_t reg;
646 unsigned i;
648 /* (0) CLB */
649 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
650 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
652 /* (1) CLBU */
653 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
654 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
655 g_assert_cmphex(reg, ==, 0);
658 /* (2) FB */
659 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
660 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
662 /* (3) FBU */
663 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
664 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
665 g_assert_cmphex(reg, ==, 0);
668 /* (4) IS */
669 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
670 g_assert_cmphex(reg, ==, 0);
672 /* (5) IE */
673 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
674 g_assert_cmphex(reg, ==, 0);
676 /* (6) CMD */
677 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
678 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
679 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
680 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
681 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
682 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
683 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
684 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
685 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
686 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
687 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE); /* RW only if CAP.SALP */
688 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP); /* RW only if CAP.SALP */
689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
690 /* If CPDetect support does not exist, CPState must be off. */
691 if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
692 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
694 /* If MPSPresence is not set, MPSState must be off. */
695 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
696 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
698 /* If we do not support MPS, MPSS and MPSP must be off. */
699 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
700 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
701 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
703 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
704 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
705 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
707 /* HPCP and ESP cannot both be active. */
708 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
709 /* If CAP.FBSS is not set, FBSCP must not be set. */
710 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
711 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
714 /* (7) RESERVED */
715 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
716 g_assert_cmphex(reg, ==, 0);
718 /* (8) TFD */
719 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
720 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
721 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
722 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
723 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
724 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
725 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
726 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
727 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
728 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
730 /* (9) SIG */
731 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
732 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
733 * D2H register FIS and update the signature asynchronously,
734 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
736 /* (10) SSTS / SCR0: SStatus */
737 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
738 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
739 /* Even though the register should be 0 at boot, it is asynchronous and
740 * prone to change, so we cannot test any well known value. */
742 /* (11) SCTL / SCR2: SControl */
743 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
744 g_assert_cmphex(reg, ==, 0);
746 /* (12) SERR / SCR1: SError */
747 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
748 g_assert_cmphex(reg, ==, 0);
750 /* (13) SACT / SCR3: SActive */
751 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
752 g_assert_cmphex(reg, ==, 0);
754 /* (14) CI */
755 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
756 g_assert_cmphex(reg, ==, 0);
758 /* (15) SNTF */
759 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
760 g_assert_cmphex(reg, ==, 0);
762 /* (16) FBS */
763 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
764 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
765 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
766 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
767 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
768 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
769 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
770 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
771 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
772 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
775 /* [17 -- 27] RESERVED */
776 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
777 reg = ahci_px_rreg(ahci, port, i);
778 g_assert_cmphex(reg, ==, 0);
781 /* [28 -- 31] Vendor-Specific */
782 for (i = AHCI_PX_VS; i < 32; ++i) {
783 reg = ahci_px_rreg(ahci, port, i);
784 if (reg) {
785 g_test_message("INFO: Vendor register %u non-empty", i);
791 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
792 * device we see, then read and check the response.
794 static void ahci_test_identify(AHCIQState *ahci)
796 uint16_t buff[256];
797 unsigned px;
798 int rc;
799 uint16_t sect_size;
800 const size_t buffsize = 512;
802 g_assert(ahci != NULL);
805 * This serves as a bit of a tutorial on AHCI device programming:
807 * (1) Create a data buffer for the IDENTIFY response to be sent to
808 * (2) Create a Command Table buffer, where we will store the
809 * command and PRDT (Physical Region Descriptor Table)
810 * (3) Construct an FIS host-to-device command structure, and write it to
811 * the top of the Command Table buffer.
812 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
813 * a location in memory where data may be stored/retrieved.
814 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
815 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
816 * header that points to a Command Table buffer. Pick an unused slot
817 * and update it to point to the Command Table we have built.
818 * (7) Now: Command #n points to our Command Table, and our Command Table
819 * contains the FIS (that describes our command) and the PRDTL, which
820 * describes our buffer.
821 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
822 * #n is ready for processing.
825 /* Pick the first implemented and running port */
826 px = ahci_port_select(ahci);
827 g_test_message("Selected port %u for test", px);
829 /* Clear out the FIS Receive area and any pending interrupts. */
830 ahci_port_clear(ahci, px);
832 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
833 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0);
835 /* Check serial number/version in the buffer */
836 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
837 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
838 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
839 * as a consequence, only needs to unchunk the data on LE machines. */
840 string_bswap16(&buff[10], 20);
841 rc = memcmp(&buff[10], "testdisk ", 20);
842 g_assert_cmphex(rc, ==, 0);
844 string_bswap16(&buff[23], 8);
845 rc = memcmp(&buff[23], "version ", 8);
846 g_assert_cmphex(rc, ==, 0);
848 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
849 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE);
852 static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
853 uint64_t sector, uint8_t read_cmd,
854 uint8_t write_cmd)
856 uint64_t ptr;
857 uint8_t port;
858 unsigned char *tx = g_malloc(bufsize);
859 unsigned char *rx = g_malloc0(bufsize);
861 g_assert(ahci != NULL);
863 /* Pick the first running port and clear it. */
864 port = ahci_port_select(ahci);
865 ahci_port_clear(ahci, port);
867 /*** Create pattern and transfer to guest ***/
868 /* Data buffer in the guest */
869 ptr = ahci_alloc(ahci, bufsize);
870 g_assert(ptr);
872 /* Write some indicative pattern to our buffer. */
873 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
874 bufwrite(ptr, tx, bufsize);
876 /* Write this buffer to disk, then read it back to the DMA buffer. */
877 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector);
878 qmemset(ptr, 0x00, bufsize);
879 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector);
881 /*** Read back the Data ***/
882 bufread(ptr, rx, bufsize);
883 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
885 ahci_free(ahci, ptr);
886 g_free(tx);
887 g_free(rx);
890 static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd)
892 uint8_t port;
894 /* Sanitize */
895 port = ahci_port_select(ahci);
896 ahci_port_clear(ahci, port);
898 ahci_io(ahci, port, ide_cmd, NULL, 0, 0);
900 return port;
903 static void ahci_test_flush(AHCIQState *ahci)
905 ahci_test_nondata(ahci, CMD_FLUSH_CACHE);
908 static void ahci_test_max(AHCIQState *ahci)
910 RegD2HFIS *d2h = g_malloc0(0x20);
911 uint64_t nsect;
912 uint8_t port;
913 uint8_t cmd;
914 uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1;
916 if (config_sect > 0xFFFFFF) {
917 cmd = CMD_READ_MAX_EXT;
918 } else {
919 cmd = CMD_READ_MAX;
922 port = ahci_test_nondata(ahci, cmd);
923 memread(ahci->port[port].fb + 0x40, d2h, 0x20);
924 nsect = (uint64_t)d2h->lba_hi[2] << 40 |
925 (uint64_t)d2h->lba_hi[1] << 32 |
926 (uint64_t)d2h->lba_hi[0] << 24 |
927 (uint64_t)d2h->lba_lo[2] << 16 |
928 (uint64_t)d2h->lba_lo[1] << 8 |
929 (uint64_t)d2h->lba_lo[0];
931 g_assert_cmphex(nsect, ==, config_sect);
932 g_free(d2h);
936 /******************************************************************************/
937 /* Test Interfaces */
938 /******************************************************************************/
941 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
943 static void test_sanity(void)
945 AHCIQState *ahci;
946 ahci = ahci_boot(NULL);
947 ahci_shutdown(ahci);
951 * Ensure that the PCI configuration space for the AHCI device is in-line with
952 * the AHCI 1.3 specification for initial values.
954 static void test_pci_spec(void)
956 AHCIQState *ahci;
957 ahci = ahci_boot(NULL);
958 ahci_test_pci_spec(ahci);
959 ahci_shutdown(ahci);
963 * Engage the PCI AHCI device and sanity check the response.
964 * Perform additional PCI config space bringup for the HBA.
966 static void test_pci_enable(void)
968 AHCIQState *ahci;
969 ahci = ahci_boot(NULL);
970 ahci_pci_enable(ahci);
971 ahci_shutdown(ahci);
975 * Investigate the memory mapped regions of the HBA,
976 * and test them for AHCI specification adherence.
978 static void test_hba_spec(void)
980 AHCIQState *ahci;
982 ahci = ahci_boot(NULL);
983 ahci_pci_enable(ahci);
984 ahci_test_hba_spec(ahci);
985 ahci_shutdown(ahci);
989 * Engage the HBA functionality of the AHCI PCI device,
990 * and bring it into a functional idle state.
992 static void test_hba_enable(void)
994 AHCIQState *ahci;
996 ahci = ahci_boot(NULL);
997 ahci_pci_enable(ahci);
998 ahci_hba_enable(ahci);
999 ahci_shutdown(ahci);
1003 * Bring up the device and issue an IDENTIFY command.
1004 * Inspect the state of the HBA device and the data returned.
1006 static void test_identify(void)
1008 AHCIQState *ahci;
1010 ahci = ahci_boot_and_enable(NULL);
1011 ahci_test_identify(ahci);
1012 ahci_shutdown(ahci);
1016 * Fragmented DMA test: Perform a standard 4K DMA read/write
1017 * test, but make sure the physical regions are fragmented to
1018 * be very small, each just 32 bytes, to see how AHCI performs
1019 * with chunks defined to be much less than a sector.
1021 static void test_dma_fragmented(void)
1023 AHCIQState *ahci;
1024 AHCICommand *cmd;
1025 uint8_t px;
1026 size_t bufsize = 4096;
1027 unsigned char *tx = g_malloc(bufsize);
1028 unsigned char *rx = g_malloc0(bufsize);
1029 uint64_t ptr;
1031 ahci = ahci_boot_and_enable(NULL);
1032 px = ahci_port_select(ahci);
1033 ahci_port_clear(ahci, px);
1035 /* create pattern */
1036 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1038 /* Create a DMA buffer in guest memory, and write our pattern to it. */
1039 ptr = guest_alloc(ahci->parent->alloc, bufsize);
1040 g_assert(ptr);
1041 bufwrite(ptr, tx, bufsize);
1043 cmd = ahci_command_create(CMD_WRITE_DMA);
1044 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1045 ahci_command_commit(ahci, cmd, px);
1046 ahci_command_issue(ahci, cmd);
1047 ahci_command_verify(ahci, cmd);
1048 ahci_command_free(cmd);
1050 cmd = ahci_command_create(CMD_READ_DMA);
1051 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1052 ahci_command_commit(ahci, cmd, px);
1053 ahci_command_issue(ahci, cmd);
1054 ahci_command_verify(ahci, cmd);
1055 ahci_command_free(cmd);
1057 /* Read back the guest's receive buffer into local memory */
1058 bufread(ptr, rx, bufsize);
1059 guest_free(ahci->parent->alloc, ptr);
1061 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1063 ahci_shutdown(ahci);
1065 g_free(rx);
1066 g_free(tx);
1070 * Write sector 1 with random data to make AHCI storage dirty
1071 * Needed for flush tests so that flushes actually go though the block layer
1073 static void make_dirty(AHCIQState* ahci, uint8_t port)
1075 uint64_t ptr;
1076 unsigned bufsize = 512;
1078 ptr = ahci_alloc(ahci, bufsize);
1079 g_assert(ptr);
1081 ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize, 1);
1082 ahci_free(ahci, ptr);
1085 static void test_flush(void)
1087 AHCIQState *ahci;
1088 uint8_t port;
1090 ahci = ahci_boot_and_enable(NULL);
1092 port = ahci_port_select(ahci);
1093 ahci_port_clear(ahci, port);
1095 make_dirty(ahci, port);
1097 ahci_test_flush(ahci);
1098 ahci_shutdown(ahci);
1101 static void test_flush_retry(void)
1103 AHCIQState *ahci;
1104 AHCICommand *cmd;
1105 uint8_t port;
1107 prepare_blkdebug_script(debug_path, "flush_to_disk");
1108 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1109 "format=%s,cache=writeback,"
1110 "rerror=stop,werror=stop "
1111 "-M q35 "
1112 "-device ide-hd,drive=drive0 ",
1113 debug_path,
1114 tmp_path, imgfmt);
1116 port = ahci_port_select(ahci);
1117 ahci_port_clear(ahci, port);
1119 /* Issue write so that flush actually goes to disk */
1120 make_dirty(ahci, port);
1122 /* Issue Flush Command and wait for error */
1123 cmd = ahci_guest_io_halt(ahci, port, CMD_FLUSH_CACHE, 0, 0, 0);
1124 ahci_guest_io_resume(ahci, cmd);
1126 ahci_shutdown(ahci);
1130 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1132 static void test_migrate_sanity(void)
1134 AHCIQState *src, *dst;
1135 char *uri = g_strdup_printf("unix:%s", mig_socket);
1137 src = ahci_boot("-m 384 -M q35 "
1138 "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt);
1139 dst = ahci_boot("-m 384 -M q35 "
1140 "-drive if=ide,file=%s,format=%s "
1141 "-incoming %s", tmp_path, imgfmt, uri);
1143 ahci_migrate(src, dst, uri);
1145 ahci_shutdown(src);
1146 ahci_shutdown(dst);
1147 g_free(uri);
1151 * Simple migration test: Write a pattern, migrate, then read.
1153 static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write)
1155 AHCIQState *src, *dst;
1156 uint8_t px;
1157 size_t bufsize = 4096;
1158 unsigned char *tx = g_malloc(bufsize);
1159 unsigned char *rx = g_malloc0(bufsize);
1160 char *uri = g_strdup_printf("unix:%s", mig_socket);
1162 src = ahci_boot_and_enable("-m 384 -M q35 "
1163 "-drive if=ide,format=%s,file=%s ",
1164 imgfmt, tmp_path);
1165 dst = ahci_boot("-m 384 -M q35 "
1166 "-drive if=ide,format=%s,file=%s "
1167 "-incoming %s", imgfmt, tmp_path, uri);
1169 set_context(src->parent);
1171 /* initialize */
1172 px = ahci_port_select(src);
1173 ahci_port_clear(src, px);
1175 /* create pattern */
1176 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1178 /* Write, migrate, then read. */
1179 ahci_io(src, px, cmd_write, tx, bufsize, 0);
1180 ahci_migrate(src, dst, uri);
1181 ahci_io(dst, px, cmd_read, rx, bufsize, 0);
1183 /* Verify pattern */
1184 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1186 ahci_shutdown(src);
1187 ahci_shutdown(dst);
1188 g_free(rx);
1189 g_free(tx);
1190 g_free(uri);
1193 static void test_migrate_dma(void)
1195 ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA);
1198 static void test_migrate_ncq(void)
1200 ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1204 * Halted IO Error Test
1206 * Simulate an error on first write, Try to write a pattern,
1207 * Confirm the VM has stopped, resume the VM, verify command
1208 * has completed, then read back the data and verify.
1210 static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write)
1212 AHCIQState *ahci;
1213 uint8_t port;
1214 size_t bufsize = 4096;
1215 unsigned char *tx = g_malloc(bufsize);
1216 unsigned char *rx = g_malloc0(bufsize);
1217 uint64_t ptr;
1218 AHCICommand *cmd;
1220 prepare_blkdebug_script(debug_path, "write_aio");
1222 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1223 "format=%s,cache=writeback,"
1224 "rerror=stop,werror=stop "
1225 "-M q35 "
1226 "-device ide-hd,drive=drive0 ",
1227 debug_path,
1228 tmp_path, imgfmt);
1230 /* Initialize and prepare */
1231 port = ahci_port_select(ahci);
1232 ahci_port_clear(ahci, port);
1234 /* create DMA source buffer and write pattern */
1235 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1236 ptr = ahci_alloc(ahci, bufsize);
1237 g_assert(ptr);
1238 memwrite(ptr, tx, bufsize);
1240 /* Attempt to write (and fail) */
1241 cmd = ahci_guest_io_halt(ahci, port, cmd_write,
1242 ptr, bufsize, 0);
1244 /* Attempt to resume the command */
1245 ahci_guest_io_resume(ahci, cmd);
1246 ahci_free(ahci, ptr);
1248 /* Read back and verify */
1249 ahci_io(ahci, port, cmd_read, rx, bufsize, 0);
1250 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1252 /* Cleanup and go home */
1253 ahci_shutdown(ahci);
1254 g_free(rx);
1255 g_free(tx);
1258 static void test_halted_dma(void)
1260 ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA);
1263 static void test_halted_ncq(void)
1265 ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1269 * IO Error Migration Test
1271 * Simulate an error on first write, Try to write a pattern,
1272 * Confirm the VM has stopped, migrate, resume the VM,
1273 * verify command has completed, then read back the data and verify.
1275 static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write)
1277 AHCIQState *src, *dst;
1278 uint8_t port;
1279 size_t bufsize = 4096;
1280 unsigned char *tx = g_malloc(bufsize);
1281 unsigned char *rx = g_malloc0(bufsize);
1282 uint64_t ptr;
1283 AHCICommand *cmd;
1284 char *uri = g_strdup_printf("unix:%s", mig_socket);
1286 prepare_blkdebug_script(debug_path, "write_aio");
1288 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1289 "format=%s,cache=writeback,"
1290 "rerror=stop,werror=stop "
1291 "-M q35 "
1292 "-device ide-hd,drive=drive0 ",
1293 debug_path,
1294 tmp_path, imgfmt);
1296 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1297 "format=%s,cache=writeback,"
1298 "rerror=stop,werror=stop "
1299 "-M q35 "
1300 "-device ide-hd,drive=drive0 "
1301 "-incoming %s",
1302 tmp_path, imgfmt, uri);
1304 set_context(src->parent);
1306 /* Initialize and prepare */
1307 port = ahci_port_select(src);
1308 ahci_port_clear(src, port);
1309 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1311 /* create DMA source buffer and write pattern */
1312 ptr = ahci_alloc(src, bufsize);
1313 g_assert(ptr);
1314 memwrite(ptr, tx, bufsize);
1316 /* Write, trigger the VM to stop, migrate, then resume. */
1317 cmd = ahci_guest_io_halt(src, port, cmd_write,
1318 ptr, bufsize, 0);
1319 ahci_migrate(src, dst, uri);
1320 ahci_guest_io_resume(dst, cmd);
1321 ahci_free(dst, ptr);
1323 /* Read back */
1324 ahci_io(dst, port, cmd_read, rx, bufsize, 0);
1326 /* Verify TX and RX are identical */
1327 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1329 /* Cleanup and go home. */
1330 ahci_shutdown(src);
1331 ahci_shutdown(dst);
1332 g_free(rx);
1333 g_free(tx);
1334 g_free(uri);
1337 static void test_migrate_halted_dma(void)
1339 ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA);
1342 static void test_migrate_halted_ncq(void)
1344 ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1348 * Migration test: Try to flush, migrate, then resume.
1350 static void test_flush_migrate(void)
1352 AHCIQState *src, *dst;
1353 AHCICommand *cmd;
1354 uint8_t px;
1355 const char *s;
1356 char *uri = g_strdup_printf("unix:%s", mig_socket);
1358 prepare_blkdebug_script(debug_path, "flush_to_disk");
1360 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1361 "cache=writeback,rerror=stop,werror=stop,"
1362 "format=%s "
1363 "-M q35 "
1364 "-device ide-hd,drive=drive0 ",
1365 debug_path, tmp_path, imgfmt);
1366 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1367 "cache=writeback,rerror=stop,werror=stop,"
1368 "format=%s "
1369 "-M q35 "
1370 "-device ide-hd,drive=drive0 "
1371 "-incoming %s", tmp_path, imgfmt, uri);
1373 set_context(src->parent);
1375 px = ahci_port_select(src);
1376 ahci_port_clear(src, px);
1378 /* Dirty device so that flush reaches disk */
1379 make_dirty(src, px);
1381 /* Issue Flush Command */
1382 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1383 ahci_command_commit(src, cmd, px);
1384 ahci_command_issue_async(src, cmd);
1385 qmp_eventwait("STOP");
1387 /* Migrate over */
1388 ahci_migrate(src, dst, uri);
1390 /* Complete the command */
1391 s = "{'execute':'cont' }";
1392 qmp_async(s);
1393 qmp_eventwait("RESUME");
1394 ahci_command_wait(dst, cmd);
1395 ahci_command_verify(dst, cmd);
1397 ahci_command_free(cmd);
1398 ahci_shutdown(src);
1399 ahci_shutdown(dst);
1400 g_free(uri);
1403 static void test_max(void)
1405 AHCIQState *ahci;
1407 ahci = ahci_boot_and_enable(NULL);
1408 ahci_test_max(ahci);
1409 ahci_shutdown(ahci);
1412 static void test_reset(void)
1414 AHCIQState *ahci;
1415 int i;
1417 ahci = ahci_boot(NULL);
1418 ahci_test_pci_spec(ahci);
1419 ahci_pci_enable(ahci);
1421 for (i = 0; i < 2; i++) {
1422 ahci_test_hba_spec(ahci);
1423 ahci_hba_enable(ahci);
1424 ahci_test_identify(ahci);
1425 ahci_test_io_rw_simple(ahci, 4096, 0,
1426 CMD_READ_DMA_EXT,
1427 CMD_WRITE_DMA_EXT);
1428 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
1429 ahci_clean_mem(ahci);
1432 ahci_shutdown(ahci);
1435 static void test_ncq_simple(void)
1437 AHCIQState *ahci;
1439 ahci = ahci_boot_and_enable(NULL);
1440 ahci_test_io_rw_simple(ahci, 4096, 0,
1441 READ_FPDMA_QUEUED,
1442 WRITE_FPDMA_QUEUED);
1443 ahci_shutdown(ahci);
1446 static int prepare_iso(size_t size, unsigned char **buf, char **name)
1448 char cdrom_path[] = "/tmp/qtest.iso.XXXXXX";
1449 unsigned char *patt;
1450 ssize_t ret;
1451 int fd = mkstemp(cdrom_path);
1453 g_assert(buf);
1454 g_assert(name);
1455 patt = g_malloc(size);
1457 /* Generate a pattern and build a CDROM image to read from */
1458 generate_pattern(patt, size, ATAPI_SECTOR_SIZE);
1459 ret = write(fd, patt, size);
1460 g_assert(ret == size);
1462 *name = g_strdup(cdrom_path);
1463 *buf = patt;
1464 return fd;
1467 static void remove_iso(int fd, char *name)
1469 unlink(name);
1470 g_free(name);
1471 close(fd);
1474 static int ahci_cb_cmp_buff(AHCIQState *ahci, AHCICommand *cmd,
1475 const AHCIOpts *opts)
1477 unsigned char *tx = opts->opaque;
1478 unsigned char *rx;
1480 if (!opts->size) {
1481 return 0;
1484 rx = g_malloc0(opts->size);
1485 bufread(opts->buffer, rx, opts->size);
1486 g_assert_cmphex(memcmp(tx, rx, opts->size), ==, 0);
1487 g_free(rx);
1489 return 0;
1492 static void ahci_test_cdrom(int nsectors, bool dma, uint8_t cmd,
1493 bool override_bcl, uint16_t bcl)
1495 AHCIQState *ahci;
1496 unsigned char *tx;
1497 char *iso;
1498 int fd;
1499 AHCIOpts opts = {
1500 .size = (ATAPI_SECTOR_SIZE * nsectors),
1501 .atapi = true,
1502 .atapi_dma = dma,
1503 .post_cb = ahci_cb_cmp_buff,
1504 .set_bcl = override_bcl,
1505 .bcl = bcl,
1507 uint64_t iso_size = ATAPI_SECTOR_SIZE * (nsectors + 1);
1509 /* Prepare ISO and fill 'tx' buffer */
1510 fd = prepare_iso(iso_size, &tx, &iso);
1511 opts.opaque = tx;
1513 /* Standard startup wonkery, but use ide-cd and our special iso file */
1514 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1515 "-M q35 "
1516 "-device ide-cd,drive=drive0 ", iso);
1518 /* Build & Send AHCI command */
1519 ahci_exec(ahci, ahci_port_select(ahci), cmd, &opts);
1521 /* Cleanup */
1522 g_free(tx);
1523 ahci_shutdown(ahci);
1524 remove_iso(fd, iso);
1527 static void ahci_test_cdrom_read10(int nsectors, bool dma)
1529 ahci_test_cdrom(nsectors, dma, CMD_ATAPI_READ_10, false, 0);
1532 static void test_cdrom_dma(void)
1534 ahci_test_cdrom_read10(1, true);
1537 static void test_cdrom_dma_multi(void)
1539 ahci_test_cdrom_read10(3, true);
1542 static void test_cdrom_pio(void)
1544 ahci_test_cdrom_read10(1, false);
1547 static void test_cdrom_pio_multi(void)
1549 ahci_test_cdrom_read10(3, false);
1552 /* Regression test: Test that a READ_CD command with a BCL of 0 but a size of 0
1553 * completes as a NOP instead of erroring out. */
1554 static void test_atapi_bcl(void)
1556 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD, true, 0);
1560 static void atapi_wait_tray(bool open)
1562 QDict *rsp = qmp_eventwait_ref("DEVICE_TRAY_MOVED");
1563 QDict *data = qdict_get_qdict(rsp, "data");
1564 if (open) {
1565 g_assert(qdict_get_bool(data, "tray-open"));
1566 } else {
1567 g_assert(!qdict_get_bool(data, "tray-open"));
1569 qobject_unref(rsp);
1572 static void test_atapi_tray(void)
1574 AHCIQState *ahci;
1575 unsigned char *tx;
1576 char *iso;
1577 int fd;
1578 uint8_t port, sense, asc;
1579 uint64_t iso_size = ATAPI_SECTOR_SIZE;
1580 QDict *rsp;
1582 fd = prepare_iso(iso_size, &tx, &iso);
1583 ahci = ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s "
1584 "-M q35 "
1585 "-device ide-cd,id=cd0,drive=drive0 ", iso);
1586 port = ahci_port_select(ahci);
1588 ahci_atapi_eject(ahci, port);
1589 atapi_wait_tray(true);
1591 ahci_atapi_load(ahci, port);
1592 atapi_wait_tray(false);
1594 /* Remove media */
1595 qmp_async("{'execute': 'blockdev-open-tray', "
1596 "'arguments': {'id': 'cd0'}}");
1597 atapi_wait_tray(true);
1598 rsp = qmp_receive();
1599 qobject_unref(rsp);
1601 qmp_discard_response("{'execute': 'blockdev-remove-medium', "
1602 "'arguments': {'id': 'cd0'}}");
1604 /* Test the tray without a medium */
1605 ahci_atapi_load(ahci, port);
1606 atapi_wait_tray(false);
1608 ahci_atapi_eject(ahci, port);
1609 atapi_wait_tray(true);
1611 /* Re-insert media */
1612 qmp_discard_response("{'execute': 'blockdev-add', "
1613 "'arguments': {'node-name': 'node0', "
1614 "'driver': 'raw', "
1615 "'file': { 'driver': 'file', "
1616 "'filename': %s }}}", iso);
1617 qmp_discard_response("{'execute': 'blockdev-insert-medium',"
1618 "'arguments': { 'id': 'cd0', "
1619 "'node-name': 'node0' }}");
1621 /* Again, the event shows up first */
1622 qmp_async("{'execute': 'blockdev-close-tray', "
1623 "'arguments': {'id': 'cd0'}}");
1624 atapi_wait_tray(false);
1625 rsp = qmp_receive();
1626 qobject_unref(rsp);
1628 /* Now, to convince ATAPI we understand the media has changed... */
1629 ahci_atapi_test_ready(ahci, port, false, SENSE_NOT_READY);
1630 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1631 g_assert_cmpuint(sense, ==, SENSE_NOT_READY);
1632 g_assert_cmpuint(asc, ==, ASC_MEDIUM_NOT_PRESENT);
1634 ahci_atapi_test_ready(ahci, port, false, SENSE_UNIT_ATTENTION);
1635 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1636 g_assert_cmpuint(sense, ==, SENSE_UNIT_ATTENTION);
1637 g_assert_cmpuint(asc, ==, ASC_MEDIUM_MAY_HAVE_CHANGED);
1639 ahci_atapi_test_ready(ahci, port, true, SENSE_NO_SENSE);
1640 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1641 g_assert_cmpuint(sense, ==, SENSE_NO_SENSE);
1643 /* Final tray test. */
1644 ahci_atapi_eject(ahci, port);
1645 atapi_wait_tray(true);
1647 ahci_atapi_load(ahci, port);
1648 atapi_wait_tray(false);
1650 /* Cleanup */
1651 g_free(tx);
1652 ahci_shutdown(ahci);
1653 remove_iso(fd, iso);
1656 /******************************************************************************/
1657 /* AHCI I/O Test Matrix Definitions */
1659 enum BuffLen {
1660 LEN_BEGIN = 0,
1661 LEN_SIMPLE = LEN_BEGIN,
1662 LEN_DOUBLE,
1663 LEN_LONG,
1664 LEN_SHORT,
1665 NUM_LENGTHS
1668 static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
1669 "long", "short" };
1671 enum AddrMode {
1672 ADDR_MODE_BEGIN = 0,
1673 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
1674 ADDR_MODE_LBA48,
1675 NUM_ADDR_MODES
1678 static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
1680 enum IOMode {
1681 MODE_BEGIN = 0,
1682 MODE_PIO = MODE_BEGIN,
1683 MODE_DMA,
1684 NUM_MODES
1687 static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
1689 enum IOOps {
1690 IO_BEGIN = 0,
1691 IO_READ = IO_BEGIN,
1692 IO_WRITE,
1693 NUM_IO_OPS
1696 enum OffsetType {
1697 OFFSET_BEGIN = 0,
1698 OFFSET_ZERO = OFFSET_BEGIN,
1699 OFFSET_LOW,
1700 OFFSET_HIGH,
1701 NUM_OFFSETS
1704 static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" };
1706 typedef struct AHCIIOTestOptions {
1707 enum BuffLen length;
1708 enum AddrMode address_type;
1709 enum IOMode io_type;
1710 enum OffsetType offset;
1711 } AHCIIOTestOptions;
1713 static uint64_t offset_sector(enum OffsetType ofst,
1714 enum AddrMode addr_type,
1715 uint64_t buffsize)
1717 uint64_t ceil;
1718 uint64_t nsectors;
1720 switch (ofst) {
1721 case OFFSET_ZERO:
1722 return 0;
1723 case OFFSET_LOW:
1724 return 1;
1725 case OFFSET_HIGH:
1726 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff;
1727 ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1);
1728 nsectors = buffsize / AHCI_SECTOR_SIZE;
1729 return ceil - nsectors + 1;
1730 default:
1731 g_assert_not_reached();
1736 * Table of possible I/O ATA commands given a set of enumerations.
1738 static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
1739 [MODE_PIO] = {
1740 [ADDR_MODE_LBA28] = {
1741 [IO_READ] = CMD_READ_PIO,
1742 [IO_WRITE] = CMD_WRITE_PIO },
1743 [ADDR_MODE_LBA48] = {
1744 [IO_READ] = CMD_READ_PIO_EXT,
1745 [IO_WRITE] = CMD_WRITE_PIO_EXT }
1747 [MODE_DMA] = {
1748 [ADDR_MODE_LBA28] = {
1749 [IO_READ] = CMD_READ_DMA,
1750 [IO_WRITE] = CMD_WRITE_DMA },
1751 [ADDR_MODE_LBA48] = {
1752 [IO_READ] = CMD_READ_DMA_EXT,
1753 [IO_WRITE] = CMD_WRITE_DMA_EXT }
1758 * Test a Read/Write pattern using various commands, addressing modes,
1759 * transfer modes, and buffer sizes.
1761 static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
1762 unsigned bufsize, uint64_t sector)
1764 AHCIQState *ahci;
1766 ahci = ahci_boot_and_enable(NULL);
1767 ahci_test_io_rw_simple(ahci, bufsize, sector,
1768 io_cmds[dma][lba48][IO_READ],
1769 io_cmds[dma][lba48][IO_WRITE]);
1770 ahci_shutdown(ahci);
1774 * Demultiplex the test data and invoke the actual test routine.
1776 static void test_io_interface(gconstpointer opaque)
1778 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
1779 unsigned bufsize;
1780 uint64_t sector;
1782 switch (opts->length) {
1783 case LEN_SIMPLE:
1784 bufsize = 4096;
1785 break;
1786 case LEN_DOUBLE:
1787 bufsize = 8192;
1788 break;
1789 case LEN_LONG:
1790 bufsize = 4096 * 64;
1791 break;
1792 case LEN_SHORT:
1793 bufsize = 512;
1794 break;
1795 default:
1796 g_assert_not_reached();
1799 sector = offset_sector(opts->offset, opts->address_type, bufsize);
1800 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector);
1801 g_free(opts);
1802 return;
1805 static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
1806 enum BuffLen len, enum OffsetType offset)
1808 char *name;
1809 AHCIIOTestOptions *opts;
1811 opts = g_new(AHCIIOTestOptions, 1);
1812 opts->length = len;
1813 opts->address_type = addr;
1814 opts->io_type = type;
1815 opts->offset = offset;
1817 name = g_strdup_printf("ahci/io/%s/%s/%s/%s",
1818 io_mode_str[type],
1819 addr_mode_str[addr],
1820 buff_len_str[len],
1821 offset_str[offset]);
1823 if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) &&
1824 (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) {
1825 g_test_message("%s: skipped; test image too small", name);
1826 g_free(opts);
1827 g_free(name);
1828 return;
1831 qtest_add_data_func(name, opts, test_io_interface);
1832 g_free(name);
1835 /******************************************************************************/
1837 int main(int argc, char **argv)
1839 const char *arch;
1840 int ret;
1841 int fd;
1842 int c;
1843 int i, j, k, m;
1845 static struct option long_options[] = {
1846 {"pedantic", no_argument, 0, 'p' },
1847 {0, 0, 0, 0},
1850 /* Should be first to utilize g_test functionality, So we can see errors. */
1851 g_test_init(&argc, &argv, NULL);
1853 while (1) {
1854 c = getopt_long(argc, argv, "", long_options, NULL);
1855 if (c == -1) {
1856 break;
1858 switch (c) {
1859 case -1:
1860 break;
1861 case 'p':
1862 ahci_pedantic = 1;
1863 break;
1864 default:
1865 fprintf(stderr, "Unrecognized ahci_test option.\n");
1866 g_assert_not_reached();
1870 /* Check architecture */
1871 arch = qtest_get_arch();
1872 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1873 g_test_message("Skipping test for non-x86");
1874 return 0;
1877 /* Create a temporary image */
1878 fd = mkstemp(tmp_path);
1879 g_assert(fd >= 0);
1880 if (have_qemu_img()) {
1881 imgfmt = "qcow2";
1882 test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE;
1883 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE);
1884 } else {
1885 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
1886 "skipping LBA48 high-sector tests");
1887 imgfmt = "raw";
1888 test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL;
1889 ret = ftruncate(fd, test_image_size_mb * 1024 * 1024);
1890 g_assert(ret == 0);
1892 close(fd);
1894 /* Create temporary blkdebug instructions */
1895 fd = mkstemp(debug_path);
1896 g_assert(fd >= 0);
1897 close(fd);
1899 /* Reserve a hollow file to use as a socket for migration tests */
1900 fd = mkstemp(mig_socket);
1901 g_assert(fd >= 0);
1902 close(fd);
1904 /* Run the tests */
1905 qtest_add_func("/ahci/sanity", test_sanity);
1906 qtest_add_func("/ahci/pci_spec", test_pci_spec);
1907 qtest_add_func("/ahci/pci_enable", test_pci_enable);
1908 qtest_add_func("/ahci/hba_spec", test_hba_spec);
1909 qtest_add_func("/ahci/hba_enable", test_hba_enable);
1910 qtest_add_func("/ahci/identify", test_identify);
1912 for (i = MODE_BEGIN; i < NUM_MODES; i++) {
1913 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
1914 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
1915 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) {
1916 create_ahci_io_test(i, j, k, m);
1922 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
1924 qtest_add_func("/ahci/flush/simple", test_flush);
1925 qtest_add_func("/ahci/flush/retry", test_flush_retry);
1926 qtest_add_func("/ahci/flush/migrate", test_flush_migrate);
1928 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity);
1929 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma);
1930 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma);
1931 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma);
1933 qtest_add_func("/ahci/max", test_max);
1934 qtest_add_func("/ahci/reset", test_reset);
1936 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple);
1937 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq);
1938 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq);
1939 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq);
1941 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma);
1942 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi);
1943 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio);
1944 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi);
1946 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl);
1947 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray);
1949 ret = g_test_run();
1951 /* Cleanup */
1952 unlink(tmp_path);
1953 unlink(debug_path);
1954 unlink(mig_socket);
1956 return ret;