Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / disas / riscv-xthead.h
blobfcd42746e7d47f36fcc92eed2e0403cd376fc3f1
1 /*
2 * QEMU disassembler -- RISC-V specific header (xthead*).
4 * Copyright (c) 2023 VRULL GmbH
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
9 #ifndef DISAS_RISCV_XTHEAD_H
10 #define DISAS_RISCV_XTHEAD_H
12 #include "disas/riscv.h"
14 extern const rv_opcode_data xthead_opcode_data[];
16 void decode_xtheadba(rv_decode *, rv_isa);
17 void decode_xtheadbb(rv_decode *, rv_isa);
18 void decode_xtheadbs(rv_decode *, rv_isa);
19 void decode_xtheadcmo(rv_decode *, rv_isa);
20 void decode_xtheadcondmov(rv_decode *, rv_isa);
21 void decode_xtheadfmemidx(rv_decode *, rv_isa);
22 void decode_xtheadfmv(rv_decode *, rv_isa);
23 void decode_xtheadmac(rv_decode *, rv_isa);
24 void decode_xtheadmemidx(rv_decode *, rv_isa);
25 void decode_xtheadmempair(rv_decode *, rv_isa);
26 void decode_xtheadsync(rv_decode *, rv_isa);
28 #endif /* DISAS_RISCV_XTHEAD_H */