hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2.1 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/irq.h"
  24 #include "hw/isa/apm.h"
  25 #include "hw/i2c/pm_smbus.h"
  26 #include "hw/pci/pci.h"
  27 #include "hw/qdev-properties.h"
  28 #include "hw/acpi/acpi.h"
  29 #include "hw/acpi/pcihp.h"
  30 #include "hw/acpi/piix4.h"
  31 #include "sysemu/runstate.h"
  32 #include "sysemu/sysemu.h"
  33 #include "sysemu/xen.h"
  34 #include "qapi/error.h"
  35 #include "qemu/range.h"
  36 #include "hw/acpi/cpu_hotplug.h"
  37 #include "hw/acpi/cpu.h"
  38 #include "hw/hotplug.h"
  39 #include "hw/mem/pc-dimm.h"
  40 #include "hw/mem/nvdimm.h"
  41 #include "hw/acpi/memory_hotplug.h"
  42 #include "hw/acpi/acpi_dev_interface.h"
  43 #include "migration/vmstate.h"
  44 #include "hw/core/cpu.h"
  45 #include "qom/object.h"
  46
  47 #define GPE_BASE 0xafe0
  48 #define GPE_LEN 4
  49
  50 #define ACPI_PCIHP_ADDR_PIIX4 0xae00
  51
  52 struct pci_status {
  53     uint32_t up; /* deprecated, maintained for migration compatibility */
  54     uint32_t down;
  55 };
  56
  57 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
  58                                            PCIBus *bus, PIIX4PMState *s);
  59
  60 #define ACPI_ENABLE 0xf1
  61 #define ACPI_DISABLE 0xf0
  62
  63 static void pm_tmr_timer(ACPIREGS *ar)
  64 {
  65     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
  66     acpi_update_sci(&s->ar, s->irq);
  67 }
  68
  69 static void apm_ctrl_changed(uint32_t val, void *arg)
  70 {
  71     PIIX4PMState *s = arg;
  72     PCIDevice *d = PCI_DEVICE(s);
  73
  74     /* ACPI specs 3.0, 4.7.2.5 */
  75     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
  76     if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
  77         return;
  78     }
  79
  80     if (d->config[0x5b] & (1 << 1)) {
  81         if (s->smi_irq) {
  82             qemu_irq_raise(s->smi_irq);
  83         }
  84     }
  85 }
  86
  87 static void pm_io_space_update(PIIX4PMState *s)
  88 {
  89     PCIDevice *d = PCI_DEVICE(s);
  90
  91     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
  92     s->io_base &= 0xffc0;
  93
  94     memory_region_transaction_begin();
  95     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
  96     memory_region_set_address(&s->io, s->io_base);
  97     memory_region_transaction_commit();
  98 }
  99
 100 static void smbus_io_space_update(PIIX4PMState *s)
 101 {
 102     PCIDevice *d = PCI_DEVICE(s);
 103
 104     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 105     s->smb_io_base &= 0xffc0;
 106
 107     memory_region_transaction_begin();
 108     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 109     memory_region_set_address(&s->smb.io, s->smb_io_base);
 110     memory_region_transaction_commit();
 111 }
 112
 113 static void pm_write_config(PCIDevice *d,
 114                             uint32_t address, uint32_t val, int len)
 115 {
 116     pci_default_write_config(d, address, val, len);
 117     if (range_covers_byte(address, len, 0x80) ||
 118         ranges_overlap(address, len, 0x40, 4)) {
 119         pm_io_space_update((PIIX4PMState *)d);
 120     }
 121     if (range_covers_byte(address, len, 0xd2) ||
 122         ranges_overlap(address, len, 0x90, 4)) {
 123         smbus_io_space_update((PIIX4PMState *)d);
 124     }
 125 }
 126
 127 static int vmstate_acpi_post_load(void *opaque, int version_id)
 128 {
 129     PIIX4PMState *s = opaque;
 130
 131     pm_io_space_update(s);
 132     smbus_io_space_update(s);
 133     return 0;
 134 }
 135
 136 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 137  {                                                                   \
 138      .name       = (stringify(_field)),                              \
 139      .version_id = 0,                                                \
 140      .info       = &vmstate_info_uint16,                             \
 141      .size       = sizeof(uint16_t),                                 \
 142      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 143      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 144  }
 145
 146 static const VMStateDescription vmstate_gpe = {
 147     .name = "gpe",
 148     .version_id = 1,
 149     .minimum_version_id = 1,
 150     .fields = (const VMStateField[]) {
 151         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 152         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 153         VMSTATE_END_OF_LIST()
 154     }
 155 };
 156
 157 static const VMStateDescription vmstate_pci_status = {
 158     .name = "pci_status",
 159     .version_id = 1,
 160     .minimum_version_id = 1,
 161     .fields = (const VMStateField[]) {
 162         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 163         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 164         VMSTATE_END_OF_LIST()
 165     }
 166 };
 167
 168 static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque, int version_id)
 169 {
 170     PIIX4PMState *s = opaque;
 171     return s->acpi_pci_hotplug.use_acpi_hotplug_bridge;
 172 }
 173
 174 static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque,
 175                                                     int version_id)
 176 {
 177     PIIX4PMState *s = opaque;
 178     return !s->acpi_pci_hotplug.use_acpi_hotplug_bridge;
 179 }
 180
 181 static bool vmstate_test_use_memhp(void *opaque)
 182 {
 183     PIIX4PMState *s = opaque;
 184     return s->acpi_memory_hotplug.is_enabled;
 185 }
 186
 187 static const VMStateDescription vmstate_memhp_state = {
 188     .name = "piix4_pm/memhp",
 189     .version_id = 1,
 190     .minimum_version_id = 1,
 191     .needed = vmstate_test_use_memhp,
 192     .fields = (const VMStateField[]) {
 193         VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
 194         VMSTATE_END_OF_LIST()
 195     }
 196 };
 197
 198 static bool vmstate_test_use_cpuhp(void *opaque)
 199 {
 200     PIIX4PMState *s = opaque;
 201     return !s->cpu_hotplug_legacy;
 202 }
 203
 204 static int vmstate_cpuhp_pre_load(void *opaque)
 205 {
 206     Object *obj = OBJECT(opaque);
 207     object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort);
 208     return 0;
 209 }
 210
 211 static const VMStateDescription vmstate_cpuhp_state = {
 212     .name = "piix4_pm/cpuhp",
 213     .version_id = 1,
 214     .minimum_version_id = 1,
 215     .needed = vmstate_test_use_cpuhp,
 216     .pre_load = vmstate_cpuhp_pre_load,
 217     .fields = (const VMStateField[]) {
 218         VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState),
 219         VMSTATE_END_OF_LIST()
 220     }
 221 };
 222
 223 static bool piix4_vmstate_need_smbus(void *opaque, int version_id)
 224 {
 225     return pm_smbus_vmstate_needed();
 226 }
 227
 228 /*
 229  * This is a fudge to turn off the acpi_index field,
 230  * whose test was always broken on piix4 with 6.2 and older machine types.
 231  */
 232 static bool vmstate_test_migrate_acpi_index(void *opaque, int version_id)
 233 {
 234     PIIX4PMState *s = PIIX4_PM(opaque);
 235     return s->acpi_pci_hotplug.use_acpi_hotplug_bridge &&
 236            !s->not_migrate_acpi_index;
 237 }
 238
 239 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 240  * To support incoming qemu-kvm 1.2 migration, change version_id
 241  * and minimum_version_id to 2 below (which breaks migration from
 242  * qemu 1.2).
 243  *
 244  */
 245 static const VMStateDescription vmstate_acpi = {
 246     .name = "piix4_pm",
 247     .version_id = 3,
 248     .minimum_version_id = 3,
 249     .post_load = vmstate_acpi_post_load,
 250     .fields = (const VMStateField[]) {
 251         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 252         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 253         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 254         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 255         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 256         VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3,
 257                             pmsmb_vmstate, PMSMBus),
 258         VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
 259         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 260         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 261         VMSTATE_STRUCT_TEST(
 262             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 263             PIIX4PMState,
 264             vmstate_test_no_use_acpi_hotplug_bridge,
 265             2, vmstate_pci_status,
 266             struct AcpiPciHpPciStatus),
 267         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 268                             vmstate_test_use_acpi_hotplug_bridge,
 269                             vmstate_test_migrate_acpi_index),
 270         VMSTATE_END_OF_LIST()
 271     },
 272     .subsections = (const VMStateDescription * const []) {
 273          &vmstate_memhp_state,
 274          &vmstate_cpuhp_state,
 275          NULL
 276     }
 277 };
 278
 279 static void piix4_pm_reset(DeviceState *dev)
 280 {
 281     PIIX4PMState *s = PIIX4_PM(dev);
 282     PCIDevice *d = PCI_DEVICE(s);
 283     uint8_t *pci_conf = d->config;
 284
 285     pci_conf[0x58] = 0;
 286     pci_conf[0x59] = 0;
 287     pci_conf[0x5a] = 0;
 288     pci_conf[0x5b] = 0;
 289
 290     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 291     pci_conf[0x80] = 0;
 292
 293     if (!s->smm_enabled) {
 294         /* Mark SMM as already inited (until KVM supports SMM). */
 295         pci_conf[0x5B] = 0x02;
 296     }
 297
 298     acpi_pm1_evt_reset(&s->ar);
 299     acpi_pm1_cnt_reset(&s->ar);
 300     acpi_pm_tmr_reset(&s->ar);
 301     acpi_gpe_reset(&s->ar);
 302     acpi_update_sci(&s->ar, s->irq);
 303
 304     pm_io_space_update(s);
 305     if (s->acpi_pci_hotplug.use_acpi_hotplug_bridge ||
 306         s->acpi_pci_hotplug.use_acpi_root_pci_hotplug) {
 307         acpi_pcihp_reset(&s->acpi_pci_hotplug);
 308     }
 309 }
 310
 311 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 312 {
 313     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 314
 315     assert(s != NULL);
 316     acpi_pm1_evt_power_down(&s->ar);
 317 }
 318
 319 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev,
 320                                     DeviceState *dev, Error **errp)
 321 {
 322     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 323
 324     if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 325         acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp);
 326     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 327         if (!s->acpi_memory_hotplug.is_enabled) {
 328             error_setg(errp,
 329                 "memory hotplug is not enabled: %s.memory-hotplug-support "
 330                 "is not set", object_get_typename(OBJECT(s)));
 331         }
 332     } else if (
 333                !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 334         error_setg(errp, "acpi: device pre plug request for not supported"
 335                    " device type: %s", object_get_typename(OBJECT(dev)));
 336     }
 337 }
 338
 339 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
 340                                  DeviceState *dev, Error **errp)
 341 {
 342     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 343
 344     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 345         if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
 346             nvdimm_acpi_plug_cb(hotplug_dev, dev);
 347         } else {
 348             acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug,
 349                                 dev, errp);
 350         }
 351     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 352         acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp);
 353     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 354         if (s->cpu_hotplug_legacy) {
 355             legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp);
 356         } else {
 357             acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 358         }
 359     } else {
 360         g_assert_not_reached();
 361     }
 362 }
 363
 364 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 365                                            DeviceState *dev, Error **errp)
 366 {
 367     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 368
 369     if (s->acpi_memory_hotplug.is_enabled &&
 370         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 371         acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug,
 372                                       dev, errp);
 373     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 374         acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug,
 375                                             dev, errp);
 376     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 377                !s->cpu_hotplug_legacy) {
 378         acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 379     } else {
 380         error_setg(errp, "acpi: device unplug request for not supported device"
 381                    " type: %s", object_get_typename(OBJECT(dev)));
 382     }
 383 }
 384
 385 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
 386                                    DeviceState *dev, Error **errp)
 387 {
 388     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 389
 390     if (s->acpi_memory_hotplug.is_enabled &&
 391         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 392         acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
 393     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 394         acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev,
 395                                     errp);
 396     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 397                !s->cpu_hotplug_legacy) {
 398         acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
 399     } else {
 400         error_setg(errp, "acpi: device unplug for not supported device"
 401                    " type: %s", object_get_typename(OBJECT(dev)));
 402     }
 403 }
 404
 405 static bool piix4_is_hotpluggable_bus(HotplugHandler *hotplug_dev,
 406                                       BusState *bus)
 407 {
 408     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 409     return acpi_pcihp_is_hotpluggbale_bus(&s->acpi_pci_hotplug, bus);
 410 }
 411
 412 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 413 {
 414     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 415     PCIDevice *d = PCI_DEVICE(s);
 416     MemoryRegion *io_as = pci_address_space_io(d);
 417     uint8_t *pci_conf;
 418
 419     pci_conf = d->config;
 420     pci_conf[0x5f] = 0x10 |
 421         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 422     pci_conf[0x63] = 0x60;
 423     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 424         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 425 }
 426
 427 static void piix4_pm_add_properties(PIIX4PMState *s)
 428 {
 429     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 430     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 431     static const uint32_t gpe0_blk = GPE_BASE;
 432     static const uint32_t gpe0_blk_len = GPE_LEN;
 433     static const uint16_t sci_int = 9;
 434
 435     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 436                                   &acpi_enable_cmd, OBJ_PROP_FLAG_READ);
 437     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 438                                   &acpi_disable_cmd, OBJ_PROP_FLAG_READ);
 439     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 440                                   &gpe0_blk, OBJ_PROP_FLAG_READ);
 441     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 442                                   &gpe0_blk_len, OBJ_PROP_FLAG_READ);
 443     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 444                                   &sci_int, OBJ_PROP_FLAG_READ);
 445     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 446                                   &s->io_base, OBJ_PROP_FLAG_READ);
 447 }
 448
 449 static void piix4_pm_realize(PCIDevice *dev, Error **errp)
 450 {
 451     PIIX4PMState *s = PIIX4_PM(dev);
 452     uint8_t *pci_conf;
 453
 454     pci_conf = dev->config;
 455     pci_conf[0x06] = 0x80;
 456     pci_conf[0x07] = 0x02;
 457     pci_conf[0x09] = 0x00;
 458     pci_conf[0x3d] = 0x01; // interrupt pin 1
 459
 460     /* APM */
 461     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 462
 463     if (!s->smm_enabled) {
 464         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 465          * support SMM mode. */
 466         pci_conf[0x5B] = 0x02;
 467     }
 468
 469     /* XXX: which specification is used ? The i82731AB has different
 470        mappings */
 471     pci_conf[0x90] = s->smb_io_base | 1;
 472     pci_conf[0x91] = s->smb_io_base >> 8;
 473     pci_conf[0xd2] = 0x09;
 474     pm_smbus_init(DEVICE(dev), &s->smb, true);
 475     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 476     memory_region_add_subregion(pci_address_space_io(dev),
 477                                 s->smb_io_base, &s->smb.io);
 478
 479     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 480     memory_region_set_enabled(&s->io, false);
 481     memory_region_add_subregion(pci_address_space_io(dev),
 482                                 0, &s->io);
 483
 484     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 485     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 486     acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val,
 487                       !s->smm_compat && !s->smm_enabled);
 488     acpi_gpe_init(&s->ar, GPE_LEN);
 489
 490     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 491     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 492
 493     s->machine_ready.notify = piix4_pm_machine_ready;
 494     qemu_add_machine_init_done_notifier(&s->machine_ready);
 495
 496     if (xen_enabled()) {
 497         s->acpi_pci_hotplug.use_acpi_hotplug_bridge = false;
 498     }
 499
 500     piix4_acpi_system_hot_add_init(pci_address_space_io(dev),
 501                                    pci_get_bus(dev), s);
 502
 503     piix4_pm_add_properties(s);
 504 }
 505
 506 static void piix4_pm_init(Object *obj)
 507 {
 508     PIIX4PMState *s = PIIX4_PM(obj);
 509
 510     qdev_init_gpio_out(DEVICE(obj), &s->irq, 1);
 511     qdev_init_gpio_out_named(DEVICE(obj), &s->smi_irq, "smi-irq", 1);
 512 }
 513
 514 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 515 {
 516     PIIX4PMState *s = opaque;
 517     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 518
 519     return val;
 520 }
 521
 522 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 523                        unsigned width)
 524 {
 525     PIIX4PMState *s = opaque;
 526
 527     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 528     acpi_update_sci(&s->ar, s->irq);
 529 }
 530
 531 static const MemoryRegionOps piix4_gpe_ops = {
 532     .read = gpe_readb,
 533     .write = gpe_writeb,
 534     .valid.min_access_size = 1,
 535     .valid.max_access_size = 4,
 536     .impl.min_access_size = 1,
 537     .impl.max_access_size = 1,
 538     .endianness = DEVICE_LITTLE_ENDIAN,
 539 };
 540
 541
 542 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp)
 543 {
 544     PIIX4PMState *s = PIIX4_PM(obj);
 545
 546     return s->cpu_hotplug_legacy;
 547 }
 548
 549 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp)
 550 {
 551     PIIX4PMState *s = PIIX4_PM(obj);
 552
 553     assert(!value);
 554     if (s->cpu_hotplug_legacy && value == false) {
 555         acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state,
 556                                    PIIX4_CPU_HOTPLUG_IO_BASE);
 557     }
 558     s->cpu_hotplug_legacy = value;
 559 }
 560
 561 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 562                                            PCIBus *bus, PIIX4PMState *s)
 563 {
 564     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 565                           "acpi-gpe0", GPE_LEN);
 566     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 567
 568     if (s->acpi_pci_hotplug.use_acpi_hotplug_bridge ||
 569         s->acpi_pci_hotplug.use_acpi_root_pci_hotplug) {
 570         acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
 571                         ACPI_PCIHP_ADDR_PIIX4);
 572         qbus_set_hotplug_handler(BUS(pci_get_bus(PCI_DEVICE(s))), OBJECT(s));
 573     }
 574
 575     s->cpu_hotplug_legacy = true;
 576     object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy",
 577                              piix4_get_cpu_hotplug_legacy,
 578                              piix4_set_cpu_hotplug_legacy);
 579     legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 580                                  PIIX4_CPU_HOTPLUG_IO_BASE);
 581
 582     if (s->acpi_memory_hotplug.is_enabled) {
 583         acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug,
 584                                  ACPI_MEMORY_HOTPLUG_BASE);
 585     }
 586 }
 587
 588 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
 589 {
 590     PIIX4PMState *s = PIIX4_PM(adev);
 591
 592     acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
 593     if (!s->cpu_hotplug_legacy) {
 594         acpi_cpu_ospm_status(&s->cpuhp_state, list);
 595     }
 596 }
 597
 598 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
 599 {
 600     PIIX4PMState *s = PIIX4_PM(adev);
 601
 602     acpi_send_gpe_event(&s->ar, s->irq, ev);
 603 }
 604
 605 static Property piix4_pm_properties[] = {
 606     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 607     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 608     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 609     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 610     DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, PIIX4PMState,
 611                      acpi_pci_hotplug.use_acpi_hotplug_bridge, true),
 612     DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCI_ROOTHP, PIIX4PMState,
 613                      acpi_pci_hotplug.use_acpi_root_pci_hotplug, true),
 614     DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
 615                      acpi_memory_hotplug.is_enabled, true),
 616     DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false),
 617     DEFINE_PROP_BOOL("smm-enabled", PIIX4PMState, smm_enabled, false),
 618     DEFINE_PROP_BOOL("x-not-migrate-acpi-index", PIIX4PMState,
 619                       not_migrate_acpi_index, false),
 620     DEFINE_PROP_END_OF_LIST(),
 621 };
 622
 623 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 624 {
 625     DeviceClass *dc = DEVICE_CLASS(klass);
 626     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 627     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 628     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 629
 630     k->realize = piix4_pm_realize;
 631     k->config_write = pm_write_config;
 632     k->vendor_id = PCI_VENDOR_ID_INTEL;
 633     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 634     k->revision = 0x03;
 635     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 636     device_class_set_legacy_reset(dc, piix4_pm_reset);
 637     dc->desc = "PM";
 638     dc->vmsd = &vmstate_acpi;
 639     device_class_set_props(dc, piix4_pm_properties);
 640     /*
 641      * Reason: part of PIIX4 southbridge, needs to be wired up,
 642      * e.g. by mips_malta_init()
 643      */
 644     dc->user_creatable = false;
 645     dc->hotpluggable = false;
 646     hc->pre_plug = piix4_device_pre_plug_cb;
 647     hc->plug = piix4_device_plug_cb;
 648     hc->unplug_request = piix4_device_unplug_request_cb;
 649     hc->unplug = piix4_device_unplug_cb;
 650     hc->is_hotpluggable_bus = piix4_is_hotpluggable_bus;
 651     adevc->ospm_status = piix4_ospm_status;
 652     adevc->send_event = piix4_send_gpe;
 653 }
 654
 655 static const TypeInfo piix4_pm_info = {
 656     .name          = TYPE_PIIX4_PM,
 657     .parent        = TYPE_PCI_DEVICE,
 658     .instance_init  = piix4_pm_init,
 659     .instance_size = sizeof(PIIX4PMState),
 660     .class_init    = piix4_pm_class_init,
 661     .interfaces = (InterfaceInfo[]) {
 662         { TYPE_HOTPLUG_HANDLER },
 663         { TYPE_ACPI_DEVICE_IF },
 664         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 665         { }
 666     }
 667 };
 668
 669 static void piix4_pm_register_types(void)
 670 {
 671     type_register_static(&piix4_pm_info);
 672 }
 673
 674 type_init(piix4_pm_register_types)