Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / hw / arm / fsl-imx6ul.c
blob19f443570bffd0d21f7ef779f2d40633d23ae8bd
1 /*
2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
4 * i.MX6UL SOC emulation.
6 * Based on hw/arm/fsl-imx7.c
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
21 #include "hw/arm/fsl-imx6ul.h"
22 #include "hw/misc/unimp.h"
23 #include "hw/usb/imx-usb-phy.h"
24 #include "hw/boards.h"
25 #include "sysemu/sysemu.h"
26 #include "qemu/error-report.h"
27 #include "qemu/module.h"
28 #include "target/arm/cpu-qom.h"
30 #define NAME_SIZE 20
32 static void fsl_imx6ul_init(Object *obj)
34 FslIMX6ULState *s = FSL_IMX6UL(obj);
35 char name[NAME_SIZE];
36 int i;
38 object_initialize_child(obj, "cpu0", &s->cpu,
39 ARM_CPU_TYPE_NAME("cortex-a7"));
42 * A7MPCORE
44 object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
45 TYPE_A15MPCORE_PRIV);
48 * CCM
50 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM);
53 * SRC
55 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
58 * GPCv2
60 object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
63 * SNVS
65 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
68 * GPIOs
70 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
71 snprintf(name, NAME_SIZE, "gpio%d", i);
72 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
76 * GPTs
78 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
79 snprintf(name, NAME_SIZE, "gpt%d", i);
80 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT);
84 * EPITs
86 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
87 snprintf(name, NAME_SIZE, "epit%d", i + 1);
88 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
92 * eCSPIs
94 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
95 snprintf(name, NAME_SIZE, "spi%d", i + 1);
96 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
100 * I2Cs
102 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
103 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
104 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
108 * UARTs
110 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
111 snprintf(name, NAME_SIZE, "uart%d", i);
112 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
116 * Ethernets
118 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
119 snprintf(name, NAME_SIZE, "eth%d", i);
120 object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
124 * USB PHYs
126 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
127 snprintf(name, NAME_SIZE, "usbphy%d", i);
128 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
132 * USBs
134 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
135 snprintf(name, NAME_SIZE, "usb%d", i);
136 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
140 * SDHCIs
142 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
143 snprintf(name, NAME_SIZE, "usdhc%d", i);
144 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
148 * Watchdogs
150 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
151 snprintf(name, NAME_SIZE, "wdt%d", i);
152 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
156 static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
158 MachineState *ms = MACHINE(qdev_get_machine());
159 FslIMX6ULState *s = FSL_IMX6UL(dev);
160 int i;
161 char name[NAME_SIZE];
162 SysBusDevice *sbd;
163 DeviceState *d;
165 if (ms->smp.cpus > 1) {
166 error_setg(errp, "%s: Only a single CPU is supported (%d requested)",
167 TYPE_FSL_IMX6UL, ms->smp.cpus);
168 return;
171 qdev_realize(DEVICE(&s->cpu), NULL, &error_abort);
174 * A7MPCORE
176 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", 1, &error_abort);
177 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
178 FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort);
179 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
180 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
182 sbd = SYS_BUS_DEVICE(&s->a7mpcore);
183 d = DEVICE(&s->cpu);
185 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ));
186 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ));
187 sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ));
188 sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ));
191 * A7MPCORE DAP
193 create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
194 FSL_IMX6UL_A7MPCORE_DAP_SIZE);
197 * MMDC
199 create_unimplemented_device("a7mpcore-mmdc", FSL_IMX6UL_MMDC_CFG_ADDR,
200 FSL_IMX6UL_MMDC_CFG_SIZE);
203 * OCOTP
205 create_unimplemented_device("a7mpcore-ocotp", FSL_IMX6UL_OCOTP_CTRL_ADDR,
206 FSL_IMX6UL_OCOTP_CTRL_SIZE);
209 * QSPI
211 create_unimplemented_device("a7mpcore-qspi", FSL_IMX6UL_QSPI_ADDR,
212 FSL_IMX6UL_QSPI_SIZE);
215 * CAAM
217 create_unimplemented_device("a7mpcore-qspi", FSL_IMX6UL_CAAM_ADDR,
218 FSL_IMX6UL_CAAM_SIZE);
221 * USBMISC
223 create_unimplemented_device("a7mpcore-usbmisc", FSL_IMX6UL_USBO2_USBMISC_ADDR,
224 FSL_IMX6UL_USBO2_USBMISC_SIZE);
227 * GPTs
229 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
230 static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
231 FSL_IMX6UL_GPT1_ADDR,
232 FSL_IMX6UL_GPT2_ADDR,
235 static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = {
236 FSL_IMX6UL_GPT1_IRQ,
237 FSL_IMX6UL_GPT2_IRQ,
240 s->gpt[i].ccm = IMX_CCM(&s->ccm);
241 sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
243 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
244 FSL_IMX6UL_GPTn_ADDR[i]);
246 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
247 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
248 FSL_IMX6UL_GPTn_IRQ[i]));
252 * EPITs
254 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
255 static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
256 FSL_IMX6UL_EPIT1_ADDR,
257 FSL_IMX6UL_EPIT2_ADDR,
260 static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = {
261 FSL_IMX6UL_EPIT1_IRQ,
262 FSL_IMX6UL_EPIT2_IRQ,
265 s->epit[i].ccm = IMX_CCM(&s->ccm);
266 sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &error_abort);
268 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
269 FSL_IMX6UL_EPITn_ADDR[i]);
271 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
272 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
273 FSL_IMX6UL_EPITn_IRQ[i]));
277 * GPIOs
279 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
280 static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
281 FSL_IMX6UL_GPIO1_ADDR,
282 FSL_IMX6UL_GPIO2_ADDR,
283 FSL_IMX6UL_GPIO3_ADDR,
284 FSL_IMX6UL_GPIO4_ADDR,
285 FSL_IMX6UL_GPIO5_ADDR,
288 static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
289 FSL_IMX6UL_GPIO1_LOW_IRQ,
290 FSL_IMX6UL_GPIO2_LOW_IRQ,
291 FSL_IMX6UL_GPIO3_LOW_IRQ,
292 FSL_IMX6UL_GPIO4_LOW_IRQ,
293 FSL_IMX6UL_GPIO5_LOW_IRQ,
296 static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
297 FSL_IMX6UL_GPIO1_HIGH_IRQ,
298 FSL_IMX6UL_GPIO2_HIGH_IRQ,
299 FSL_IMX6UL_GPIO3_HIGH_IRQ,
300 FSL_IMX6UL_GPIO4_HIGH_IRQ,
301 FSL_IMX6UL_GPIO5_HIGH_IRQ,
304 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
306 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
307 FSL_IMX6UL_GPIOn_ADDR[i]);
309 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
310 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
311 FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
313 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
314 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
315 FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
319 * IOMUXC
321 create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
322 FSL_IMX6UL_IOMUXC_SIZE);
323 create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
324 FSL_IMX6UL_IOMUXC_GPR_SIZE);
327 * CCM
329 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
330 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
333 * SRC
335 sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
336 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
339 * GPCv2
341 sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
342 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
345 * ECSPIs
347 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
348 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
349 FSL_IMX6UL_ECSPI1_ADDR,
350 FSL_IMX6UL_ECSPI2_ADDR,
351 FSL_IMX6UL_ECSPI3_ADDR,
352 FSL_IMX6UL_ECSPI4_ADDR,
355 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = {
356 FSL_IMX6UL_ECSPI1_IRQ,
357 FSL_IMX6UL_ECSPI2_IRQ,
358 FSL_IMX6UL_ECSPI3_IRQ,
359 FSL_IMX6UL_ECSPI4_IRQ,
362 /* Initialize the SPI */
363 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
365 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
366 FSL_IMX6UL_SPIn_ADDR[i]);
368 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
369 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
370 FSL_IMX6UL_SPIn_IRQ[i]));
374 * I2Cs
376 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
377 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
378 FSL_IMX6UL_I2C1_ADDR,
379 FSL_IMX6UL_I2C2_ADDR,
380 FSL_IMX6UL_I2C3_ADDR,
381 FSL_IMX6UL_I2C4_ADDR,
384 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = {
385 FSL_IMX6UL_I2C1_IRQ,
386 FSL_IMX6UL_I2C2_IRQ,
387 FSL_IMX6UL_I2C3_IRQ,
388 FSL_IMX6UL_I2C4_IRQ,
391 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
392 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
394 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
395 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
396 FSL_IMX6UL_I2Cn_IRQ[i]));
400 * UARTs
402 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
403 static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
404 FSL_IMX6UL_UART1_ADDR,
405 FSL_IMX6UL_UART2_ADDR,
406 FSL_IMX6UL_UART3_ADDR,
407 FSL_IMX6UL_UART4_ADDR,
408 FSL_IMX6UL_UART5_ADDR,
409 FSL_IMX6UL_UART6_ADDR,
410 FSL_IMX6UL_UART7_ADDR,
411 FSL_IMX6UL_UART8_ADDR,
414 static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = {
415 FSL_IMX6UL_UART1_IRQ,
416 FSL_IMX6UL_UART2_IRQ,
417 FSL_IMX6UL_UART3_IRQ,
418 FSL_IMX6UL_UART4_IRQ,
419 FSL_IMX6UL_UART5_IRQ,
420 FSL_IMX6UL_UART6_IRQ,
421 FSL_IMX6UL_UART7_IRQ,
422 FSL_IMX6UL_UART8_IRQ,
425 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
427 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
429 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
430 FSL_IMX6UL_UARTn_ADDR[i]);
432 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
433 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
434 FSL_IMX6UL_UARTn_IRQ[i]));
438 * Ethernets
440 * We must use two loops since phy_connected affects the other interface
441 * and we have to set all properties before calling sysbus_realize().
443 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
444 object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected",
445 s->phy_connected[i], &error_abort);
447 * If the MDIO bus on this controller is not connected, assume the
448 * other controller provides support for it.
450 if (!s->phy_connected[i]) {
451 object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer",
452 OBJECT(&s->eth[i]), &error_abort);
456 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
457 static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = {
458 FSL_IMX6UL_ENET1_ADDR,
459 FSL_IMX6UL_ENET2_ADDR,
462 static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = {
463 FSL_IMX6UL_ENET1_IRQ,
464 FSL_IMX6UL_ENET2_IRQ,
467 static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = {
468 FSL_IMX6UL_ENET1_TIMER_IRQ,
469 FSL_IMX6UL_ENET2_TIMER_IRQ,
472 object_property_set_uint(OBJECT(&s->eth[i]), "phy-num",
473 s->phy_num[i], &error_abort);
474 object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num",
475 FSL_IMX6UL_ETH_NUM_TX_RINGS, &error_abort);
476 qemu_configure_nic_device(DEVICE(&s->eth[i]), true, NULL);
477 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
479 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
480 FSL_IMX6UL_ENETn_ADDR[i]);
482 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
483 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
484 FSL_IMX6UL_ENETn_IRQ[i]));
486 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
487 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
488 FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
492 * USB PHYs
494 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
495 static const hwaddr
496 FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
497 FSL_IMX6UL_USBPHY1_ADDR,
498 FSL_IMX6UL_USBPHY2_ADDR,
501 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
502 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
503 FSL_IMX6UL_USB_PHYn_ADDR[i]);
507 * USBs
509 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
510 static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
511 FSL_IMX6UL_USBO2_USB1_ADDR,
512 FSL_IMX6UL_USBO2_USB2_ADDR,
515 static const int FSL_IMX6UL_USBn_IRQ[] = {
516 FSL_IMX6UL_USB1_IRQ,
517 FSL_IMX6UL_USB2_IRQ,
520 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
521 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
522 FSL_IMX6UL_USB02_USBn_ADDR[i]);
523 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
524 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
525 FSL_IMX6UL_USBn_IRQ[i]));
529 * USDHCs
531 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
532 static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
533 FSL_IMX6UL_USDHC1_ADDR,
534 FSL_IMX6UL_USDHC2_ADDR,
537 static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = {
538 FSL_IMX6UL_USDHC1_IRQ,
539 FSL_IMX6UL_USDHC2_IRQ,
542 object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor",
543 SDHCI_VENDOR_IMX, &error_abort);
544 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
546 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
547 FSL_IMX6UL_USDHCn_ADDR[i]);
549 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
550 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
551 FSL_IMX6UL_USDHCn_IRQ[i]));
555 * SNVS
557 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
558 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
561 * Watchdogs
563 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
564 static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
565 FSL_IMX6UL_WDOG1_ADDR,
566 FSL_IMX6UL_WDOG2_ADDR,
567 FSL_IMX6UL_WDOG3_ADDR,
570 static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
571 FSL_IMX6UL_WDOG1_IRQ,
572 FSL_IMX6UL_WDOG2_IRQ,
573 FSL_IMX6UL_WDOG3_IRQ,
576 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
577 true, &error_abort);
578 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
580 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
581 FSL_IMX6UL_WDOGn_ADDR[i]);
582 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
583 qdev_get_gpio_in(DEVICE(&s->a7mpcore),
584 FSL_IMX6UL_WDOGn_IRQ[i]));
588 * SDMA
590 create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
591 FSL_IMX6UL_SDMA_SIZE);
594 * SAIs (Audio SSI (Synchronous Serial Interface))
596 for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
597 static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
598 FSL_IMX6UL_SAI1_ADDR,
599 FSL_IMX6UL_SAI2_ADDR,
600 FSL_IMX6UL_SAI3_ADDR,
603 snprintf(name, NAME_SIZE, "sai%d", i);
604 create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
605 FSL_IMX6UL_SAIn_SIZE);
609 * PWMs
611 for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
612 static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
613 FSL_IMX6UL_PWM1_ADDR,
614 FSL_IMX6UL_PWM2_ADDR,
615 FSL_IMX6UL_PWM3_ADDR,
616 FSL_IMX6UL_PWM4_ADDR,
617 FSL_IMX6UL_PWM5_ADDR,
618 FSL_IMX6UL_PWM6_ADDR,
619 FSL_IMX6UL_PWM7_ADDR,
620 FSL_IMX6UL_PWM8_ADDR,
623 snprintf(name, NAME_SIZE, "pwm%d", i);
624 create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
625 FSL_IMX6UL_PWMn_SIZE);
629 * Audio ASRC (asynchronous sample rate converter)
631 create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
632 FSL_IMX6UL_ASRC_SIZE);
635 * CANs
637 for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
638 static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
639 FSL_IMX6UL_CAN1_ADDR,
640 FSL_IMX6UL_CAN2_ADDR,
643 snprintf(name, NAME_SIZE, "can%d", i);
644 create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
645 FSL_IMX6UL_CANn_SIZE);
649 * APHB_DMA
651 create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR,
652 FSL_IMX6UL_APBH_DMA_SIZE);
655 * ADCs
657 for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) {
658 static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = {
659 FSL_IMX6UL_ADC1_ADDR,
660 FSL_IMX6UL_ADC2_ADDR,
663 snprintf(name, NAME_SIZE, "adc%d", i);
664 create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
665 FSL_IMX6UL_ADCn_SIZE);
669 * LCD
671 create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
672 FSL_IMX6UL_LCDIF_SIZE);
675 * CSU
677 create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
678 FSL_IMX6UL_CSU_SIZE);
681 * TZASC
683 create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
684 FSL_IMX6UL_TZASC_SIZE);
687 * ROM memory
689 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6ul.rom",
690 FSL_IMX6UL_ROM_SIZE, &error_abort);
691 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR,
692 &s->rom);
695 * CAAM memory
697 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6ul.caam",
698 FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort);
699 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR,
700 &s->caam);
703 * OCRAM memory
705 memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram",
706 FSL_IMX6UL_OCRAM_MEM_SIZE,
707 &error_abort);
708 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR,
709 &s->ocram);
712 * internal OCRAM (128 KB) is aliased over 512 KB
714 memory_region_init_alias(&s->ocram_alias, OBJECT(dev),
715 "imx6ul.ocram_alias", &s->ocram, 0,
716 FSL_IMX6UL_OCRAM_ALIAS_SIZE);
717 memory_region_add_subregion(get_system_memory(),
718 FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
721 static Property fsl_imx6ul_properties[] = {
722 DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
723 DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
724 DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX6ULState, phy_connected[0],
725 true),
726 DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX6ULState, phy_connected[1],
727 true),
728 DEFINE_PROP_END_OF_LIST(),
731 static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
733 DeviceClass *dc = DEVICE_CLASS(oc);
735 device_class_set_props(dc, fsl_imx6ul_properties);
736 dc->realize = fsl_imx6ul_realize;
737 dc->desc = "i.MX6UL SOC";
738 /* Reason: Uses serial_hds and nd_table in realize() directly */
739 dc->user_creatable = false;
742 static const TypeInfo fsl_imx6ul_type_info = {
743 .name = TYPE_FSL_IMX6UL,
744 .parent = TYPE_DEVICE,
745 .instance_size = sizeof(FslIMX6ULState),
746 .instance_init = fsl_imx6ul_init,
747 .class_init = fsl_imx6ul_class_init,
750 static void fsl_imx6ul_register_types(void)
752 type_register_static(&fsl_imx6ul_type_info);
754 type_init(fsl_imx6ul_register_types)