2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2019, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/dma.h"
17 #include "sysemu/reset.h"
18 #include "hw/ppc/fdt.h"
19 #include "hw/ppc/pnv.h"
20 #include "hw/ppc/pnv_chip.h"
21 #include "hw/ppc/pnv_core.h"
22 #include "hw/ppc/pnv_xscom.h"
23 #include "hw/ppc/pnv_xive.h"
24 #include "hw/ppc/xive_regs.h"
25 #include "hw/qdev-properties.h"
26 #include "hw/ppc/ppc.h"
31 #include "pnv_xive_regs.h"
36 * Virtual structures table (VST)
38 #define SBE_PER_BYTE 4
40 typedef struct XiveVstInfo
{
46 static const XiveVstInfo vst_infos
[] = {
47 [VST_TSEL_IVT
] = { "EAT", sizeof(XiveEAS
), 16 },
48 [VST_TSEL_SBE
] = { "SBE", 1, 16 },
49 [VST_TSEL_EQDT
] = { "ENDT", sizeof(XiveEND
), 16 },
50 [VST_TSEL_VPDT
] = { "VPDT", sizeof(XiveNVT
), 32 },
53 * Interrupt fifo backing store table (not modeled) :
58 * 3 - Second escalate,
60 * 5 - IPI cascaded queue ?
62 [VST_TSEL_IRQ
] = { "IRQ", 1, 6 },
65 #define xive_error(xive, fmt, ...) \
66 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \
67 (xive)->chip->chip_id, ## __VA_ARGS__);
70 * When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID
71 * field overrides the hardwired chip ID in the Powerbus operations
72 * and for CAM compares
74 static uint8_t pnv_xive_block_id(PnvXive
*xive
)
76 uint8_t blk
= xive
->chip
->chip_id
;
77 uint64_t cfg_val
= xive
->regs
[PC_TCTXT_CFG
>> 3];
79 if (cfg_val
& PC_TCTXT_CHIPID_OVERRIDE
) {
80 blk
= GETFIELD(PC_TCTXT_CHIPID
, cfg_val
);
87 * VST accessors for SBE, EAT, ENDT, NVT
89 * Indirect VST tables are arrays of VSDs pointing to a page (of same
90 * size). Each page is a direct VST table.
93 #define XIVE_VSD_SIZE 8
95 /* Indirect page size can be 4K, 64K, 2M, 16M. */
96 static uint64_t pnv_xive_vst_page_size_allowed(uint32_t page_shift
)
98 return page_shift
== 12 || page_shift
== 16 ||
99 page_shift
== 21 || page_shift
== 24;
102 static uint64_t pnv_xive_vst_addr_direct(PnvXive
*xive
, uint32_t type
,
103 uint64_t vsd
, uint32_t idx
)
105 const XiveVstInfo
*info
= &vst_infos
[type
];
106 uint64_t vst_addr
= vsd
& VSD_ADDRESS_MASK
;
107 uint64_t vst_tsize
= 1ull << (GETFIELD(VSD_TSIZE
, vsd
) + 12);
110 idx_max
= vst_tsize
/ info
->size
- 1;
113 xive_error(xive
, "VST: %s entry %x out of range [ 0 .. %x ] !?",
114 info
->name
, idx
, idx_max
);
119 return vst_addr
+ idx
* info
->size
;
122 static uint64_t pnv_xive_vst_addr_indirect(PnvXive
*xive
, uint32_t type
,
123 uint64_t vsd
, uint32_t idx
)
125 const XiveVstInfo
*info
= &vst_infos
[type
];
129 uint32_t vst_per_page
;
131 /* Get the page size of the indirect table. */
132 vsd_addr
= vsd
& VSD_ADDRESS_MASK
;
133 if (ldq_be_dma(&address_space_memory
, vsd_addr
, &vsd
,
134 MEMTXATTRS_UNSPECIFIED
)) {
135 xive_error(xive
, "VST: failed to access %s entry %x @0x%" PRIx64
,
136 info
->name
, idx
, vsd_addr
);
140 if (!(vsd
& VSD_ADDRESS_MASK
)) {
142 xive_error(xive
, "VST: invalid %s entry %x !?", info
->name
, idx
);
147 page_shift
= GETFIELD(VSD_TSIZE
, vsd
) + 12;
149 if (!pnv_xive_vst_page_size_allowed(page_shift
)) {
150 xive_error(xive
, "VST: invalid %s page shift %d", info
->name
,
155 vst_per_page
= (1ull << page_shift
) / info
->size
;
156 vsd_idx
= idx
/ vst_per_page
;
158 /* Load the VSD we are looking for, if not already done */
160 vsd_addr
= vsd_addr
+ vsd_idx
* XIVE_VSD_SIZE
;
161 if (ldq_be_dma(&address_space_memory
, vsd_addr
, &vsd
,
162 MEMTXATTRS_UNSPECIFIED
)) {
163 xive_error(xive
, "VST: failed to access %s entry %x @0x%"
164 PRIx64
, info
->name
, vsd_idx
, vsd_addr
);
168 if (!(vsd
& VSD_ADDRESS_MASK
)) {
170 xive_error(xive
, "VST: invalid %s entry %x !?", info
->name
, idx
);
176 * Check that the pages have a consistent size across the
179 if (page_shift
!= GETFIELD(VSD_TSIZE
, vsd
) + 12) {
180 xive_error(xive
, "VST: %s entry %x indirect page size differ !?",
186 return pnv_xive_vst_addr_direct(xive
, type
, vsd
, (idx
% vst_per_page
));
190 * This is a simplified model of operation forwarding on a remote IC.
192 * A PC MMIO address is built to identify the NVT structure. The load
193 * on the remote IC will return the address of the structure in RAM,
194 * which will then be used by pnv_xive_vst_write/read to perform the
197 static uint64_t pnv_xive_vst_addr_remote(PnvXive
*xive
, uint32_t type
,
198 uint64_t vsd
, uint8_t blk
,
201 const XiveVstInfo
*info
= &vst_infos
[type
];
202 uint64_t remote_addr
= vsd
& VSD_ADDRESS_MASK
;
206 if (type
!= VST_TSEL_VPDT
) {
207 xive_error(xive
, "VST: invalid access on remote VST %s %x/%x !?",
208 info
->name
, blk
, idx
);
212 remote_addr
|= ((uint64_t)idx
) << xive
->pc_shift
;
214 vst_addr
= address_space_ldq_be(&address_space_memory
, remote_addr
,
215 MEMTXATTRS_UNSPECIFIED
, &result
);
216 if (result
!= MEMTX_OK
) {
217 xive_error(xive
, "VST: read failed at @0x%" HWADDR_PRIx
218 " for NVT %x/%x\n", remote_addr
, blk
, idx
);
225 static uint64_t pnv_xive_vst_addr(PnvXive
*xive
, uint32_t type
, uint8_t blk
,
228 const XiveVstInfo
*info
= &vst_infos
[type
];
231 if (blk
>= info
->max_blocks
) {
232 xive_error(xive
, "VST: invalid block id %d for VST %s %d !?",
233 blk
, info
->name
, idx
);
237 vsd
= xive
->vsds
[type
][blk
];
239 /* Remote VST access */
240 if (GETFIELD(VSD_MODE
, vsd
) == VSD_MODE_FORWARD
) {
241 return pnv_xive_vst_addr_remote(xive
, type
, vsd
, blk
, idx
);
244 if (VSD_INDIRECT
& vsd
) {
245 return pnv_xive_vst_addr_indirect(xive
, type
, vsd
, idx
);
248 return pnv_xive_vst_addr_direct(xive
, type
, vsd
, idx
);
251 static int pnv_xive_vst_read(PnvXive
*xive
, uint32_t type
, uint8_t blk
,
252 uint32_t idx
, void *data
)
254 const XiveVstInfo
*info
= &vst_infos
[type
];
255 uint64_t addr
= pnv_xive_vst_addr(xive
, type
, blk
, idx
);
262 result
= address_space_read(&address_space_memory
, addr
,
263 MEMTXATTRS_UNSPECIFIED
, data
,
265 if (result
!= MEMTX_OK
) {
266 xive_error(xive
, "VST: read failed at @0x%" HWADDR_PRIx
267 " for VST %s %x/%x\n", addr
, info
->name
, blk
, idx
);
273 #define XIVE_VST_WORD_ALL -1
275 static int pnv_xive_vst_write(PnvXive
*xive
, uint32_t type
, uint8_t blk
,
276 uint32_t idx
, void *data
, uint32_t word_number
)
278 const XiveVstInfo
*info
= &vst_infos
[type
];
279 uint64_t addr
= pnv_xive_vst_addr(xive
, type
, blk
, idx
);
286 if (word_number
== XIVE_VST_WORD_ALL
) {
287 result
= address_space_write(&address_space_memory
, addr
,
288 MEMTXATTRS_UNSPECIFIED
, data
,
291 result
= address_space_write(&address_space_memory
,
292 addr
+ word_number
* 4,
293 MEMTXATTRS_UNSPECIFIED
,
294 data
+ word_number
* 4, 4);
297 if (result
!= MEMTX_OK
) {
298 xive_error(xive
, "VST: write failed at @0x%" HWADDR_PRIx
299 "for VST %s %x/%x\n", addr
, info
->name
, blk
, idx
);
305 static int pnv_xive_get_end(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
308 PnvXive
*xive
= PNV_XIVE(xrtr
);
310 if (pnv_xive_block_id(xive
) != blk
) {
311 xive_error(xive
, "VST: END %x/%x is remote !?", blk
, idx
);
315 return pnv_xive_vst_read(PNV_XIVE(xrtr
), VST_TSEL_EQDT
, blk
, idx
, end
);
318 static int pnv_xive_write_end(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
319 XiveEND
*end
, uint8_t word_number
)
321 PnvXive
*xive
= PNV_XIVE(xrtr
);
323 if (pnv_xive_block_id(xive
) != blk
) {
324 xive_error(xive
, "VST: END %x/%x is remote !?", blk
, idx
);
328 return pnv_xive_vst_write(PNV_XIVE(xrtr
), VST_TSEL_EQDT
, blk
, idx
, end
,
332 static int pnv_xive_end_update(PnvXive
*xive
)
334 uint8_t blk
= GETFIELD(VC_EQC_CWATCH_BLOCKID
,
335 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
336 uint32_t idx
= GETFIELD(VC_EQC_CWATCH_OFFSET
,
337 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
339 uint64_t eqc_watch
[4];
341 for (i
= 0; i
< ARRAY_SIZE(eqc_watch
); i
++) {
342 eqc_watch
[i
] = cpu_to_be64(xive
->regs
[(VC_EQC_CWATCH_DAT0
>> 3) + i
]);
345 return pnv_xive_vst_write(xive
, VST_TSEL_EQDT
, blk
, idx
, eqc_watch
,
349 static void pnv_xive_end_cache_load(PnvXive
*xive
)
351 uint8_t blk
= GETFIELD(VC_EQC_CWATCH_BLOCKID
,
352 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
353 uint32_t idx
= GETFIELD(VC_EQC_CWATCH_OFFSET
,
354 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
355 uint64_t eqc_watch
[4] = { 0 };
358 if (pnv_xive_vst_read(xive
, VST_TSEL_EQDT
, blk
, idx
, eqc_watch
)) {
359 xive_error(xive
, "VST: no END entry %x/%x !?", blk
, idx
);
362 for (i
= 0; i
< ARRAY_SIZE(eqc_watch
); i
++) {
363 xive
->regs
[(VC_EQC_CWATCH_DAT0
>> 3) + i
] = be64_to_cpu(eqc_watch
[i
]);
367 static int pnv_xive_get_nvt(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
370 return pnv_xive_vst_read(PNV_XIVE(xrtr
), VST_TSEL_VPDT
, blk
, idx
, nvt
);
373 static int pnv_xive_write_nvt(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
374 XiveNVT
*nvt
, uint8_t word_number
)
376 return pnv_xive_vst_write(PNV_XIVE(xrtr
), VST_TSEL_VPDT
, blk
, idx
, nvt
,
380 static int pnv_xive_nvt_update(PnvXive
*xive
)
382 uint8_t blk
= GETFIELD(PC_VPC_CWATCH_BLOCKID
,
383 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
384 uint32_t idx
= GETFIELD(PC_VPC_CWATCH_OFFSET
,
385 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
387 uint64_t vpc_watch
[8];
389 for (i
= 0; i
< ARRAY_SIZE(vpc_watch
); i
++) {
390 vpc_watch
[i
] = cpu_to_be64(xive
->regs
[(PC_VPC_CWATCH_DAT0
>> 3) + i
]);
393 return pnv_xive_vst_write(xive
, VST_TSEL_VPDT
, blk
, idx
, vpc_watch
,
397 static void pnv_xive_nvt_cache_load(PnvXive
*xive
)
399 uint8_t blk
= GETFIELD(PC_VPC_CWATCH_BLOCKID
,
400 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
401 uint32_t idx
= GETFIELD(PC_VPC_CWATCH_OFFSET
,
402 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
403 uint64_t vpc_watch
[8] = { 0 };
406 if (pnv_xive_vst_read(xive
, VST_TSEL_VPDT
, blk
, idx
, vpc_watch
)) {
407 xive_error(xive
, "VST: no NVT entry %x/%x !?", blk
, idx
);
410 for (i
= 0; i
< ARRAY_SIZE(vpc_watch
); i
++) {
411 xive
->regs
[(PC_VPC_CWATCH_DAT0
>> 3) + i
] = be64_to_cpu(vpc_watch
[i
]);
415 static int pnv_xive_get_eas(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
418 PnvXive
*xive
= PNV_XIVE(xrtr
);
421 * EAT lookups should be local to the IC
423 if (pnv_xive_block_id(xive
) != blk
) {
424 xive_error(xive
, "VST: EAS %x is remote !?", XIVE_EAS(blk
, idx
));
428 return pnv_xive_vst_read(xive
, VST_TSEL_IVT
, blk
, idx
, eas
);
431 static int pnv_xive_get_pq(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
434 PnvXive
*xive
= PNV_XIVE(xrtr
);
436 if (pnv_xive_block_id(xive
) != blk
) {
437 xive_error(xive
, "VST: EAS %x is remote !?", XIVE_EAS(blk
, idx
));
441 *pq
= xive_source_esb_get(&xive
->ipi_source
, idx
);
445 static int pnv_xive_set_pq(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
448 PnvXive
*xive
= PNV_XIVE(xrtr
);
450 if (pnv_xive_block_id(xive
) != blk
) {
451 xive_error(xive
, "VST: EAS %x is remote !?", XIVE_EAS(blk
, idx
));
455 *pq
= xive_source_esb_set(&xive
->ipi_source
, idx
, *pq
);
460 * One bit per thread id. The first register PC_THREAD_EN_REG0 covers
461 * the first cores 0-15 (normal) of the chip or 0-7 (fused). The
462 * second register covers cores 16-23 (normal) or 8-11 (fused).
464 static bool pnv_xive_is_cpu_enabled(PnvXive
*xive
, PowerPCCPU
*cpu
)
466 int pir
= ppc_cpu_pir(cpu
);
467 uint32_t fc
= PNV9_PIR2FUSEDCORE(pir
);
468 uint64_t reg
= fc
< 8 ? PC_THREAD_EN_REG0
: PC_THREAD_EN_REG1
;
469 uint32_t bit
= pir
& 0x3f;
471 return xive
->regs
[reg
>> 3] & PPC_BIT(bit
);
474 static int pnv_xive_match_nvt(XivePresenter
*xptr
, uint8_t format
,
475 uint8_t nvt_blk
, uint32_t nvt_idx
,
476 bool cam_ignore
, uint8_t priority
,
477 uint32_t logic_serv
, XiveTCTXMatch
*match
)
479 PnvXive
*xive
= PNV_XIVE(xptr
);
480 PnvChip
*chip
= xive
->chip
;
484 for (i
= 0; i
< chip
->nr_cores
; i
++) {
485 PnvCore
*pc
= chip
->cores
[i
];
486 CPUCore
*cc
= CPU_CORE(pc
);
488 for (j
= 0; j
< cc
->nr_threads
; j
++) {
489 PowerPCCPU
*cpu
= pc
->threads
[j
];
493 if (!pnv_xive_is_cpu_enabled(xive
, cpu
)) {
497 tctx
= XIVE_TCTX(pnv_cpu_state(cpu
)->intc
);
500 * Check the thread context CAM lines and record matches.
502 ring
= xive_presenter_tctx_match(xptr
, tctx
, format
, nvt_blk
,
503 nvt_idx
, cam_ignore
, logic_serv
);
505 * Save the context and follow on to catch duplicates, that we
510 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: already found a "
511 "thread context NVT %x/%x\n",
526 static uint32_t pnv_xive_presenter_get_config(XivePresenter
*xptr
)
530 /* TIMA GEN1 is all P9 knows */
531 cfg
|= XIVE_PRESENTER_GEN1_TIMA_OS
;
536 static uint8_t pnv_xive_get_block_id(XiveRouter
*xrtr
)
538 return pnv_xive_block_id(PNV_XIVE(xrtr
));
542 * The TIMA MMIO space is shared among the chips and to identify the
543 * chip from which the access is being done, we extract the chip id
546 static PnvXive
*pnv_xive_tm_get_xive(PowerPCCPU
*cpu
)
548 int pir
= ppc_cpu_pir(cpu
);
549 XivePresenter
*xptr
= XIVE_TCTX(pnv_cpu_state(cpu
)->intc
)->xptr
;
550 PnvXive
*xive
= PNV_XIVE(xptr
);
552 if (!pnv_xive_is_cpu_enabled(xive
, cpu
)) {
553 xive_error(xive
, "IC: CPU %x is not enabled", pir
);
559 * The internal sources (IPIs) of the interrupt controller have no
560 * knowledge of the XIVE chip on which they reside. Encode the block
561 * id in the source interrupt number before forwarding the source
562 * event notification to the Router. This is required on a multichip
565 static void pnv_xive_notify(XiveNotifier
*xn
, uint32_t srcno
, bool pq_checked
)
567 PnvXive
*xive
= PNV_XIVE(xn
);
568 uint8_t blk
= pnv_xive_block_id(xive
);
570 xive_router_notify(xn
, XIVE_EAS(blk
, srcno
), pq_checked
);
577 static uint64_t pnv_xive_vc_size(PnvXive
*xive
)
579 return (~xive
->regs
[CQ_VC_BARM
>> 3] + 1) & CQ_VC_BARM_MASK
;
582 static uint64_t pnv_xive_edt_shift(PnvXive
*xive
)
584 return ctz64(pnv_xive_vc_size(xive
) / XIVE_TABLE_EDT_MAX
);
587 static uint64_t pnv_xive_pc_size(PnvXive
*xive
)
589 return (~xive
->regs
[CQ_PC_BARM
>> 3] + 1) & CQ_PC_BARM_MASK
;
592 static uint32_t pnv_xive_nr_ipis(PnvXive
*xive
, uint8_t blk
)
594 uint64_t vsd
= xive
->vsds
[VST_TSEL_SBE
][blk
];
595 uint64_t vst_tsize
= 1ull << (GETFIELD(VSD_TSIZE
, vsd
) + 12);
597 return VSD_INDIRECT
& vsd
? 0 : vst_tsize
* SBE_PER_BYTE
;
601 * Compute the number of entries per indirect subpage.
603 static uint64_t pnv_xive_vst_per_subpage(PnvXive
*xive
, uint32_t type
)
605 uint8_t blk
= pnv_xive_block_id(xive
);
606 uint64_t vsd
= xive
->vsds
[type
][blk
];
607 const XiveVstInfo
*info
= &vst_infos
[type
];
611 /* For direct tables, fake a valid value */
612 if (!(VSD_INDIRECT
& vsd
)) {
616 /* Get the page size of the indirect table. */
617 vsd_addr
= vsd
& VSD_ADDRESS_MASK
;
618 if (ldq_be_dma(&address_space_memory
, vsd_addr
, &vsd
,
619 MEMTXATTRS_UNSPECIFIED
)) {
620 xive_error(xive
, "VST: failed to access %s entry @0x%" PRIx64
,
621 info
->name
, vsd_addr
);
625 if (!(vsd
& VSD_ADDRESS_MASK
)) {
627 xive_error(xive
, "VST: invalid %s entry %x !?", info
->name
, idx
);
632 page_shift
= GETFIELD(VSD_TSIZE
, vsd
) + 12;
634 if (!pnv_xive_vst_page_size_allowed(page_shift
)) {
635 xive_error(xive
, "VST: invalid %s page shift %d", info
->name
,
640 return (1ull << page_shift
) / info
->size
;
646 * The Virtualization Controller MMIO region containing the IPI ESB
647 * pages and END ESB pages is sub-divided into "sets" which map
648 * portions of the VC region to the different ESB pages. It is
649 * configured at runtime through the EDT "Domain Table" to let the
650 * firmware decide how to split the VC address space between IPI ESB
651 * pages and END ESB pages.
655 * Computes the overall size of the IPI or the END ESB pages
657 static uint64_t pnv_xive_edt_size(PnvXive
*xive
, uint64_t type
)
659 uint64_t edt_size
= 1ull << pnv_xive_edt_shift(xive
);
663 for (i
= 0; i
< XIVE_TABLE_EDT_MAX
; i
++) {
664 uint64_t edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[i
]);
666 if (edt_type
== type
) {
675 * Maps an offset of the VC region in the IPI or END region using the
676 * layout defined by the EDT "Domaine Table"
678 static uint64_t pnv_xive_edt_offset(PnvXive
*xive
, uint64_t vc_offset
,
682 uint64_t edt_size
= 1ull << pnv_xive_edt_shift(xive
);
683 uint64_t edt_offset
= vc_offset
;
685 for (i
= 0; i
< XIVE_TABLE_EDT_MAX
&& (i
* edt_size
) < vc_offset
; i
++) {
686 uint64_t edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[i
]);
688 if (edt_type
!= type
) {
689 edt_offset
-= edt_size
;
696 static void pnv_xive_edt_resize(PnvXive
*xive
)
698 uint64_t ipi_edt_size
= pnv_xive_edt_size(xive
, CQ_TDR_EDT_IPI
);
699 uint64_t end_edt_size
= pnv_xive_edt_size(xive
, CQ_TDR_EDT_EQ
);
701 memory_region_set_size(&xive
->ipi_edt_mmio
, ipi_edt_size
);
702 memory_region_add_subregion(&xive
->ipi_mmio
, 0, &xive
->ipi_edt_mmio
);
704 memory_region_set_size(&xive
->end_edt_mmio
, end_edt_size
);
705 memory_region_add_subregion(&xive
->end_mmio
, 0, &xive
->end_edt_mmio
);
709 * XIVE Table configuration. Only EDT is supported.
711 static int pnv_xive_table_set_data(PnvXive
*xive
, uint64_t val
)
713 uint64_t tsel
= xive
->regs
[CQ_TAR
>> 3] & CQ_TAR_TSEL
;
714 uint8_t tsel_index
= GETFIELD(CQ_TAR_TSEL_INDEX
, xive
->regs
[CQ_TAR
>> 3]);
715 uint64_t *xive_table
;
719 case CQ_TAR_TSEL_BLK
:
720 max_index
= ARRAY_SIZE(xive
->blk
);
721 xive_table
= xive
->blk
;
723 case CQ_TAR_TSEL_MIG
:
724 max_index
= ARRAY_SIZE(xive
->mig
);
725 xive_table
= xive
->mig
;
727 case CQ_TAR_TSEL_EDT
:
728 max_index
= ARRAY_SIZE(xive
->edt
);
729 xive_table
= xive
->edt
;
731 case CQ_TAR_TSEL_VDT
:
732 max_index
= ARRAY_SIZE(xive
->vdt
);
733 xive_table
= xive
->vdt
;
736 xive_error(xive
, "IC: invalid table %d", (int) tsel
);
740 if (tsel_index
>= max_index
) {
741 xive_error(xive
, "IC: invalid index %d", (int) tsel_index
);
745 xive_table
[tsel_index
] = val
;
747 if (xive
->regs
[CQ_TAR
>> 3] & CQ_TAR_TBL_AUTOINC
) {
748 xive
->regs
[CQ_TAR
>> 3] =
749 SETFIELD(CQ_TAR_TSEL_INDEX
, xive
->regs
[CQ_TAR
>> 3], ++tsel_index
);
753 * EDT configuration is complete. Resize the MMIO windows exposing
754 * the IPI and the END ESBs in the VC region.
756 if (tsel
== CQ_TAR_TSEL_EDT
&& tsel_index
== ARRAY_SIZE(xive
->edt
)) {
757 pnv_xive_edt_resize(xive
);
764 * Virtual Structure Tables (VST) configuration
766 static void pnv_xive_vst_set_exclusive(PnvXive
*xive
, uint8_t type
,
767 uint8_t blk
, uint64_t vsd
)
769 XiveENDSource
*end_xsrc
= &xive
->end_source
;
770 XiveSource
*xsrc
= &xive
->ipi_source
;
771 const XiveVstInfo
*info
= &vst_infos
[type
];
772 uint32_t page_shift
= GETFIELD(VSD_TSIZE
, vsd
) + 12;
773 uint64_t vst_tsize
= 1ull << page_shift
;
774 uint64_t vst_addr
= vsd
& VSD_ADDRESS_MASK
;
778 if (VSD_INDIRECT
& vsd
) {
779 if (!(xive
->regs
[VC_GLOBAL_CONFIG
>> 3] & VC_GCONF_INDIRECT
)) {
780 xive_error(xive
, "VST: %s indirect tables are not enabled",
785 if (!pnv_xive_vst_page_size_allowed(page_shift
)) {
786 xive_error(xive
, "VST: invalid %s page shift %d", info
->name
,
792 if (!QEMU_IS_ALIGNED(vst_addr
, 1ull << page_shift
)) {
793 xive_error(xive
, "VST: %s table address 0x%"PRIx64
" is not aligned with"
794 " page shift %d", info
->name
, vst_addr
, page_shift
);
798 /* Record the table configuration (in SRAM on HW) */
799 xive
->vsds
[type
][blk
] = vsd
;
801 /* Now tune the models with the configuration provided by the FW */
804 case VST_TSEL_IVT
: /* Nothing to be done */
809 * Backing store pages for the END.
811 * If the table is direct, we can compute the number of PQ
812 * entries provisioned by FW (such as skiboot) and resize the
813 * END ESB window accordingly.
815 if (!(VSD_INDIRECT
& vsd
)) {
816 memory_region_set_size(&end_xsrc
->esb_mmio
, (vst_tsize
/ info
->size
)
817 * (1ull << xsrc
->esb_shift
));
819 memory_region_add_subregion(&xive
->end_edt_mmio
, 0,
820 &end_xsrc
->esb_mmio
);
825 * Backing store pages for the source PQ bits. The model does
826 * not use these PQ bits backed in RAM because the XiveSource
829 * If the table is direct, we can compute the number of PQ
830 * entries provisioned by FW (such as skiboot) and resize the
831 * ESB window accordingly.
833 if (!(VSD_INDIRECT
& vsd
)) {
834 memory_region_set_size(&xsrc
->esb_mmio
, vst_tsize
* SBE_PER_BYTE
835 * (1ull << xsrc
->esb_shift
));
837 memory_region_add_subregion(&xive
->ipi_edt_mmio
, 0, &xsrc
->esb_mmio
);
840 case VST_TSEL_VPDT
: /* Not modeled */
841 case VST_TSEL_IRQ
: /* Not modeled */
843 * These tables contains the backing store pages for the
844 * interrupt fifos of the VC sub-engine in case of overflow.
849 g_assert_not_reached();
854 * Both PC and VC sub-engines are configured as each use the Virtual
855 * Structure Tables : SBE, EAS, END and NVT.
857 static void pnv_xive_vst_set_data(PnvXive
*xive
, uint64_t vsd
, bool pc_engine
)
859 uint8_t mode
= GETFIELD(VSD_MODE
, vsd
);
860 uint8_t type
= GETFIELD(VST_TABLE_SELECT
,
861 xive
->regs
[VC_VSD_TABLE_ADDR
>> 3]);
862 uint8_t blk
= GETFIELD(VST_TABLE_BLOCK
,
863 xive
->regs
[VC_VSD_TABLE_ADDR
>> 3]);
864 uint64_t vst_addr
= vsd
& VSD_ADDRESS_MASK
;
866 if (type
> VST_TSEL_IRQ
) {
867 xive_error(xive
, "VST: invalid table type %d", type
);
871 if (blk
>= vst_infos
[type
].max_blocks
) {
872 xive_error(xive
, "VST: invalid block id %d for"
873 " %s table", blk
, vst_infos
[type
].name
);
878 * Only take the VC sub-engine configuration into account because
879 * the XiveRouter model combines both VC and PC sub-engines
886 xive_error(xive
, "VST: invalid %s table address", vst_infos
[type
].name
);
891 case VSD_MODE_FORWARD
:
892 xive
->vsds
[type
][blk
] = vsd
;
895 case VSD_MODE_EXCLUSIVE
:
896 pnv_xive_vst_set_exclusive(xive
, type
, blk
, vsd
);
900 xive_error(xive
, "VST: unsupported table mode %d", mode
);
906 * Interrupt controller MMIO region. The layout is compatible between
909 * Page 0 sub-engine BARs
910 * 0x000 - 0x3FF IC registers
911 * 0x400 - 0x7FF PC registers
912 * 0x800 - 0xFFF VC registers
914 * Page 1 Notify page (writes only)
915 * 0x000 - 0x7FF HW interrupt triggers (PSI, PHB)
916 * 0x800 - 0xFFF forwards and syncs
918 * Page 2 LSI Trigger page (writes only) (not modeled)
919 * Page 3 LSI SB EOI page (reads only) (not modeled)
921 * Page 4-7 indirect TIMA
925 * IC - registers MMIO
927 static void pnv_xive_ic_reg_write(void *opaque
, hwaddr offset
,
928 uint64_t val
, unsigned size
)
930 PnvXive
*xive
= PNV_XIVE(opaque
);
931 MemoryRegion
*sysmem
= get_system_memory();
932 uint32_t reg
= offset
>> 3;
933 bool is_chip0
= xive
->chip
->chip_id
== 0;
938 * XIVE CQ (PowerBus bridge) settings
940 case CQ_MSGSND
: /* msgsnd for doorbells */
941 case CQ_FIRMASK_OR
: /* FIR error reporting */
944 if (val
& CQ_PBI_PC_64K
) {
947 if (val
& CQ_PBI_VC_64K
) {
951 case CQ_CFG_PB_GEN
: /* PowerBus General Configuration */
953 * TODO: CQ_INT_ADDR_OPT for 1-block-per-chip mode
958 * XIVE Virtualization Controller settings
960 case VC_GLOBAL_CONFIG
:
964 * XIVE Presenter Controller settings
966 case PC_GLOBAL_CONFIG
:
968 * PC_GCONF_CHIPID_OVR
969 * Overrides Int command Chip ID with the Chip ID field (DEBUG)
974 * TODO: block group support
980 * enable block tracking and exchange of block ownership
981 * information between Interrupt controllers
988 case VC_SBC_CONFIG
: /* Store EOI configuration */
990 * Configure store EOI if required by firmware (skiboot has removed
991 * support recently though)
993 if (val
& (VC_SBC_CONF_CPLX_CIST
| VC_SBC_CONF_CIST_BOTH
)) {
994 xive
->ipi_source
.esb_flags
|= XIVE_SRC_STORE_EOI
;
998 case VC_EQC_CONFIG
: /* TODO: silent escalation */
999 case VC_AIB_TX_ORDER_TAG2
: /* relax ordering */
1003 * XIVE BAR settings (XSCOM only)
1006 /* bit4: resets all BAR registers */
1009 case CQ_IC_BAR
: /* IC BAR. 8 pages */
1010 xive
->ic_shift
= val
& CQ_IC_BAR_64K
? 16 : 12;
1011 if (!(val
& CQ_IC_BAR_VALID
)) {
1013 if (xive
->regs
[reg
] & CQ_IC_BAR_VALID
) {
1014 memory_region_del_subregion(&xive
->ic_mmio
,
1015 &xive
->ic_reg_mmio
);
1016 memory_region_del_subregion(&xive
->ic_mmio
,
1017 &xive
->ic_notify_mmio
);
1018 memory_region_del_subregion(&xive
->ic_mmio
,
1019 &xive
->ic_lsi_mmio
);
1020 memory_region_del_subregion(&xive
->ic_mmio
,
1021 &xive
->tm_indirect_mmio
);
1023 memory_region_del_subregion(sysmem
, &xive
->ic_mmio
);
1026 xive
->ic_base
= val
& ~(CQ_IC_BAR_VALID
| CQ_IC_BAR_64K
);
1027 if (!(xive
->regs
[reg
] & CQ_IC_BAR_VALID
)) {
1028 memory_region_add_subregion(sysmem
, xive
->ic_base
,
1031 memory_region_add_subregion(&xive
->ic_mmio
, 0,
1032 &xive
->ic_reg_mmio
);
1033 memory_region_add_subregion(&xive
->ic_mmio
,
1034 1ul << xive
->ic_shift
,
1035 &xive
->ic_notify_mmio
);
1036 memory_region_add_subregion(&xive
->ic_mmio
,
1037 2ul << xive
->ic_shift
,
1038 &xive
->ic_lsi_mmio
);
1039 memory_region_add_subregion(&xive
->ic_mmio
,
1040 4ull << xive
->ic_shift
,
1041 &xive
->tm_indirect_mmio
);
1046 case CQ_TM1_BAR
: /* TM BAR. 4 pages. Map only once */
1047 case CQ_TM2_BAR
: /* second TM BAR. for hotplug. Not modeled */
1048 xive
->tm_shift
= val
& CQ_TM_BAR_64K
? 16 : 12;
1049 if (!(val
& CQ_TM_BAR_VALID
)) {
1051 if (xive
->regs
[reg
] & CQ_TM_BAR_VALID
&& is_chip0
) {
1052 memory_region_del_subregion(sysmem
, &xive
->tm_mmio
);
1055 xive
->tm_base
= val
& ~(CQ_TM_BAR_VALID
| CQ_TM_BAR_64K
);
1056 if (!(xive
->regs
[reg
] & CQ_TM_BAR_VALID
) && is_chip0
) {
1057 memory_region_add_subregion(sysmem
, xive
->tm_base
,
1064 xive
->regs
[reg
] = val
;
1065 memory_region_set_size(&xive
->pc_mmio
, pnv_xive_pc_size(xive
));
1067 case CQ_PC_BAR
: /* From 32M to 512G */
1068 if (!(val
& CQ_PC_BAR_VALID
)) {
1070 if (xive
->regs
[reg
] & CQ_PC_BAR_VALID
) {
1071 memory_region_del_subregion(sysmem
, &xive
->pc_mmio
);
1074 xive
->pc_base
= val
& ~(CQ_PC_BAR_VALID
);
1075 if (!(xive
->regs
[reg
] & CQ_PC_BAR_VALID
)) {
1076 memory_region_add_subregion(sysmem
, xive
->pc_base
,
1083 xive
->regs
[reg
] = val
;
1084 memory_region_set_size(&xive
->vc_mmio
, pnv_xive_vc_size(xive
));
1086 case CQ_VC_BAR
: /* From 64M to 4TB */
1087 if (!(val
& CQ_VC_BAR_VALID
)) {
1089 if (xive
->regs
[reg
] & CQ_VC_BAR_VALID
) {
1090 memory_region_del_subregion(sysmem
, &xive
->vc_mmio
);
1093 xive
->vc_base
= val
& ~(CQ_VC_BAR_VALID
);
1094 if (!(xive
->regs
[reg
] & CQ_VC_BAR_VALID
)) {
1095 memory_region_add_subregion(sysmem
, xive
->vc_base
,
1102 * XIVE Table settings.
1104 case CQ_TAR
: /* Table Address */
1106 case CQ_TDR
: /* Table Data */
1107 pnv_xive_table_set_data(xive
, val
);
1111 * XIVE VC & PC Virtual Structure Table settings
1113 case VC_VSD_TABLE_ADDR
:
1114 case PC_VSD_TABLE_ADDR
: /* Virtual table selector */
1116 case VC_VSD_TABLE_DATA
: /* Virtual table setting */
1117 case PC_VSD_TABLE_DATA
:
1118 pnv_xive_vst_set_data(xive
, val
, offset
== PC_VSD_TABLE_DATA
);
1122 * Interrupt fifo overflow in memory backing store (Not modeled)
1124 case VC_IRQ_CONFIG_IPI
:
1125 case VC_IRQ_CONFIG_HW
:
1126 case VC_IRQ_CONFIG_CASCADE1
:
1127 case VC_IRQ_CONFIG_CASCADE2
:
1128 case VC_IRQ_CONFIG_REDIST
:
1129 case VC_IRQ_CONFIG_IPI_CASC
:
1133 * XIVE hardware thread enablement
1135 case PC_THREAD_EN_REG0
: /* Physical Thread Enable */
1136 case PC_THREAD_EN_REG1
: /* Physical Thread Enable (fused core) */
1139 case PC_THREAD_EN_REG0_SET
:
1140 xive
->regs
[PC_THREAD_EN_REG0
>> 3] |= val
;
1142 case PC_THREAD_EN_REG1_SET
:
1143 xive
->regs
[PC_THREAD_EN_REG1
>> 3] |= val
;
1145 case PC_THREAD_EN_REG0_CLR
:
1146 xive
->regs
[PC_THREAD_EN_REG0
>> 3] &= ~val
;
1148 case PC_THREAD_EN_REG1_CLR
:
1149 xive
->regs
[PC_THREAD_EN_REG1
>> 3] &= ~val
;
1153 * Indirect TIMA access set up. Defines the PIR of the HW thread
1156 case PC_TCTXT_INDIR0
... PC_TCTXT_INDIR3
:
1160 * XIVE PC & VC cache updates for EAS, NVT and END
1162 case VC_IVC_SCRUB_MASK
:
1163 case VC_IVC_SCRUB_TRIG
:
1166 case VC_EQC_CWATCH_SPEC
:
1167 val
&= ~VC_EQC_CWATCH_CONFLICT
; /* HW resets this bit */
1169 case VC_EQC_CWATCH_DAT1
... VC_EQC_CWATCH_DAT3
:
1171 case VC_EQC_CWATCH_DAT0
:
1172 /* writing to DATA0 triggers the cache write */
1173 xive
->regs
[reg
] = val
;
1174 pnv_xive_end_update(xive
);
1176 case VC_EQC_SCRUB_MASK
:
1177 case VC_EQC_SCRUB_TRIG
:
1179 * The scrubbing registers flush the cache in RAM and can also
1184 case PC_VPC_CWATCH_SPEC
:
1185 val
&= ~PC_VPC_CWATCH_CONFLICT
; /* HW resets this bit */
1187 case PC_VPC_CWATCH_DAT1
... PC_VPC_CWATCH_DAT7
:
1189 case PC_VPC_CWATCH_DAT0
:
1190 /* writing to DATA0 triggers the cache write */
1191 xive
->regs
[reg
] = val
;
1192 pnv_xive_nvt_update(xive
);
1194 case PC_VPC_SCRUB_MASK
:
1195 case PC_VPC_SCRUB_TRIG
:
1197 * The scrubbing registers flush the cache in RAM and can also
1204 * XIVE PC & VC cache invalidation
1208 case VC_AT_MACRO_KILL
:
1210 case PC_AT_KILL_MASK
:
1211 case VC_AT_MACRO_KILL_MASK
:
1215 xive_error(xive
, "IC: invalid write to reg=0x%"HWADDR_PRIx
, offset
);
1219 xive
->regs
[reg
] = val
;
1222 static uint64_t pnv_xive_ic_reg_read(void *opaque
, hwaddr offset
, unsigned size
)
1224 PnvXive
*xive
= PNV_XIVE(opaque
);
1226 uint32_t reg
= offset
>> 3;
1242 case PC_TCTXT_TRACK
:
1243 case PC_TCTXT_INDIR0
:
1244 case PC_TCTXT_INDIR1
:
1245 case PC_TCTXT_INDIR2
:
1246 case PC_TCTXT_INDIR3
:
1247 case PC_GLOBAL_CONFIG
:
1249 case PC_VPC_SCRUB_MASK
:
1251 case VC_GLOBAL_CONFIG
:
1252 case VC_AIB_TX_ORDER_TAG2
:
1254 case VC_IRQ_CONFIG_IPI
:
1255 case VC_IRQ_CONFIG_HW
:
1256 case VC_IRQ_CONFIG_CASCADE1
:
1257 case VC_IRQ_CONFIG_CASCADE2
:
1258 case VC_IRQ_CONFIG_REDIST
:
1259 case VC_IRQ_CONFIG_IPI_CASC
:
1261 case VC_EQC_SCRUB_MASK
:
1262 case VC_IVC_SCRUB_MASK
:
1264 case VC_AT_MACRO_KILL_MASK
:
1265 case VC_VSD_TABLE_ADDR
:
1266 case PC_VSD_TABLE_ADDR
:
1267 case VC_VSD_TABLE_DATA
:
1268 case PC_VSD_TABLE_DATA
:
1269 case PC_THREAD_EN_REG0
:
1270 case PC_THREAD_EN_REG1
:
1271 val
= xive
->regs
[reg
];
1275 * XIVE hardware thread enablement
1277 case PC_THREAD_EN_REG0_SET
:
1278 case PC_THREAD_EN_REG0_CLR
:
1279 val
= xive
->regs
[PC_THREAD_EN_REG0
>> 3];
1281 case PC_THREAD_EN_REG1_SET
:
1282 case PC_THREAD_EN_REG1_CLR
:
1283 val
= xive
->regs
[PC_THREAD_EN_REG1
>> 3];
1286 case CQ_MSGSND
: /* Identifies which cores have msgsnd enabled. */
1287 val
= 0xffffff0000000000;
1291 * XIVE PC & VC cache updates for EAS, NVT and END
1293 case VC_EQC_CWATCH_SPEC
:
1294 xive
->regs
[reg
] = ~(VC_EQC_CWATCH_FULL
| VC_EQC_CWATCH_CONFLICT
);
1295 val
= xive
->regs
[reg
];
1297 case VC_EQC_CWATCH_DAT0
:
1299 * Load DATA registers from cache with data requested by the
1302 pnv_xive_end_cache_load(xive
);
1303 val
= xive
->regs
[reg
];
1305 case VC_EQC_CWATCH_DAT1
... VC_EQC_CWATCH_DAT3
:
1306 val
= xive
->regs
[reg
];
1309 case PC_VPC_CWATCH_SPEC
:
1310 xive
->regs
[reg
] = ~(PC_VPC_CWATCH_FULL
| PC_VPC_CWATCH_CONFLICT
);
1311 val
= xive
->regs
[reg
];
1313 case PC_VPC_CWATCH_DAT0
:
1315 * Load DATA registers from cache with data requested by the
1318 pnv_xive_nvt_cache_load(xive
);
1319 val
= xive
->regs
[reg
];
1321 case PC_VPC_CWATCH_DAT1
... PC_VPC_CWATCH_DAT7
:
1322 val
= xive
->regs
[reg
];
1325 case PC_VPC_SCRUB_TRIG
:
1326 case VC_IVC_SCRUB_TRIG
:
1327 case VC_EQC_SCRUB_TRIG
:
1328 xive
->regs
[reg
] &= ~VC_SCRUB_VALID
;
1329 val
= xive
->regs
[reg
];
1333 * XIVE PC & VC cache invalidation
1336 xive
->regs
[reg
] &= ~PC_AT_KILL_VALID
;
1337 val
= xive
->regs
[reg
];
1339 case VC_AT_MACRO_KILL
:
1340 xive
->regs
[reg
] &= ~VC_KILL_VALID
;
1341 val
= xive
->regs
[reg
];
1345 * XIVE synchronisation
1348 val
= VC_EQC_SYNC_MASK
;
1352 xive_error(xive
, "IC: invalid read reg=0x%"HWADDR_PRIx
, offset
);
1358 static const MemoryRegionOps pnv_xive_ic_reg_ops
= {
1359 .read
= pnv_xive_ic_reg_read
,
1360 .write
= pnv_xive_ic_reg_write
,
1361 .endianness
= DEVICE_BIG_ENDIAN
,
1363 .min_access_size
= 8,
1364 .max_access_size
= 8,
1367 .min_access_size
= 8,
1368 .max_access_size
= 8,
1373 * IC - Notify MMIO port page (write only)
1375 #define PNV_XIVE_FORWARD_IPI 0x800 /* Forward IPI */
1376 #define PNV_XIVE_FORWARD_HW 0x880 /* Forward HW */
1377 #define PNV_XIVE_FORWARD_OS_ESC 0x900 /* Forward OS escalation */
1378 #define PNV_XIVE_FORWARD_HW_ESC 0x980 /* Forward Hyp escalation */
1379 #define PNV_XIVE_FORWARD_REDIS 0xa00 /* Forward Redistribution */
1380 #define PNV_XIVE_RESERVED5 0xa80 /* Cache line 5 PowerBUS operation */
1381 #define PNV_XIVE_RESERVED6 0xb00 /* Cache line 6 PowerBUS operation */
1382 #define PNV_XIVE_RESERVED7 0xb80 /* Cache line 7 PowerBUS operation */
1384 /* VC synchronisation */
1385 #define PNV_XIVE_SYNC_IPI 0xc00 /* Sync IPI */
1386 #define PNV_XIVE_SYNC_HW 0xc80 /* Sync HW */
1387 #define PNV_XIVE_SYNC_OS_ESC 0xd00 /* Sync OS escalation */
1388 #define PNV_XIVE_SYNC_HW_ESC 0xd80 /* Sync Hyp escalation */
1389 #define PNV_XIVE_SYNC_REDIS 0xe00 /* Sync Redistribution */
1391 /* PC synchronisation */
1392 #define PNV_XIVE_SYNC_PULL 0xe80 /* Sync pull context */
1393 #define PNV_XIVE_SYNC_PUSH 0xf00 /* Sync push context */
1394 #define PNV_XIVE_SYNC_VPC 0xf80 /* Sync remove VPC store */
1396 static void pnv_xive_end_notify(XiveRouter
*xrtr
, XiveEAS
*eas
)
1398 PnvXive
*xive
= PNV_XIVE(xrtr
);
1399 uint8_t end_blk
= xive_get_field64(EAS_END_BLOCK
, eas
->w
);
1400 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
1401 uint32_t end_data
= xive_get_field64(EAS_END_DATA
, eas
->w
);
1402 uint64_t end_vsd
= xive
->vsds
[VST_TSEL_EQDT
][end_blk
];
1404 switch (GETFIELD(VSD_MODE
, end_vsd
)) {
1405 case VSD_MODE_EXCLUSIVE
:
1406 /* Perform the END notification on the local IC. */
1407 xive_router_end_notify(xrtr
, eas
);
1410 case VSD_MODE_FORWARD
: {
1412 uint64_t notif_port
= end_vsd
& VSD_ADDRESS_MASK
;
1413 uint64_t data
= XIVE_TRIGGER_END
| XIVE_TRIGGER_PQ
|
1414 be64_to_cpu(eas
->w
);
1416 /* Forward the store on the remote IC notify page. */
1417 address_space_stq_be(&address_space_memory
, notif_port
, data
,
1418 MEMTXATTRS_UNSPECIFIED
, &result
);
1419 if (result
!= MEMTX_OK
) {
1420 xive_error(xive
, "IC: Forward notif END %x/%x [%x] failed @%"
1421 HWADDR_PRIx
, end_blk
, end_idx
, end_data
, notif_port
);
1427 case VSD_MODE_INVALID
:
1430 xive_error(xive
, "IC: Invalid END VSD for block %x", end_blk
);
1436 * The notify page can either be used to receive trigger events from
1437 * the HW controllers (PHB, PSI) or to reroute interrupts between
1438 * Interrupt controllers.
1440 static void pnv_xive_ic_hw_trigger(PnvXive
*xive
, hwaddr addr
, uint64_t val
)
1445 trace_pnv_xive_ic_hw_trigger(addr
, val
);
1447 if (val
& XIVE_TRIGGER_END
) {
1448 val
= cpu_to_be64(val
);
1449 pnv_xive_end_notify(XIVE_ROUTER(xive
), (XiveEAS
*) &val
);
1454 * Forward the source event notification directly to the Router.
1455 * The source interrupt number should already be correctly encoded
1456 * with the chip block id by the sending device (PHB, PSI).
1458 blk
= XIVE_EAS_BLOCK(val
);
1459 idx
= XIVE_EAS_INDEX(val
);
1461 xive_router_notify(XIVE_NOTIFIER(xive
), XIVE_EAS(blk
, idx
),
1462 !!(val
& XIVE_TRIGGER_PQ
));
1465 static void pnv_xive_ic_notify_write(void *opaque
, hwaddr addr
, uint64_t val
,
1468 PnvXive
*xive
= PNV_XIVE(opaque
);
1470 /* VC: HW triggers */
1472 case 0x000 ... 0x7FF:
1473 pnv_xive_ic_hw_trigger(opaque
, addr
, val
);
1476 /* VC: Forwarded IRQs */
1477 case PNV_XIVE_FORWARD_IPI
:
1478 case PNV_XIVE_FORWARD_HW
:
1479 case PNV_XIVE_FORWARD_OS_ESC
:
1480 case PNV_XIVE_FORWARD_HW_ESC
:
1481 case PNV_XIVE_FORWARD_REDIS
:
1482 /* TODO: forwarded IRQs. Should be like HW triggers */
1483 xive_error(xive
, "IC: forwarded at @0x%"HWADDR_PRIx
" IRQ 0x%"PRIx64
,
1488 case PNV_XIVE_SYNC_IPI
:
1489 case PNV_XIVE_SYNC_HW
:
1490 case PNV_XIVE_SYNC_OS_ESC
:
1491 case PNV_XIVE_SYNC_HW_ESC
:
1492 case PNV_XIVE_SYNC_REDIS
:
1496 case PNV_XIVE_SYNC_PULL
:
1497 case PNV_XIVE_SYNC_PUSH
:
1498 case PNV_XIVE_SYNC_VPC
:
1502 xive_error(xive
, "IC: invalid notify write @%"HWADDR_PRIx
, addr
);
1506 static uint64_t pnv_xive_ic_notify_read(void *opaque
, hwaddr addr
,
1509 PnvXive
*xive
= PNV_XIVE(opaque
);
1511 /* loads are invalid */
1512 xive_error(xive
, "IC: invalid notify read @%"HWADDR_PRIx
, addr
);
1516 static const MemoryRegionOps pnv_xive_ic_notify_ops
= {
1517 .read
= pnv_xive_ic_notify_read
,
1518 .write
= pnv_xive_ic_notify_write
,
1519 .endianness
= DEVICE_BIG_ENDIAN
,
1521 .min_access_size
= 8,
1522 .max_access_size
= 8,
1525 .min_access_size
= 8,
1526 .max_access_size
= 8,
1531 * IC - LSI MMIO handlers (not modeled)
1534 static void pnv_xive_ic_lsi_write(void *opaque
, hwaddr addr
,
1535 uint64_t val
, unsigned size
)
1537 PnvXive
*xive
= PNV_XIVE(opaque
);
1539 xive_error(xive
, "IC: LSI invalid write @%"HWADDR_PRIx
, addr
);
1542 static uint64_t pnv_xive_ic_lsi_read(void *opaque
, hwaddr addr
, unsigned size
)
1544 PnvXive
*xive
= PNV_XIVE(opaque
);
1546 xive_error(xive
, "IC: LSI invalid read @%"HWADDR_PRIx
, addr
);
1550 static const MemoryRegionOps pnv_xive_ic_lsi_ops
= {
1551 .read
= pnv_xive_ic_lsi_read
,
1552 .write
= pnv_xive_ic_lsi_write
,
1553 .endianness
= DEVICE_BIG_ENDIAN
,
1555 .min_access_size
= 8,
1556 .max_access_size
= 8,
1559 .min_access_size
= 8,
1560 .max_access_size
= 8,
1565 * IC - Indirect TIMA MMIO handlers
1569 * When the TIMA is accessed from the indirect page, the thread id of
1570 * the target CPU is configured in the PC_TCTXT_INDIR0 register before
1571 * use. This is used for resets and for debug purpose also.
1573 static XiveTCTX
*pnv_xive_get_indirect_tctx(PnvXive
*xive
)
1575 PnvChip
*chip
= xive
->chip
;
1576 uint64_t tctxt_indir
= xive
->regs
[PC_TCTXT_INDIR0
>> 3];
1577 PowerPCCPU
*cpu
= NULL
;
1580 if (!(tctxt_indir
& PC_TCTXT_INDIR_VALID
)) {
1581 xive_error(xive
, "IC: no indirect TIMA access in progress");
1585 pir
= (chip
->chip_id
<< 8) | GETFIELD(PC_TCTXT_INDIR_THRDID
, tctxt_indir
);
1586 cpu
= pnv_chip_find_cpu(chip
, pir
);
1588 xive_error(xive
, "IC: invalid PIR %x for indirect access", pir
);
1592 /* Check that HW thread is XIVE enabled */
1593 if (!pnv_xive_is_cpu_enabled(xive
, cpu
)) {
1594 xive_error(xive
, "IC: CPU %x is not enabled", pir
);
1597 return XIVE_TCTX(pnv_cpu_state(cpu
)->intc
);
1600 static void xive_tm_indirect_write(void *opaque
, hwaddr offset
,
1601 uint64_t value
, unsigned size
)
1603 XiveTCTX
*tctx
= pnv_xive_get_indirect_tctx(PNV_XIVE(opaque
));
1605 xive_tctx_tm_write(XIVE_PRESENTER(opaque
), tctx
, offset
, value
, size
);
1608 static uint64_t xive_tm_indirect_read(void *opaque
, hwaddr offset
,
1611 XiveTCTX
*tctx
= pnv_xive_get_indirect_tctx(PNV_XIVE(opaque
));
1613 return xive_tctx_tm_read(XIVE_PRESENTER(opaque
), tctx
, offset
, size
);
1616 static const MemoryRegionOps xive_tm_indirect_ops
= {
1617 .read
= xive_tm_indirect_read
,
1618 .write
= xive_tm_indirect_write
,
1619 .endianness
= DEVICE_BIG_ENDIAN
,
1621 .min_access_size
= 1,
1622 .max_access_size
= 8,
1625 .min_access_size
= 1,
1626 .max_access_size
= 8,
1630 static void pnv_xive_tm_write(void *opaque
, hwaddr offset
,
1631 uint64_t value
, unsigned size
)
1633 PowerPCCPU
*cpu
= POWERPC_CPU(current_cpu
);
1634 PnvXive
*xive
= pnv_xive_tm_get_xive(cpu
);
1635 XiveTCTX
*tctx
= XIVE_TCTX(pnv_cpu_state(cpu
)->intc
);
1637 xive_tctx_tm_write(XIVE_PRESENTER(xive
), tctx
, offset
, value
, size
);
1640 static uint64_t pnv_xive_tm_read(void *opaque
, hwaddr offset
, unsigned size
)
1642 PowerPCCPU
*cpu
= POWERPC_CPU(current_cpu
);
1643 PnvXive
*xive
= pnv_xive_tm_get_xive(cpu
);
1644 XiveTCTX
*tctx
= XIVE_TCTX(pnv_cpu_state(cpu
)->intc
);
1646 return xive_tctx_tm_read(XIVE_PRESENTER(xive
), tctx
, offset
, size
);
1649 const MemoryRegionOps pnv_xive_tm_ops
= {
1650 .read
= pnv_xive_tm_read
,
1651 .write
= pnv_xive_tm_write
,
1652 .endianness
= DEVICE_BIG_ENDIAN
,
1654 .min_access_size
= 1,
1655 .max_access_size
= 8,
1658 .min_access_size
= 1,
1659 .max_access_size
= 8,
1664 * Interrupt controller XSCOM region.
1666 static uint64_t pnv_xive_xscom_read(void *opaque
, hwaddr addr
, unsigned size
)
1668 switch (addr
>> 3) {
1669 case X_VC_EQC_CONFIG
:
1670 /* FIXME (skiboot): This is the only XSCOM load. Bizarre. */
1671 return VC_EQC_SYNC_MASK
;
1673 return pnv_xive_ic_reg_read(opaque
, addr
, size
);
1677 static void pnv_xive_xscom_write(void *opaque
, hwaddr addr
,
1678 uint64_t val
, unsigned size
)
1680 pnv_xive_ic_reg_write(opaque
, addr
, val
, size
);
1683 static const MemoryRegionOps pnv_xive_xscom_ops
= {
1684 .read
= pnv_xive_xscom_read
,
1685 .write
= pnv_xive_xscom_write
,
1686 .endianness
= DEVICE_BIG_ENDIAN
,
1688 .min_access_size
= 8,
1689 .max_access_size
= 8,
1692 .min_access_size
= 8,
1693 .max_access_size
= 8,
1698 * Virtualization Controller MMIO region containing the IPI and END ESB pages
1700 static uint64_t pnv_xive_vc_read(void *opaque
, hwaddr offset
,
1703 PnvXive
*xive
= PNV_XIVE(opaque
);
1704 uint64_t edt_index
= offset
>> pnv_xive_edt_shift(xive
);
1705 uint64_t edt_type
= 0;
1706 uint64_t edt_offset
;
1708 AddressSpace
*edt_as
= NULL
;
1711 if (edt_index
< XIVE_TABLE_EDT_MAX
) {
1712 edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[edt_index
]);
1716 case CQ_TDR_EDT_IPI
:
1717 edt_as
= &xive
->ipi_as
;
1720 edt_as
= &xive
->end_as
;
1723 xive_error(xive
, "VC: invalid EDT type for read @%"HWADDR_PRIx
, offset
);
1727 /* Remap the offset for the targeted address space */
1728 edt_offset
= pnv_xive_edt_offset(xive
, offset
, edt_type
);
1730 ret
= address_space_ldq(edt_as
, edt_offset
, MEMTXATTRS_UNSPECIFIED
,
1733 if (result
!= MEMTX_OK
) {
1734 xive_error(xive
, "VC: %s read failed at @0x%"HWADDR_PRIx
" -> @0x%"
1735 HWADDR_PRIx
, edt_type
== CQ_TDR_EDT_IPI
? "IPI" : "END",
1736 offset
, edt_offset
);
1743 static void pnv_xive_vc_write(void *opaque
, hwaddr offset
,
1744 uint64_t val
, unsigned size
)
1746 PnvXive
*xive
= PNV_XIVE(opaque
);
1747 uint64_t edt_index
= offset
>> pnv_xive_edt_shift(xive
);
1748 uint64_t edt_type
= 0;
1749 uint64_t edt_offset
;
1751 AddressSpace
*edt_as
= NULL
;
1753 if (edt_index
< XIVE_TABLE_EDT_MAX
) {
1754 edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[edt_index
]);
1758 case CQ_TDR_EDT_IPI
:
1759 edt_as
= &xive
->ipi_as
;
1762 edt_as
= &xive
->end_as
;
1765 xive_error(xive
, "VC: invalid EDT type for write @%"HWADDR_PRIx
,
1770 /* Remap the offset for the targeted address space */
1771 edt_offset
= pnv_xive_edt_offset(xive
, offset
, edt_type
);
1773 address_space_stq(edt_as
, edt_offset
, val
, MEMTXATTRS_UNSPECIFIED
, &result
);
1774 if (result
!= MEMTX_OK
) {
1775 xive_error(xive
, "VC: write failed at @0x%"HWADDR_PRIx
, edt_offset
);
1779 static const MemoryRegionOps pnv_xive_vc_ops
= {
1780 .read
= pnv_xive_vc_read
,
1781 .write
= pnv_xive_vc_write
,
1782 .endianness
= DEVICE_BIG_ENDIAN
,
1784 .min_access_size
= 8,
1785 .max_access_size
= 8,
1788 .min_access_size
= 8,
1789 .max_access_size
= 8,
1794 * Presenter Controller MMIO region. Points to the NVT sets.
1796 * HW implements all possible mem ops to the underlying NVT structure
1797 * but QEMU does not need to be so precise. The model implementation
1798 * simply returns the RAM address of the NVT structure which is then
1799 * used by pnv_xive_vst_write/read to perform the RAM operation.
1801 static uint64_t pnv_xive_pc_read(void *opaque
, hwaddr offset
, unsigned size
)
1803 PnvXive
*xive
= PNV_XIVE(opaque
);
1804 uint32_t nvt_idx
= offset
>> xive
->pc_shift
;
1805 uint8_t blk
= pnv_xive_block_id(xive
); /* TODO: VDT -> block xlate */
1807 return pnv_xive_vst_addr(xive
, VST_TSEL_VPDT
, blk
, nvt_idx
);
1810 static void pnv_xive_pc_write(void *opaque
, hwaddr addr
,
1811 uint64_t value
, unsigned size
)
1813 PnvXive
*xive
= PNV_XIVE(opaque
);
1815 xive_error(xive
, "PC: invalid write to VC @%"HWADDR_PRIx
, addr
);
1818 static const MemoryRegionOps pnv_xive_pc_ops
= {
1819 .read
= pnv_xive_pc_read
,
1820 .write
= pnv_xive_pc_write
,
1821 .endianness
= DEVICE_BIG_ENDIAN
,
1823 .min_access_size
= 8,
1824 .max_access_size
= 8,
1827 .min_access_size
= 8,
1828 .max_access_size
= 8,
1832 static void xive_nvt_pic_print_info(XiveNVT
*nvt
, uint32_t nvt_idx
,
1835 uint8_t eq_blk
= xive_get_field32(NVT_W1_EQ_BLOCK
, nvt
->w1
);
1836 uint32_t eq_idx
= xive_get_field32(NVT_W1_EQ_INDEX
, nvt
->w1
);
1838 if (!xive_nvt_is_valid(nvt
)) {
1842 g_string_append_printf(buf
, " %08x end:%02x/%04x IPB:%02x\n",
1843 nvt_idx
, eq_blk
, eq_idx
,
1844 xive_get_field32(NVT_W4_IPB
, nvt
->w4
));
1847 void pnv_xive_pic_print_info(PnvXive
*xive
, GString
*buf
)
1849 XiveRouter
*xrtr
= XIVE_ROUTER(xive
);
1850 uint8_t blk
= pnv_xive_block_id(xive
);
1851 uint8_t chip_id
= xive
->chip
->chip_id
;
1852 uint32_t srcno0
= XIVE_EAS(blk
, 0);
1853 uint32_t nr_ipis
= pnv_xive_nr_ipis(xive
, blk
);
1858 uint64_t xive_nvt_per_subpage
;
1860 g_string_append_printf(buf
, "XIVE[%x] #%d Source %08x .. %08x\n",
1861 chip_id
, blk
, srcno0
, srcno0
+ nr_ipis
- 1);
1862 xive_source_pic_print_info(&xive
->ipi_source
, srcno0
, buf
);
1864 g_string_append_printf(buf
, "XIVE[%x] #%d EAT %08x .. %08x\n",
1865 chip_id
, blk
, srcno0
, srcno0
+ nr_ipis
- 1);
1866 for (i
= 0; i
< nr_ipis
; i
++) {
1867 if (xive_router_get_eas(xrtr
, blk
, i
, &eas
)) {
1870 if (!xive_eas_is_masked(&eas
)) {
1871 xive_eas_pic_print_info(&eas
, i
, buf
);
1875 g_string_append_printf(buf
, "XIVE[%x] #%d ENDT\n", chip_id
, blk
);
1877 while (!xive_router_get_end(xrtr
, blk
, i
, &end
)) {
1878 xive_end_pic_print_info(&end
, i
++, buf
);
1881 g_string_append_printf(buf
, "XIVE[%x] #%d END Escalation EAT\n",
1884 while (!xive_router_get_end(xrtr
, blk
, i
, &end
)) {
1885 xive_end_eas_pic_print_info(&end
, i
++, buf
);
1888 g_string_append_printf(buf
, "XIVE[%x] #%d NVTT %08x .. %08x\n",
1889 chip_id
, blk
, 0, XIVE_NVT_COUNT
- 1);
1890 xive_nvt_per_subpage
= pnv_xive_vst_per_subpage(xive
, VST_TSEL_VPDT
);
1891 for (i
= 0; i
< XIVE_NVT_COUNT
; i
+= xive_nvt_per_subpage
) {
1892 while (!xive_router_get_nvt(xrtr
, blk
, i
, &nvt
)) {
1893 xive_nvt_pic_print_info(&nvt
, i
++, buf
);
1898 static void pnv_xive_reset(void *dev
)
1900 PnvXive
*xive
= PNV_XIVE(dev
);
1901 XiveSource
*xsrc
= &xive
->ipi_source
;
1902 XiveENDSource
*end_xsrc
= &xive
->end_source
;
1904 /* Default page size (Should be changed at runtime to 64k) */
1905 xive
->ic_shift
= xive
->vc_shift
= xive
->pc_shift
= 12;
1907 /* Clear subregions */
1908 if (memory_region_is_mapped(&xsrc
->esb_mmio
)) {
1909 memory_region_del_subregion(&xive
->ipi_edt_mmio
, &xsrc
->esb_mmio
);
1912 if (memory_region_is_mapped(&xive
->ipi_edt_mmio
)) {
1913 memory_region_del_subregion(&xive
->ipi_mmio
, &xive
->ipi_edt_mmio
);
1916 if (memory_region_is_mapped(&end_xsrc
->esb_mmio
)) {
1917 memory_region_del_subregion(&xive
->end_edt_mmio
, &end_xsrc
->esb_mmio
);
1920 if (memory_region_is_mapped(&xive
->end_edt_mmio
)) {
1921 memory_region_del_subregion(&xive
->end_mmio
, &xive
->end_edt_mmio
);
1925 static void pnv_xive_init(Object
*obj
)
1927 PnvXive
*xive
= PNV_XIVE(obj
);
1929 object_initialize_child(obj
, "ipi_source", &xive
->ipi_source
,
1931 object_initialize_child(obj
, "end_source", &xive
->end_source
,
1932 TYPE_XIVE_END_SOURCE
);
1936 * Maximum number of IRQs and ENDs supported by HW
1938 #define PNV_XIVE_NR_IRQS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE))
1939 #define PNV_XIVE_NR_ENDS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE))
1941 static void pnv_xive_realize(DeviceState
*dev
, Error
**errp
)
1943 PnvXive
*xive
= PNV_XIVE(dev
);
1944 PnvXiveClass
*pxc
= PNV_XIVE_GET_CLASS(dev
);
1945 XiveSource
*xsrc
= &xive
->ipi_source
;
1946 XiveENDSource
*end_xsrc
= &xive
->end_source
;
1947 Error
*local_err
= NULL
;
1949 pxc
->parent_realize(dev
, &local_err
);
1951 error_propagate(errp
, local_err
);
1958 * The XiveSource and XiveENDSource objects are realized with the
1959 * maximum allowed HW configuration. The ESB MMIO regions will be
1960 * resized dynamically when the controller is configured by the FW
1961 * to limit accesses to resources not provisioned.
1963 object_property_set_int(OBJECT(xsrc
), "nr-irqs", PNV_XIVE_NR_IRQS
,
1965 object_property_set_link(OBJECT(xsrc
), "xive", OBJECT(xive
), &error_abort
);
1966 if (!qdev_realize(DEVICE(xsrc
), NULL
, errp
)) {
1970 object_property_set_int(OBJECT(end_xsrc
), "nr-ends", PNV_XIVE_NR_ENDS
,
1972 object_property_set_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
1974 if (!qdev_realize(DEVICE(end_xsrc
), NULL
, errp
)) {
1978 /* Default page size. Generally changed at runtime to 64k */
1979 xive
->ic_shift
= xive
->vc_shift
= xive
->pc_shift
= 12;
1981 /* XSCOM region, used for initial configuration of the BARs */
1982 memory_region_init_io(&xive
->xscom_regs
, OBJECT(dev
), &pnv_xive_xscom_ops
,
1983 xive
, "xscom-xive", PNV9_XSCOM_XIVE_SIZE
<< 3);
1985 /* Interrupt controller MMIO regions */
1986 memory_region_init(&xive
->ic_mmio
, OBJECT(dev
), "xive-ic",
1989 memory_region_init_io(&xive
->ic_reg_mmio
, OBJECT(dev
), &pnv_xive_ic_reg_ops
,
1990 xive
, "xive-ic-reg", 1 << xive
->ic_shift
);
1991 memory_region_init_io(&xive
->ic_notify_mmio
, OBJECT(dev
),
1992 &pnv_xive_ic_notify_ops
,
1993 xive
, "xive-ic-notify", 1 << xive
->ic_shift
);
1994 xive
->ic_notify_mmio
.disable_reentrancy_guard
= true;
1996 /* The Pervasive LSI trigger and EOI pages (not modeled) */
1997 memory_region_init_io(&xive
->ic_lsi_mmio
, OBJECT(dev
), &pnv_xive_ic_lsi_ops
,
1998 xive
, "xive-ic-lsi", 2 << xive
->ic_shift
);
2000 /* Thread Interrupt Management Area (Indirect) */
2001 memory_region_init_io(&xive
->tm_indirect_mmio
, OBJECT(dev
),
2002 &xive_tm_indirect_ops
,
2003 xive
, "xive-tima-indirect", PNV9_XIVE_TM_SIZE
);
2005 * Overall Virtualization Controller MMIO region containing the
2006 * IPI ESB pages and END ESB pages. The layout is defined by the
2007 * EDT "Domain table" and the accesses are dispatched using
2008 * address spaces for each.
2010 memory_region_init_io(&xive
->vc_mmio
, OBJECT(xive
), &pnv_xive_vc_ops
, xive
,
2011 "xive-vc", PNV9_XIVE_VC_SIZE
);
2013 memory_region_init(&xive
->ipi_mmio
, OBJECT(xive
), "xive-vc-ipi",
2015 address_space_init(&xive
->ipi_as
, &xive
->ipi_mmio
, "xive-vc-ipi");
2016 memory_region_init(&xive
->end_mmio
, OBJECT(xive
), "xive-vc-end",
2018 address_space_init(&xive
->end_as
, &xive
->end_mmio
, "xive-vc-end");
2021 * The MMIO windows exposing the IPI ESBs and the END ESBs in the
2022 * VC region. Their size is configured by the FW in the EDT table.
2024 memory_region_init(&xive
->ipi_edt_mmio
, OBJECT(xive
), "xive-vc-ipi-edt", 0);
2025 memory_region_init(&xive
->end_edt_mmio
, OBJECT(xive
), "xive-vc-end-edt", 0);
2027 /* Presenter Controller MMIO region (not modeled) */
2028 memory_region_init_io(&xive
->pc_mmio
, OBJECT(xive
), &pnv_xive_pc_ops
, xive
,
2029 "xive-pc", PNV9_XIVE_PC_SIZE
);
2030 xive
->pc_mmio
.disable_reentrancy_guard
= true;
2032 /* Thread Interrupt Management Area (Direct) */
2033 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &pnv_xive_tm_ops
,
2034 xive
, "xive-tima", PNV9_XIVE_TM_SIZE
);
2036 qemu_register_reset(pnv_xive_reset
, dev
);
2039 static int pnv_xive_dt_xscom(PnvXScomInterface
*dev
, void *fdt
,
2042 const char compat
[] = "ibm,power9-xive-x";
2045 uint32_t lpc_pcba
= PNV9_XSCOM_XIVE_BASE
;
2047 cpu_to_be32(lpc_pcba
),
2048 cpu_to_be32(PNV9_XSCOM_XIVE_SIZE
)
2051 name
= g_strdup_printf("xive@%x", lpc_pcba
);
2052 offset
= fdt_add_subnode(fdt
, xscom_offset
, name
);
2056 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, sizeof(reg
))));
2057 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
,
2062 static Property pnv_xive_properties
[] = {
2063 DEFINE_PROP_UINT64("ic-bar", PnvXive
, ic_base
, 0),
2064 DEFINE_PROP_UINT64("vc-bar", PnvXive
, vc_base
, 0),
2065 DEFINE_PROP_UINT64("pc-bar", PnvXive
, pc_base
, 0),
2066 DEFINE_PROP_UINT64("tm-bar", PnvXive
, tm_base
, 0),
2067 /* The PnvChip id identifies the XIVE interrupt controller. */
2068 DEFINE_PROP_LINK("chip", PnvXive
, chip
, TYPE_PNV_CHIP
, PnvChip
*),
2069 DEFINE_PROP_END_OF_LIST(),
2072 static void pnv_xive_class_init(ObjectClass
*klass
, void *data
)
2074 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2075 PnvXScomInterfaceClass
*xdc
= PNV_XSCOM_INTERFACE_CLASS(klass
);
2076 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
2077 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
2078 XivePresenterClass
*xpc
= XIVE_PRESENTER_CLASS(klass
);
2079 PnvXiveClass
*pxc
= PNV_XIVE_CLASS(klass
);
2081 xdc
->dt_xscom
= pnv_xive_dt_xscom
;
2083 dc
->desc
= "PowerNV XIVE Interrupt Controller";
2084 device_class_set_parent_realize(dc
, pnv_xive_realize
, &pxc
->parent_realize
);
2085 dc
->realize
= pnv_xive_realize
;
2086 device_class_set_props(dc
, pnv_xive_properties
);
2088 xrc
->get_eas
= pnv_xive_get_eas
;
2089 xrc
->get_pq
= pnv_xive_get_pq
;
2090 xrc
->set_pq
= pnv_xive_set_pq
;
2091 xrc
->get_end
= pnv_xive_get_end
;
2092 xrc
->write_end
= pnv_xive_write_end
;
2093 xrc
->get_nvt
= pnv_xive_get_nvt
;
2094 xrc
->write_nvt
= pnv_xive_write_nvt
;
2095 xrc
->get_block_id
= pnv_xive_get_block_id
;
2096 xrc
->end_notify
= pnv_xive_end_notify
;
2098 xnc
->notify
= pnv_xive_notify
;
2099 xpc
->match_nvt
= pnv_xive_match_nvt
;
2100 xpc
->get_config
= pnv_xive_presenter_get_config
;
2103 static const TypeInfo pnv_xive_info
= {
2104 .name
= TYPE_PNV_XIVE
,
2105 .parent
= TYPE_XIVE_ROUTER
,
2106 .instance_init
= pnv_xive_init
,
2107 .instance_size
= sizeof(PnvXive
),
2108 .class_init
= pnv_xive_class_init
,
2109 .class_size
= sizeof(PnvXiveClass
),
2110 .interfaces
= (InterfaceInfo
[]) {
2111 { TYPE_PNV_XSCOM_INTERFACE
},
2116 static void pnv_xive_register_types(void)
2118 type_register_static(&pnv_xive_info
);
2121 type_init(pnv_xive_register_types
)