2 * djMEMC, macintosh memory and interrupt controller
3 * (Quadra 610/650/800 & Centris 610/650)
5 * https://mac68k.info/wiki/display/mac68k/djMEMC+Information
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "qemu/osdep.h"
12 #include "migration/vmstate.h"
13 #include "hw/misc/djmemc.h"
14 #include "hw/qdev-properties.h"
18 #define DJMEMC_INTERLEAVECONF 0x0
19 #define DJMEMC_BANK0CONF 0x4
20 #define DJMEMC_BANK1CONF 0x8
21 #define DJMEMC_BANK2CONF 0xc
22 #define DJMEMC_BANK3CONF 0x10
23 #define DJMEMC_BANK4CONF 0x14
24 #define DJMEMC_BANK5CONF 0x18
25 #define DJMEMC_BANK6CONF 0x1c
26 #define DJMEMC_BANK7CONF 0x20
27 #define DJMEMC_BANK8CONF 0x24
28 #define DJMEMC_BANK9CONF 0x28
29 #define DJMEMC_MEMTOP 0x2c
30 #define DJMEMC_CONFIG 0x30
31 #define DJMEMC_REFRESH 0x34
34 static uint64_t djmemc_read(void *opaque
, hwaddr addr
, unsigned size
)
36 DJMEMCState
*s
= opaque
;
40 case DJMEMC_INTERLEAVECONF
:
41 case DJMEMC_BANK0CONF
... DJMEMC_BANK9CONF
:
45 val
= s
->regs
[addr
>> 2];
48 qemu_log_mask(LOG_UNIMP
, "djMEMC: unimplemented read addr=0x%"PRIx64
49 " val=0x%"PRIx64
" size=%d\n",
53 trace_djmemc_read(addr
, val
, size
);
57 static void djmemc_write(void *opaque
, hwaddr addr
, uint64_t val
,
60 DJMEMCState
*s
= opaque
;
62 trace_djmemc_write(addr
, val
, size
);
65 case DJMEMC_INTERLEAVECONF
:
66 case DJMEMC_BANK0CONF
... DJMEMC_BANK9CONF
:
70 s
->regs
[addr
>> 2] = val
;
73 qemu_log_mask(LOG_UNIMP
, "djMEMC: unimplemented write addr=0x%"PRIx64
74 " val=0x%"PRIx64
" size=%d\n",
79 static const MemoryRegionOps djmemc_mmio_ops
= {
81 .write
= djmemc_write
,
86 .endianness
= DEVICE_BIG_ENDIAN
,
89 static void djmemc_init(Object
*obj
)
91 DJMEMCState
*s
= DJMEMC(obj
);
92 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
94 memory_region_init_io(&s
->mem_regs
, obj
, &djmemc_mmio_ops
, s
, "djMEMC",
96 sysbus_init_mmio(sbd
, &s
->mem_regs
);
99 static void djmemc_reset_hold(Object
*obj
, ResetType type
)
101 DJMEMCState
*s
= DJMEMC(obj
);
103 memset(s
->regs
, 0, sizeof(s
->regs
));
106 static const VMStateDescription vmstate_djmemc
= {
109 .minimum_version_id
= 1,
110 .fields
= (const VMStateField
[]) {
111 VMSTATE_UINT32_ARRAY(regs
, DJMEMCState
, DJMEMC_NUM_REGS
),
112 VMSTATE_END_OF_LIST()
116 static void djmemc_class_init(ObjectClass
*oc
, void *data
)
118 DeviceClass
*dc
= DEVICE_CLASS(oc
);
119 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
121 dc
->vmsd
= &vmstate_djmemc
;
122 rc
->phases
.hold
= djmemc_reset_hold
;
125 static const TypeInfo djmemc_info_types
[] = {
128 .parent
= TYPE_SYS_BUS_DEVICE
,
129 .instance_size
= sizeof(DJMEMCState
),
130 .instance_init
= djmemc_init
,
131 .class_init
= djmemc_class_init
,
135 DEFINE_TYPES(djmemc_info_types
)