hw/ppc/ppc405_uc.c

   1 /*
   2  * QEMU PowerPC 405 embedded processors emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "qapi/error.h"
  28 #include "qemu/log.h"
  29 #include "cpu.h"
  30 #include "hw/ppc/ppc.h"
  31 #include "hw/i2c/ppc4xx_i2c.h"
  32 #include "hw/irq.h"
  33 #include "hw/qdev-properties.h"
  34 #include "ppc405.h"
  35 #include "hw/char/serial-mm.h"
  36 #include "qemu/timer.h"
  37 #include "sysemu/reset.h"
  38 #include "sysemu/sysemu.h"
  39 #include "exec/address-spaces.h"
  40 #include "hw/intc/ppc-uic.h"
  41 #include "trace.h"
  42
  43 /*****************************************************************************/
  44 /* Shared peripherals */
  45
  46 /*****************************************************************************/
  47 /* PLB to OPB bridge */
  48 enum {
  49     POB0_BESR0 = 0x0A0,
  50     POB0_BESR1 = 0x0A2,
  51     POB0_BEAR  = 0x0A4,
  52 };
  53
  54 static uint32_t dcr_read_pob(void *opaque, int dcrn)
  55 {
  56     Ppc405PobState *pob = opaque;
  57     uint32_t ret;
  58
  59     switch (dcrn) {
  60     case POB0_BEAR:
  61         ret = pob->bear;
  62         break;
  63     case POB0_BESR0:
  64         ret = pob->besr0;
  65         break;
  66     case POB0_BESR1:
  67         ret = pob->besr1;
  68         break;
  69     default:
  70         /* Avoid gcc warning */
  71         ret = 0;
  72         break;
  73     }
  74
  75     return ret;
  76 }
  77
  78 static void dcr_write_pob(void *opaque, int dcrn, uint32_t val)
  79 {
  80     Ppc405PobState *pob = opaque;
  81
  82     switch (dcrn) {
  83     case POB0_BEAR:
  84         /* Read only */
  85         break;
  86     case POB0_BESR0:
  87         /* Write-clear */
  88         pob->besr0 &= ~val;
  89         break;
  90     case POB0_BESR1:
  91         /* Write-clear */
  92         pob->besr1 &= ~val;
  93         break;
  94     }
  95 }
  96
  97 static void ppc405_pob_reset(DeviceState *dev)
  98 {
  99     Ppc405PobState *pob = PPC405_POB(dev);
 100
 101     /* No error */
 102     pob->bear = 0x00000000;
 103     pob->besr0 = 0x0000000;
 104     pob->besr1 = 0x0000000;
 105 }
 106
 107 static void ppc405_pob_realize(DeviceState *dev, Error **errp)
 108 {
 109     Ppc405PobState *pob = PPC405_POB(dev);
 110     Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
 111
 112     ppc4xx_dcr_register(dcr, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
 113     ppc4xx_dcr_register(dcr, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
 114     ppc4xx_dcr_register(dcr, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
 115 }
 116
 117 static void ppc405_pob_class_init(ObjectClass *oc, void *data)
 118 {
 119     DeviceClass *dc = DEVICE_CLASS(oc);
 120
 121     dc->realize = ppc405_pob_realize;
 122     device_class_set_legacy_reset(dc, ppc405_pob_reset);
 123     /* Reason: only works as function of a ppc4xx SoC */
 124     dc->user_creatable = false;
 125 }
 126
 127 /*****************************************************************************/
 128 /* OPB arbitrer */
 129 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
 130 {
 131     Ppc405OpbaState *opba = opaque;
 132     uint32_t ret;
 133
 134     switch (addr) {
 135     case 0x00:
 136         ret = opba->cr;
 137         break;
 138     case 0x01:
 139         ret = opba->pr;
 140         break;
 141     default:
 142         ret = 0x00;
 143         break;
 144     }
 145
 146     trace_opba_readb(addr, ret);
 147     return ret;
 148 }
 149
 150 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
 151                         unsigned size)
 152 {
 153     Ppc405OpbaState *opba = opaque;
 154
 155     trace_opba_writeb(addr, value);
 156
 157     switch (addr) {
 158     case 0x00:
 159         opba->cr = value & 0xF8;
 160         break;
 161     case 0x01:
 162         opba->pr = value & 0xFF;
 163         break;
 164     default:
 165         break;
 166     }
 167 }
 168 static const MemoryRegionOps opba_ops = {
 169     .read = opba_readb,
 170     .write = opba_writeb,
 171     .impl.min_access_size = 1,
 172     .impl.max_access_size = 1,
 173     .valid.min_access_size = 1,
 174     .valid.max_access_size = 4,
 175     .endianness = DEVICE_BIG_ENDIAN,
 176 };
 177
 178 static void ppc405_opba_reset(DeviceState *dev)
 179 {
 180     Ppc405OpbaState *opba = PPC405_OPBA(dev);
 181
 182     opba->cr = 0x00; /* No dynamic priorities - park disabled */
 183     opba->pr = 0x11;
 184 }
 185
 186 static void ppc405_opba_realize(DeviceState *dev, Error **errp)
 187 {
 188     Ppc405OpbaState *s = PPC405_OPBA(dev);
 189
 190     memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 2);
 191     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io);
 192 }
 193
 194 static void ppc405_opba_class_init(ObjectClass *oc, void *data)
 195 {
 196     DeviceClass *dc = DEVICE_CLASS(oc);
 197
 198     dc->realize = ppc405_opba_realize;
 199     device_class_set_legacy_reset(dc, ppc405_opba_reset);
 200     /* Reason: only works as function of a ppc4xx SoC */
 201     dc->user_creatable = false;
 202 }
 203
 204 /*****************************************************************************/
 205 /* Code decompression controller */
 206 /* XXX: TODO */
 207
 208 /*****************************************************************************/
 209 /* DMA controller */
 210 enum {
 211     DMA0_CR0 = 0x100,
 212     DMA0_CT0 = 0x101,
 213     DMA0_DA0 = 0x102,
 214     DMA0_SA0 = 0x103,
 215     DMA0_SG0 = 0x104,
 216     DMA0_CR1 = 0x108,
 217     DMA0_CT1 = 0x109,
 218     DMA0_DA1 = 0x10A,
 219     DMA0_SA1 = 0x10B,
 220     DMA0_SG1 = 0x10C,
 221     DMA0_CR2 = 0x110,
 222     DMA0_CT2 = 0x111,
 223     DMA0_DA2 = 0x112,
 224     DMA0_SA2 = 0x113,
 225     DMA0_SG2 = 0x114,
 226     DMA0_CR3 = 0x118,
 227     DMA0_CT3 = 0x119,
 228     DMA0_DA3 = 0x11A,
 229     DMA0_SA3 = 0x11B,
 230     DMA0_SG3 = 0x11C,
 231     DMA0_SR  = 0x120,
 232     DMA0_SGC = 0x123,
 233     DMA0_SLP = 0x125,
 234     DMA0_POL = 0x126,
 235 };
 236
 237 static uint32_t dcr_read_dma(void *opaque, int dcrn)
 238 {
 239     return 0;
 240 }
 241
 242 static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
 243 {
 244 }
 245
 246 static void ppc405_dma_reset(DeviceState *dev)
 247 {
 248     Ppc405DmaState *dma = PPC405_DMA(dev);
 249     int i;
 250
 251     for (i = 0; i < 4; i++) {
 252         dma->cr[i] = 0x00000000;
 253         dma->ct[i] = 0x00000000;
 254         dma->da[i] = 0x00000000;
 255         dma->sa[i] = 0x00000000;
 256         dma->sg[i] = 0x00000000;
 257     }
 258     dma->sr = 0x00000000;
 259     dma->sgc = 0x00000000;
 260     dma->slp = 0x7C000000;
 261     dma->pol = 0x00000000;
 262 }
 263
 264 static void ppc405_dma_realize(DeviceState *dev, Error **errp)
 265 {
 266     Ppc405DmaState *dma = PPC405_DMA(dev);
 267     Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
 268     int i;
 269
 270     for (i = 0; i < ARRAY_SIZE(dma->irqs); i++) {
 271         sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]);
 272     }
 273
 274     ppc4xx_dcr_register(dcr, DMA0_CR0, dma, &dcr_read_dma, &dcr_write_dma);
 275     ppc4xx_dcr_register(dcr, DMA0_CT0, dma, &dcr_read_dma, &dcr_write_dma);
 276     ppc4xx_dcr_register(dcr, DMA0_DA0, dma, &dcr_read_dma, &dcr_write_dma);
 277     ppc4xx_dcr_register(dcr, DMA0_SA0, dma, &dcr_read_dma, &dcr_write_dma);
 278     ppc4xx_dcr_register(dcr, DMA0_SG0, dma, &dcr_read_dma, &dcr_write_dma);
 279     ppc4xx_dcr_register(dcr, DMA0_CR1, dma, &dcr_read_dma, &dcr_write_dma);
 280     ppc4xx_dcr_register(dcr, DMA0_CT1, dma, &dcr_read_dma, &dcr_write_dma);
 281     ppc4xx_dcr_register(dcr, DMA0_DA1, dma, &dcr_read_dma, &dcr_write_dma);
 282     ppc4xx_dcr_register(dcr, DMA0_SA1, dma, &dcr_read_dma, &dcr_write_dma);
 283     ppc4xx_dcr_register(dcr, DMA0_SG1, dma, &dcr_read_dma, &dcr_write_dma);
 284     ppc4xx_dcr_register(dcr, DMA0_CR2, dma, &dcr_read_dma, &dcr_write_dma);
 285     ppc4xx_dcr_register(dcr, DMA0_CT2, dma, &dcr_read_dma, &dcr_write_dma);
 286     ppc4xx_dcr_register(dcr, DMA0_DA2, dma, &dcr_read_dma, &dcr_write_dma);
 287     ppc4xx_dcr_register(dcr, DMA0_SA2, dma, &dcr_read_dma, &dcr_write_dma);
 288     ppc4xx_dcr_register(dcr, DMA0_SG2, dma, &dcr_read_dma, &dcr_write_dma);
 289     ppc4xx_dcr_register(dcr, DMA0_CR3, dma, &dcr_read_dma, &dcr_write_dma);
 290     ppc4xx_dcr_register(dcr, DMA0_CT3, dma, &dcr_read_dma, &dcr_write_dma);
 291     ppc4xx_dcr_register(dcr, DMA0_DA3, dma, &dcr_read_dma, &dcr_write_dma);
 292     ppc4xx_dcr_register(dcr, DMA0_SA3, dma, &dcr_read_dma, &dcr_write_dma);
 293     ppc4xx_dcr_register(dcr, DMA0_SG3, dma, &dcr_read_dma, &dcr_write_dma);
 294     ppc4xx_dcr_register(dcr, DMA0_SR,  dma, &dcr_read_dma, &dcr_write_dma);
 295     ppc4xx_dcr_register(dcr, DMA0_SGC, dma, &dcr_read_dma, &dcr_write_dma);
 296     ppc4xx_dcr_register(dcr, DMA0_SLP, dma, &dcr_read_dma, &dcr_write_dma);
 297     ppc4xx_dcr_register(dcr, DMA0_POL, dma, &dcr_read_dma, &dcr_write_dma);
 298 }
 299
 300 static void ppc405_dma_class_init(ObjectClass *oc, void *data)
 301 {
 302     DeviceClass *dc = DEVICE_CLASS(oc);
 303
 304     dc->realize = ppc405_dma_realize;
 305     device_class_set_legacy_reset(dc, ppc405_dma_reset);
 306     /* Reason: only works as function of a ppc4xx SoC */
 307     dc->user_creatable = false;
 308 }
 309
 310 /*****************************************************************************/
 311 /* GPIO */
 312 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
 313 {
 314     trace_ppc405_gpio_read(addr, size);
 315     return 0;
 316 }
 317
 318 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value,
 319                               unsigned size)
 320 {
 321     trace_ppc405_gpio_write(addr, size, value);
 322 }
 323
 324 static const MemoryRegionOps ppc405_gpio_ops = {
 325     .read = ppc405_gpio_read,
 326     .write = ppc405_gpio_write,
 327     .endianness = DEVICE_NATIVE_ENDIAN,
 328 };
 329
 330 static void ppc405_gpio_realize(DeviceState *dev, Error **errp)
 331 {
 332     Ppc405GpioState *s = PPC405_GPIO(dev);
 333
 334     memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio",
 335                           0x38);
 336     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io);
 337 }
 338
 339 static void ppc405_gpio_class_init(ObjectClass *oc, void *data)
 340 {
 341     DeviceClass *dc = DEVICE_CLASS(oc);
 342
 343     dc->realize = ppc405_gpio_realize;
 344     /* Reason: only works as function of a ppc4xx SoC */
 345     dc->user_creatable = false;
 346 }
 347
 348 /*****************************************************************************/
 349 /* On Chip Memory */
 350 enum {
 351     OCM0_ISARC   = 0x018,
 352     OCM0_ISACNTL = 0x019,
 353     OCM0_DSARC   = 0x01A,
 354     OCM0_DSACNTL = 0x01B,
 355 };
 356
 357 static void ocm_update_mappings(Ppc405OcmState *ocm,
 358                                 uint32_t isarc, uint32_t isacntl,
 359                                 uint32_t dsarc, uint32_t dsacntl)
 360 {
 361     trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
 362                               ocm->isacntl, ocm->dsarc, ocm->dsacntl);
 363
 364     if (ocm->isarc != isarc ||
 365         (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
 366         if (ocm->isacntl & 0x80000000) {
 367             /* Unmap previously assigned memory region */
 368             trace_ocm_unmap("ISA", ocm->isarc);
 369             memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
 370         }
 371         if (isacntl & 0x80000000) {
 372             /* Map new instruction memory region */
 373             trace_ocm_map("ISA", isarc);
 374             memory_region_add_subregion(get_system_memory(), isarc,
 375                                         &ocm->isarc_ram);
 376         }
 377     }
 378     if (ocm->dsarc != dsarc ||
 379         (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
 380         if (ocm->dsacntl & 0x80000000) {
 381             /* Beware not to unmap the region we just mapped */
 382             if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
 383                 /* Unmap previously assigned memory region */
 384                 trace_ocm_unmap("DSA", ocm->dsarc);
 385                 memory_region_del_subregion(get_system_memory(),
 386                                             &ocm->dsarc_ram);
 387             }
 388         }
 389         if (dsacntl & 0x80000000) {
 390             /* Beware not to remap the region we just mapped */
 391             if (!(isacntl & 0x80000000) || dsarc != isarc) {
 392                 /* Map new data memory region */
 393                 trace_ocm_map("DSA", dsarc);
 394                 memory_region_add_subregion(get_system_memory(), dsarc,
 395                                             &ocm->dsarc_ram);
 396             }
 397         }
 398     }
 399 }
 400
 401 static uint32_t dcr_read_ocm(void *opaque, int dcrn)
 402 {
 403     Ppc405OcmState *ocm = opaque;
 404     uint32_t ret;
 405
 406     switch (dcrn) {
 407     case OCM0_ISARC:
 408         ret = ocm->isarc;
 409         break;
 410     case OCM0_ISACNTL:
 411         ret = ocm->isacntl;
 412         break;
 413     case OCM0_DSARC:
 414         ret = ocm->dsarc;
 415         break;
 416     case OCM0_DSACNTL:
 417         ret = ocm->dsacntl;
 418         break;
 419     default:
 420         ret = 0;
 421         break;
 422     }
 423
 424     return ret;
 425 }
 426
 427 static void dcr_write_ocm(void *opaque, int dcrn, uint32_t val)
 428 {
 429     Ppc405OcmState *ocm = opaque;
 430     uint32_t isarc, dsarc, isacntl, dsacntl;
 431
 432     isarc = ocm->isarc;
 433     dsarc = ocm->dsarc;
 434     isacntl = ocm->isacntl;
 435     dsacntl = ocm->dsacntl;
 436     switch (dcrn) {
 437     case OCM0_ISARC:
 438         isarc = val & 0xFC000000;
 439         break;
 440     case OCM0_ISACNTL:
 441         isacntl = val & 0xC0000000;
 442         break;
 443     case OCM0_DSARC:
 444         isarc = val & 0xFC000000;
 445         break;
 446     case OCM0_DSACNTL:
 447         isacntl = val & 0xC0000000;
 448         break;
 449     }
 450     ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
 451     ocm->isarc = isarc;
 452     ocm->dsarc = dsarc;
 453     ocm->isacntl = isacntl;
 454     ocm->dsacntl = dsacntl;
 455 }
 456
 457 static void ppc405_ocm_reset(DeviceState *dev)
 458 {
 459     Ppc405OcmState *ocm = PPC405_OCM(dev);
 460     uint32_t isarc, dsarc, isacntl, dsacntl;
 461
 462     isarc = 0x00000000;
 463     isacntl = 0x00000000;
 464     dsarc = 0x00000000;
 465     dsacntl = 0x00000000;
 466     ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
 467     ocm->isarc = isarc;
 468     ocm->dsarc = dsarc;
 469     ocm->isacntl = isacntl;
 470     ocm->dsacntl = dsacntl;
 471 }
 472
 473 static void ppc405_ocm_realize(DeviceState *dev, Error **errp)
 474 {
 475     Ppc405OcmState *ocm = PPC405_OCM(dev);
 476     Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
 477
 478     /* XXX: Size is 4096 or 0x04000000 */
 479     memory_region_init_ram(&ocm->isarc_ram, OBJECT(ocm), "ppc405.ocm", 4 * KiB,
 480                            &error_fatal);
 481     memory_region_init_alias(&ocm->dsarc_ram, OBJECT(ocm), "ppc405.dsarc",
 482                              &ocm->isarc_ram, 0, 4 * KiB);
 483
 484     ppc4xx_dcr_register(dcr, OCM0_ISARC, ocm, &dcr_read_ocm, &dcr_write_ocm);
 485     ppc4xx_dcr_register(dcr, OCM0_ISACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm);
 486     ppc4xx_dcr_register(dcr, OCM0_DSARC, ocm, &dcr_read_ocm, &dcr_write_ocm);
 487     ppc4xx_dcr_register(dcr, OCM0_DSACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm);
 488 }
 489
 490 static void ppc405_ocm_class_init(ObjectClass *oc, void *data)
 491 {
 492     DeviceClass *dc = DEVICE_CLASS(oc);
 493
 494     dc->realize = ppc405_ocm_realize;
 495     device_class_set_legacy_reset(dc, ppc405_ocm_reset);
 496     /* Reason: only works as function of a ppc4xx SoC */
 497     dc->user_creatable = false;
 498 }
 499
 500 /*****************************************************************************/
 501 /* General purpose timers */
 502 static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n)
 503 {
 504     /* XXX: TODO */
 505     return 0;
 506 }
 507
 508 static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level)
 509 {
 510     /* XXX: TODO */
 511 }
 512
 513 static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt)
 514 {
 515     uint32_t mask;
 516     int i;
 517
 518     mask = 0x80000000;
 519     for (i = 0; i < 5; i++) {
 520         if (gpt->oe & mask) {
 521             /* Output is enabled */
 522             if (ppc4xx_gpt_compare(gpt, i)) {
 523                 /* Comparison is OK */
 524                 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
 525             } else {
 526                 /* Comparison is KO */
 527                 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
 528             }
 529         }
 530         mask = mask >> 1;
 531     }
 532 }
 533
 534 static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt)
 535 {
 536     uint32_t mask;
 537     int i;
 538
 539     mask = 0x00008000;
 540     for (i = 0; i < 5; i++) {
 541         if (gpt->is & gpt->im & mask) {
 542             qemu_irq_raise(gpt->irqs[i]);
 543         } else {
 544             qemu_irq_lower(gpt->irqs[i]);
 545         }
 546         mask = mask >> 1;
 547     }
 548 }
 549
 550 static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt)
 551 {
 552     /* XXX: TODO */
 553 }
 554
 555 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
 556 {
 557     Ppc405GptState *gpt = opaque;
 558     uint32_t ret;
 559     int idx;
 560
 561     trace_ppc4xx_gpt_read(addr, size);
 562
 563     switch (addr) {
 564     case 0x00:
 565         /* Time base counter */
 566         ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
 567                        gpt->tb_freq, NANOSECONDS_PER_SECOND);
 568         break;
 569     case 0x10:
 570         /* Output enable */
 571         ret = gpt->oe;
 572         break;
 573     case 0x14:
 574         /* Output level */
 575         ret = gpt->ol;
 576         break;
 577     case 0x18:
 578         /* Interrupt mask */
 579         ret = gpt->im;
 580         break;
 581     case 0x1C:
 582     case 0x20:
 583         /* Interrupt status */
 584         ret = gpt->is;
 585         break;
 586     case 0x24:
 587         /* Interrupt enable */
 588         ret = gpt->ie;
 589         break;
 590     case 0x80 ... 0x90:
 591         /* Compare timer */
 592         idx = (addr - 0x80) >> 2;
 593         ret = gpt->comp[idx];
 594         break;
 595     case 0xC0 ... 0xD0:
 596         /* Compare mask */
 597         idx = (addr - 0xC0) >> 2;
 598         ret = gpt->mask[idx];
 599         break;
 600     default:
 601         ret = -1;
 602         break;
 603     }
 604
 605     return ret;
 606 }
 607
 608 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
 609                              unsigned size)
 610 {
 611     Ppc405GptState *gpt = opaque;
 612     int idx;
 613
 614     trace_ppc4xx_gpt_write(addr, size, value);
 615
 616     switch (addr) {
 617     case 0x00:
 618         /* Time base counter */
 619         gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq)
 620             - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 621         ppc4xx_gpt_compute_timer(gpt);
 622         break;
 623     case 0x10:
 624         /* Output enable */
 625         gpt->oe = value & 0xF8000000;
 626         ppc4xx_gpt_set_outputs(gpt);
 627         break;
 628     case 0x14:
 629         /* Output level */
 630         gpt->ol = value & 0xF8000000;
 631         ppc4xx_gpt_set_outputs(gpt);
 632         break;
 633     case 0x18:
 634         /* Interrupt mask */
 635         gpt->im = value & 0x0000F800;
 636         break;
 637     case 0x1C:
 638         /* Interrupt status set */
 639         gpt->is |= value & 0x0000F800;
 640         ppc4xx_gpt_set_irqs(gpt);
 641         break;
 642     case 0x20:
 643         /* Interrupt status clear */
 644         gpt->is &= ~(value & 0x0000F800);
 645         ppc4xx_gpt_set_irqs(gpt);
 646         break;
 647     case 0x24:
 648         /* Interrupt enable */
 649         gpt->ie = value & 0x0000F800;
 650         ppc4xx_gpt_set_irqs(gpt);
 651         break;
 652     case 0x80 ... 0x90:
 653         /* Compare timer */
 654         idx = (addr - 0x80) >> 2;
 655         gpt->comp[idx] = value & 0xF8000000;
 656         ppc4xx_gpt_compute_timer(gpt);
 657         break;
 658     case 0xC0 ... 0xD0:
 659         /* Compare mask */
 660         idx = (addr - 0xC0) >> 2;
 661         gpt->mask[idx] = value & 0xF8000000;
 662         ppc4xx_gpt_compute_timer(gpt);
 663         break;
 664     }
 665 }
 666
 667 static const MemoryRegionOps gpt_ops = {
 668     .read = ppc4xx_gpt_read,
 669     .write = ppc4xx_gpt_write,
 670     .valid.min_access_size = 4,
 671     .valid.max_access_size = 4,
 672     .endianness = DEVICE_NATIVE_ENDIAN,
 673 };
 674
 675 static void ppc4xx_gpt_cb(void *opaque)
 676 {
 677     Ppc405GptState *gpt = opaque;
 678
 679     ppc4xx_gpt_set_irqs(gpt);
 680     ppc4xx_gpt_set_outputs(gpt);
 681     ppc4xx_gpt_compute_timer(gpt);
 682 }
 683
 684 static void ppc405_gpt_reset(DeviceState *dev)
 685 {
 686     Ppc405GptState *gpt = PPC405_GPT(dev);
 687     int i;
 688
 689     timer_del(gpt->timer);
 690     gpt->oe = 0x00000000;
 691     gpt->ol = 0x00000000;
 692     gpt->im = 0x00000000;
 693     gpt->is = 0x00000000;
 694     gpt->ie = 0x00000000;
 695     for (i = 0; i < 5; i++) {
 696         gpt->comp[i] = 0x00000000;
 697         gpt->mask[i] = 0x00000000;
 698     }
 699 }
 700
 701 static void ppc405_gpt_realize(DeviceState *dev, Error **errp)
 702 {
 703     Ppc405GptState *s = PPC405_GPT(dev);
 704     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 705     int i;
 706
 707     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s);
 708     memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0xd4);
 709     sysbus_init_mmio(sbd, &s->iomem);
 710
 711     for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
 712         sysbus_init_irq(sbd, &s->irqs[i]);
 713     }
 714 }
 715
 716 static void ppc405_gpt_finalize(Object *obj)
 717 {
 718     /* timer will be NULL if the GPT wasn't realized */
 719     if (PPC405_GPT(obj)->timer) {
 720         timer_del(PPC405_GPT(obj)->timer);
 721     }
 722 }
 723
 724 static void ppc405_gpt_class_init(ObjectClass *oc, void *data)
 725 {
 726     DeviceClass *dc = DEVICE_CLASS(oc);
 727
 728     dc->realize = ppc405_gpt_realize;
 729     device_class_set_legacy_reset(dc, ppc405_gpt_reset);
 730     /* Reason: only works as function of a ppc4xx SoC */
 731     dc->user_creatable = false;
 732 }
 733
 734 /*****************************************************************************/
 735 /* PowerPC 405EP */
 736 /* CPU control */
 737 enum {
 738     PPC405EP_CPC0_PLLMR0 = 0x0F0,
 739     PPC405EP_CPC0_BOOT   = 0x0F1,
 740     PPC405EP_CPC0_EPCTL  = 0x0F3,
 741     PPC405EP_CPC0_PLLMR1 = 0x0F4,
 742     PPC405EP_CPC0_UCR    = 0x0F5,
 743     PPC405EP_CPC0_SRR    = 0x0F6,
 744     PPC405EP_CPC0_JTAGID = 0x0F7,
 745     PPC405EP_CPC0_PCI    = 0x0F9,
 746 #if 0
 747     PPC405EP_CPC0_ER     = xxx,
 748     PPC405EP_CPC0_FR     = xxx,
 749     PPC405EP_CPC0_SR     = xxx,
 750 #endif
 751 };
 752
 753 static void ppc405ep_compute_clocks(Ppc405CpcState *cpc)
 754 {
 755     uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
 756     uint32_t UART0_clk, UART1_clk;
 757     uint64_t VCO_out, PLL_out;
 758     int M, D;
 759
 760     VCO_out = 0;
 761     if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
 762         M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
 763         trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M);
 764         D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
 765         trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D);
 766         VCO_out = (uint64_t)cpc->sysclk * M * D;
 767         if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
 768             /* Error - unlock the PLL */
 769             qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n",
 770                           VCO_out);
 771 #if 0
 772             cpc->pllmr[1] &= ~0x80000000;
 773             goto pll_bypass;
 774 #endif
 775         }
 776         PLL_out = VCO_out / D;
 777         /* Pretend the PLL is locked */
 778         cpc->boot |= 0x00000001;
 779     } else {
 780 #if 0
 781     pll_bypass:
 782 #endif
 783         PLL_out = cpc->sysclk;
 784         if (cpc->pllmr[1] & 0x40000000) {
 785             /* Pretend the PLL is not locked */
 786             cpc->boot &= ~0x00000001;
 787         }
 788     }
 789     /* Now, compute all other clocks */
 790     D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
 791      trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D);
 792     CPU_clk = PLL_out / D;
 793     D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
 794     trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D);
 795     PLB_clk = CPU_clk / D;
 796     D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
 797     trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D);
 798     OPB_clk = PLB_clk / D;
 799     D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
 800     trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D);
 801     EBC_clk = PLB_clk / D;
 802     D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
 803     trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D);
 804     MAL_clk = PLB_clk / D;
 805     D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
 806     trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D);
 807     PCI_clk = PLB_clk / D;
 808     D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
 809     trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D);
 810     UART0_clk = PLL_out / D;
 811     D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
 812     trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D);
 813     UART1_clk = PLL_out / D;
 814
 815     if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) {
 816         g_autofree char *trace = g_strdup_printf(
 817             "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
 818             " PLL out %" PRIu64 " Hz\n"
 819             "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
 820             " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
 821             " UART1 %" PRIu32 "\n",
 822             cpc->sysclk, VCO_out, PLL_out,
 823             CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
 824             UART0_clk, UART1_clk);
 825         trace_ppc405ep_clocks_setup(trace);
 826     }
 827
 828     /* Setup CPU clocks */
 829     clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
 830     /* Setup PLB clock */
 831     clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
 832     /* Setup OPB clock */
 833     clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
 834     /* Setup external clock */
 835     clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
 836     /* Setup MAL clock */
 837     clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
 838     /* Setup PCI clock */
 839     clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
 840     /* Setup UART0 clock */
 841     clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
 842     /* Setup UART1 clock */
 843     clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
 844 }
 845
 846 static uint32_t dcr_read_epcpc(void *opaque, int dcrn)
 847 {
 848     Ppc405CpcState *cpc = opaque;
 849     uint32_t ret;
 850
 851     switch (dcrn) {
 852     case PPC405EP_CPC0_BOOT:
 853         ret = cpc->boot;
 854         break;
 855     case PPC405EP_CPC0_EPCTL:
 856         ret = cpc->epctl;
 857         break;
 858     case PPC405EP_CPC0_PLLMR0:
 859         ret = cpc->pllmr[0];
 860         break;
 861     case PPC405EP_CPC0_PLLMR1:
 862         ret = cpc->pllmr[1];
 863         break;
 864     case PPC405EP_CPC0_UCR:
 865         ret = cpc->ucr;
 866         break;
 867     case PPC405EP_CPC0_SRR:
 868         ret = cpc->srr;
 869         break;
 870     case PPC405EP_CPC0_JTAGID:
 871         ret = cpc->jtagid;
 872         break;
 873     case PPC405EP_CPC0_PCI:
 874         ret = cpc->pci;
 875         break;
 876     default:
 877         /* Avoid gcc warning */
 878         ret = 0;
 879         break;
 880     }
 881
 882     return ret;
 883 }
 884
 885 static void dcr_write_epcpc(void *opaque, int dcrn, uint32_t val)
 886 {
 887     Ppc405CpcState *cpc = opaque;
 888
 889     switch (dcrn) {
 890     case PPC405EP_CPC0_BOOT:
 891         /* Read-only register */
 892         break;
 893     case PPC405EP_CPC0_EPCTL:
 894         /* Don't care for now */
 895         cpc->epctl = val & 0xC00000F3;
 896         break;
 897     case PPC405EP_CPC0_PLLMR0:
 898         cpc->pllmr[0] = val & 0x00633333;
 899         ppc405ep_compute_clocks(cpc);
 900         break;
 901     case PPC405EP_CPC0_PLLMR1:
 902         cpc->pllmr[1] = val & 0xC0F73FFF;
 903         ppc405ep_compute_clocks(cpc);
 904         break;
 905     case PPC405EP_CPC0_UCR:
 906         /* UART control - don't care for now */
 907         cpc->ucr = val & 0x003F7F7F;
 908         break;
 909     case PPC405EP_CPC0_SRR:
 910         cpc->srr = val;
 911         break;
 912     case PPC405EP_CPC0_JTAGID:
 913         /* Read-only */
 914         break;
 915     case PPC405EP_CPC0_PCI:
 916         cpc->pci = val;
 917         break;
 918     }
 919 }
 920
 921 static void ppc405_cpc_reset(DeviceState *dev)
 922 {
 923     Ppc405CpcState *cpc = PPC405_CPC(dev);
 924
 925     cpc->boot = 0x00000010;     /* Boot from PCI - IIC EEPROM disabled */
 926     cpc->epctl = 0x00000000;
 927     cpc->pllmr[0] = 0x00021002;
 928     cpc->pllmr[1] = 0x80a552be;
 929     cpc->ucr = 0x00004646;
 930     cpc->srr = 0x00040000;
 931     cpc->pci = 0x00000000;
 932     cpc->er = 0x00000000;
 933     cpc->fr = 0x00000000;
 934     cpc->sr = 0x00000000;
 935     cpc->jtagid = 0x20267049;
 936     ppc405ep_compute_clocks(cpc);
 937 }
 938
 939 /* XXX: sysclk should be between 25 and 100 MHz */
 940 static void ppc405_cpc_realize(DeviceState *dev, Error **errp)
 941 {
 942     Ppc405CpcState *cpc = PPC405_CPC(dev);
 943     Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
 944
 945     assert(dcr->cpu);
 946     cpc->clk_setup[PPC405EP_CPU_CLK].cb =
 947         ppc_40x_timers_init(&dcr->cpu->env, cpc->sysclk, PPC_INTERRUPT_PIT);
 948     cpc->clk_setup[PPC405EP_CPU_CLK].opaque = &dcr->cpu->env;
 949
 950     ppc4xx_dcr_register(dcr, PPC405EP_CPC0_BOOT, cpc,
 951                         &dcr_read_epcpc, &dcr_write_epcpc);
 952     ppc4xx_dcr_register(dcr, PPC405EP_CPC0_EPCTL, cpc,
 953                         &dcr_read_epcpc, &dcr_write_epcpc);
 954     ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR0, cpc,
 955                         &dcr_read_epcpc, &dcr_write_epcpc);
 956     ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR1, cpc,
 957                         &dcr_read_epcpc, &dcr_write_epcpc);
 958     ppc4xx_dcr_register(dcr, PPC405EP_CPC0_UCR, cpc,
 959                         &dcr_read_epcpc, &dcr_write_epcpc);
 960     ppc4xx_dcr_register(dcr, PPC405EP_CPC0_SRR, cpc,
 961                         &dcr_read_epcpc, &dcr_write_epcpc);
 962     ppc4xx_dcr_register(dcr, PPC405EP_CPC0_JTAGID, cpc,
 963                         &dcr_read_epcpc, &dcr_write_epcpc);
 964     ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PCI, cpc,
 965                         &dcr_read_epcpc, &dcr_write_epcpc);
 966 }
 967
 968 static Property ppc405_cpc_properties[] = {
 969     DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState, sysclk, 0),
 970     DEFINE_PROP_END_OF_LIST(),
 971 };
 972
 973 static void ppc405_cpc_class_init(ObjectClass *oc, void *data)
 974 {
 975     DeviceClass *dc = DEVICE_CLASS(oc);
 976
 977     dc->realize = ppc405_cpc_realize;
 978     device_class_set_legacy_reset(dc, ppc405_cpc_reset);
 979     /* Reason: only works as function of a ppc4xx SoC */
 980     dc->user_creatable = false;
 981     device_class_set_props(dc, ppc405_cpc_properties);
 982 }
 983
 984 /* PPC405_SOC */
 985
 986 static void ppc405_soc_instance_init(Object *obj)
 987 {
 988     Ppc405SoCState *s = PPC405_SOC(obj);
 989
 990     object_initialize_child(obj, "cpu", &s->cpu,
 991                             POWERPC_CPU_TYPE_NAME("405ep"));
 992
 993     object_initialize_child(obj, "uic", &s->uic, TYPE_PPC_UIC);
 994
 995     object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
 996     object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
 997
 998     object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
 999
1000     object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
1001
1002     object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
1003
1004     object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
1005
1006     object_initialize_child(obj, "i2c", &s->i2c, TYPE_PPC4xx_I2C);
1007
1008     object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC4xx_EBC);
1009
1010     object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
1011
1012     object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
1013
1014     object_initialize_child(obj, "plb", &s->plb, TYPE_PPC4xx_PLB);
1015
1016     object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
1017
1018     object_initialize_child(obj, "sdram", &s->sdram, TYPE_PPC4xx_SDRAM_DDR);
1019     object_property_add_alias(obj, "dram", OBJECT(&s->sdram), "dram");
1020 }
1021
1022 static void ppc405_reset(void *opaque)
1023 {
1024     cpu_reset(CPU(opaque));
1025 }
1026
1027 static void ppc405_soc_realize(DeviceState *dev, Error **errp)
1028 {
1029     Ppc405SoCState *s = PPC405_SOC(dev);
1030     CPUPPCState *env;
1031     SysBusDevice *sbd;
1032     int i;
1033
1034     /* init CPUs */
1035     if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
1036         return;
1037     }
1038     qemu_register_reset(ppc405_reset, &s->cpu);
1039
1040     env = &s->cpu.env;
1041
1042     ppc_dcr_init(env, NULL, NULL);
1043
1044     /* CPU control */
1045     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->cpc), &s->cpu, errp)) {
1046         return;
1047     }
1048
1049     /* PLB arbitrer */
1050     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->plb), &s->cpu, errp)) {
1051         return;
1052     }
1053
1054     /* PLB to OPB bridge */
1055     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) {
1056         return;
1057     }
1058
1059     /* OBP arbitrer */
1060     sbd = SYS_BUS_DEVICE(&s->opba);
1061     if (!sysbus_realize(sbd, errp)) {
1062         return;
1063     }
1064     sysbus_mmio_map(sbd, 0, 0xef600600);
1065
1066     /* Universal interrupt controller */
1067     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->uic), &s->cpu, errp)) {
1068         return;
1069     }
1070     sbd = SYS_BUS_DEVICE(&s->uic);
1071     sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
1072                        qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
1073     sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
1074                        qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
1075
1076     /* SDRAM controller */
1077     /*
1078      * We use the 440 DDR SDRAM controller which has more regs and features
1079      * but it's compatible enough for now
1080      */
1081     object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort);
1082     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) {
1083         return;
1084     }
1085     /* XXX 405EP has no ECC interrupt */
1086     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdram), 0,
1087                        qdev_get_gpio_in(DEVICE(&s->uic), 17));
1088
1089     /* External bus controller */
1090     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
1091         return;
1092     }
1093
1094     /* DMA controller */
1095     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) {
1096         return;
1097     }
1098     sbd = SYS_BUS_DEVICE(&s->dma);
1099     for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
1100         sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 5 + i));
1101     }
1102
1103     /* I2C controller */
1104     sbd = SYS_BUS_DEVICE(&s->i2c);
1105     if (!sysbus_realize(sbd, errp)) {
1106         return;
1107     }
1108     sysbus_mmio_map(sbd, 0, 0xef600500);
1109     sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(&s->uic), 2));
1110
1111     /* GPIO */
1112     sbd = SYS_BUS_DEVICE(&s->gpio);
1113     if (!sysbus_realize(sbd, errp)) {
1114         return;
1115     }
1116     sysbus_mmio_map(sbd, 0, 0xef600700);
1117
1118     /* Serial ports */
1119     if (serial_hd(0) != NULL) {
1120         serial_mm_init(get_system_memory(), 0xef600300, 0,
1121                        qdev_get_gpio_in(DEVICE(&s->uic), 0),
1122                        PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
1123                        DEVICE_BIG_ENDIAN);
1124     }
1125     if (serial_hd(1) != NULL) {
1126         serial_mm_init(get_system_memory(), 0xef600400, 0,
1127                        qdev_get_gpio_in(DEVICE(&s->uic), 1),
1128                        PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
1129                        DEVICE_BIG_ENDIAN);
1130     }
1131
1132     /* OCM */
1133     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ocm), &s->cpu, errp)) {
1134         return;
1135     }
1136
1137     /* GPT */
1138     sbd = SYS_BUS_DEVICE(&s->gpt);
1139     if (!sysbus_realize(sbd, errp)) {
1140         return;
1141     }
1142     sysbus_mmio_map(sbd, 0, 0xef600000);
1143     for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
1144         sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 19 + i));
1145     }
1146
1147     /* MAL */
1148     object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort);
1149     object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort);
1150     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) {
1151         return;
1152     }
1153     sbd = SYS_BUS_DEVICE(&s->mal);
1154     for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
1155         sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 11 + i));
1156     }
1157
1158     /* Ethernet */
1159     /* Uses UIC IRQs 9, 15, 17 */
1160 }
1161
1162 static void ppc405_soc_class_init(ObjectClass *oc, void *data)
1163 {
1164     DeviceClass *dc = DEVICE_CLASS(oc);
1165
1166     dc->realize = ppc405_soc_realize;
1167     /* Reason: only works as part of a ppc405 board/machine */
1168     dc->user_creatable = false;
1169 }
1170
1171 static const TypeInfo ppc405_types[] = {
1172     {
1173         .name           = TYPE_PPC405_POB,
1174         .parent         = TYPE_PPC4xx_DCR_DEVICE,
1175         .instance_size  = sizeof(Ppc405PobState),
1176         .class_init     = ppc405_pob_class_init,
1177     }, {
1178         .name           = TYPE_PPC405_OPBA,
1179         .parent         = TYPE_SYS_BUS_DEVICE,
1180         .instance_size  = sizeof(Ppc405OpbaState),
1181         .class_init     = ppc405_opba_class_init,
1182     }, {
1183         .name           = TYPE_PPC405_DMA,
1184         .parent         = TYPE_PPC4xx_DCR_DEVICE,
1185         .instance_size  = sizeof(Ppc405DmaState),
1186         .class_init     = ppc405_dma_class_init,
1187     }, {
1188         .name           = TYPE_PPC405_GPIO,
1189         .parent         = TYPE_SYS_BUS_DEVICE,
1190         .instance_size  = sizeof(Ppc405GpioState),
1191         .class_init     = ppc405_gpio_class_init,
1192     }, {
1193         .name           = TYPE_PPC405_OCM,
1194         .parent         = TYPE_PPC4xx_DCR_DEVICE,
1195         .instance_size  = sizeof(Ppc405OcmState),
1196         .class_init     = ppc405_ocm_class_init,
1197     }, {
1198         .name           = TYPE_PPC405_GPT,
1199         .parent         = TYPE_SYS_BUS_DEVICE,
1200         .instance_size  = sizeof(Ppc405GptState),
1201         .instance_finalize = ppc405_gpt_finalize,
1202         .class_init     = ppc405_gpt_class_init,
1203     }, {
1204         .name           = TYPE_PPC405_CPC,
1205         .parent         = TYPE_PPC4xx_DCR_DEVICE,
1206         .instance_size  = sizeof(Ppc405CpcState),
1207         .class_init     = ppc405_cpc_class_init,
1208     }, {
1209         .name           = TYPE_PPC405_SOC,
1210         .parent         = TYPE_DEVICE,
1211         .instance_size  = sizeof(Ppc405SoCState),
1212         .instance_init  = ppc405_soc_instance_init,
1213         .class_init     = ppc405_soc_class_init,
1214     }
1215 };
1216
1217 DEFINE_TYPES(ppc405_types)