hw/ppc/sam460ex.c

   1 /*
   2  * QEMU aCube Sam460ex board emulation
   3  *
   4  * Copyright (c) 2012 François Revol
   5  * Copyright (c) 2016-2019 BALATON Zoltan
   6  *
   7  * This file is derived from hw/ppc440_bamboo.c,
   8  * the copyright for that material belongs to the original owners.
   9  *
  10  * This work is licensed under the GNU GPL license version 2 or later.
  11  *
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu/units.h"
  16 #include "qemu/datadir.h"
  17 #include "qemu/error-report.h"
  18 #include "qapi/error.h"
  19 #include "hw/boards.h"
  20 #include "sysemu/kvm.h"
  21 #include "kvm_ppc.h"
  22 #include "sysemu/device_tree.h"
  23 #include "sysemu/block-backend.h"
  24 #include "exec/page-protection.h"
  25 #include "hw/loader.h"
  26 #include "elf.h"
  27 #include "exec/memory.h"
  28 #include "ppc440.h"
  29 #include "hw/pci-host/ppc4xx.h"
  30 #include "hw/block/flash.h"
  31 #include "sysemu/sysemu.h"
  32 #include "sysemu/reset.h"
  33 #include "hw/sysbus.h"
  34 #include "hw/char/serial-mm.h"
  35 #include "hw/i2c/ppc4xx_i2c.h"
  36 #include "hw/i2c/smbus_eeprom.h"
  37 #include "hw/ide/pci.h"
  38 #include "hw/usb/hcd-ehci.h"
  39 #include "hw/ppc/fdt.h"
  40 #include "hw/qdev-properties.h"
  41 #include "hw/intc/ppc-uic.h"
  42
  43 #include <libfdt.h>
  44
  45 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb"
  46 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
  47 /* to extract the official U-Boot bin from the updater: */
  48 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
  49      if=updater/updater-460 of=u-boot-sam460-20100605.bin */
  50
  51 #define PCIE0_DCRN_BASE 0x100
  52 #define PCIE1_DCRN_BASE 0x120
  53
  54 /* from Sam460 U-Boot include/configs/Sam460ex.h */
  55 #define FLASH_BASE             0xfff00000
  56 #define FLASH_BASE_H           0x4
  57 #define FLASH_SIZE             (1 * MiB)
  58 #define UBOOT_LOAD_BASE        0xfff80000
  59 #define UBOOT_SIZE             0x00080000
  60 #define UBOOT_ENTRY            0xfffffffc
  61
  62 /* from U-Boot */
  63 #define EPAPR_MAGIC           (0x45504150)
  64 #define KERNEL_ADDR           0x1000000
  65 #define FDT_ADDR              0x1800000
  66 #define RAMDISK_ADDR          0x1900000
  67
  68 /* Sam460ex IRQ MAP:
  69    IRQ0  = ETH_INT
  70    IRQ1  = FPGA_INT
  71    IRQ2  = PCI_INT (PCIA, PCIB, PCIC, PCIB)
  72    IRQ3  = FPGA_INT2
  73    IRQ11 = RTC_INT
  74    IRQ12 = SM502_INT
  75 */
  76
  77 #define CPU_FREQ 1150000000
  78 #define PLB_FREQ 230000000
  79 #define OPB_FREQ 115000000
  80 #define EBC_FREQ 115000000
  81 #define UART_FREQ 11059200
  82
  83 struct boot_info {
  84     uint32_t dt_base;
  85     uint32_t dt_size;
  86     uint32_t entry;
  87 };
  88
  89 static int sam460ex_load_uboot(void)
  90 {
  91     /*
  92      * This first creates 1MiB of flash memory mapped at the end of
  93      * the 32-bit address space (0xFFF00000..0xFFFFFFFF).
  94      *
  95      * If_PFLASH unit 0 is defined, the flash memory is initialized
  96      * from that block backend.
  97      *
  98      * Else, it's initialized to zero.  And then 512KiB of ROM get
  99      * mapped on top of its second half (0xFFF80000..0xFFFFFFFF),
 100      * initialized from u-boot-sam460-20100605.bin.
 101      *
 102      * This doesn't smell right.
 103      *
 104      * The physical hardware appears to have 512KiB flash memory.
 105      *
 106      * TODO Figure out what we really need here, and clean this up.
 107      */
 108
 109     DriveInfo *dinfo;
 110
 111     dinfo = drive_get(IF_PFLASH, 0, 0);
 112     if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32),
 113                                "sam460ex.flash", FLASH_SIZE,
 114                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 115                                64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) {
 116         error_report("Error registering flash memory");
 117         /* XXX: return an error instead? */
 118         exit(1);
 119     }
 120
 121     if (!dinfo) {
 122         /*error_report("No flash image given with the 'pflash' parameter,"
 123                 " using default u-boot image");*/
 124         rom_add_file_fixed(UBOOT_FILENAME,
 125                            UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32),
 126                            -1);
 127     }
 128
 129     return 0;
 130 }
 131
 132 static int sam460ex_load_device_tree(MachineState *machine,
 133                                      hwaddr addr,
 134                                      hwaddr initrd_base,
 135                                      hwaddr initrd_size)
 136 {
 137     uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) };
 138     char *filename;
 139     int fdt_size;
 140     void *fdt;
 141     uint32_t tb_freq = CPU_FREQ;
 142     uint32_t clock_freq = CPU_FREQ;
 143     int offset;
 144
 145     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
 146     if (!filename) {
 147         error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE);
 148         exit(1);
 149     }
 150     fdt = load_device_tree(filename, &fdt_size);
 151     if (!fdt) {
 152         error_report("Couldn't load dtb file `%s'", filename);
 153         g_free(filename);
 154         exit(1);
 155     }
 156     g_free(filename);
 157
 158     /* Manipulate device tree in memory. */
 159
 160     qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
 161                      sizeof(mem_reg_property));
 162
 163     /* default FDT doesn't have a /chosen node... */
 164     qemu_fdt_add_subnode(fdt, "/chosen");
 165
 166     qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base);
 167
 168     qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 169                           (initrd_base + initrd_size));
 170
 171     qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
 172                             machine->kernel_cmdline);
 173
 174     /* Copy data from the host device tree into the guest. Since the guest can
 175      * directly access the timebase without host involvement, we must expose
 176      * the correct frequencies. */
 177     if (kvm_enabled()) {
 178         tb_freq = kvmppc_get_tbfreq();
 179         clock_freq = kvmppc_get_clockfreq();
 180     }
 181
 182     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
 183                               clock_freq);
 184     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
 185                               tb_freq);
 186
 187     /* Remove cpm node if it exists (it is not emulated) */
 188     offset = fdt_path_offset(fdt, "/cpm");
 189     if (offset >= 0) {
 190         _FDT(fdt_nop_node(fdt, offset));
 191     }
 192
 193     /* set serial port clocks */
 194     offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550");
 195     while (offset >= 0) {
 196         _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ));
 197         offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550");
 198     }
 199
 200     /* some more clocks */
 201     qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency",
 202                               PLB_FREQ);
 203     qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency",
 204                               OPB_FREQ);
 205     qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency",
 206                               EBC_FREQ);
 207
 208     rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 209
 210     /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
 211     machine->fdt = fdt;
 212
 213     return fdt_size;
 214 }
 215
 216 /* Create reset TLB entries for BookE, mapping only the flash memory.  */
 217 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env)
 218 {
 219     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
 220
 221     /* on reset the flash is mapped by a shadow TLB,
 222      * but since we don't implement them we need to use
 223      * the same values U-Boot will use to avoid a fault.
 224      */
 225     tlb->attr = 0;
 226     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 227     tlb->size = 0x10000000; /* up to 0xffffffff  */
 228     tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK;
 229     tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4;
 230     tlb->PID = 0;
 231 }
 232
 233 /* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
 234 static void mmubooke_create_initial_mapping(CPUPPCState *env,
 235                                      target_ulong va,
 236                                      hwaddr pa)
 237 {
 238     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
 239
 240     tlb->attr = 0;
 241     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 242     tlb->size = 1 << 31; /* up to 0x80000000  */
 243     tlb->EPN = va & TARGET_PAGE_MASK;
 244     tlb->RPN = pa & TARGET_PAGE_MASK;
 245     tlb->PID = 0;
 246 }
 247
 248 static void main_cpu_reset(void *opaque)
 249 {
 250     PowerPCCPU *cpu = opaque;
 251     CPUPPCState *env = &cpu->env;
 252     struct boot_info *bi = env->load_info;
 253
 254     cpu_reset(CPU(cpu));
 255
 256     /* either we have a kernel to boot or we jump to U-Boot */
 257     if (bi->entry != UBOOT_ENTRY) {
 258         env->gpr[1] = (16 * MiB) - 8;
 259         env->gpr[3] = FDT_ADDR;
 260         env->nip = bi->entry;
 261
 262         /* Create a mapping for the kernel.  */
 263         mmubooke_create_initial_mapping(env, 0, 0);
 264         env->gpr[6] = tswap32(EPAPR_MAGIC);
 265         env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */
 266
 267     } else {
 268         env->nip = UBOOT_ENTRY;
 269         mmubooke_create_initial_mapping_uboot(env);
 270     }
 271 }
 272
 273 static void sam460ex_init(MachineState *machine)
 274 {
 275     MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
 276     DeviceState *uic[4];
 277     int i;
 278     PCIBus *pci_bus;
 279     USBBus *usb_bus;
 280     PowerPCCPU *cpu;
 281     CPUPPCState *env;
 282     I2CBus *i2c;
 283     hwaddr entry = UBOOT_ENTRY;
 284     target_long initrd_size = 0;
 285     DeviceState *dev;
 286     SysBusDevice *sbdev;
 287     struct boot_info *boot_info;
 288     uint8_t *spd_data;
 289     int success;
 290
 291     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 292     env = &cpu->env;
 293     if (env->mmu_model != POWERPC_MMU_BOOKE) {
 294         error_report("Only MMU model BookE is supported by this machine.");
 295         exit(1);
 296     }
 297
 298     qemu_register_reset(main_cpu_reset, cpu);
 299     boot_info = g_malloc0(sizeof(*boot_info));
 300     env->load_info = boot_info;
 301
 302     ppc_booke_timers_init(cpu, CPU_FREQ, 0);
 303     ppc_dcr_init(env, NULL, NULL);
 304
 305     /* PLB arbitrer */
 306     dev = qdev_new(TYPE_PPC4xx_PLB);
 307     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
 308     object_unref(OBJECT(dev));
 309
 310     /* interrupt controllers */
 311     for (i = 0; i < ARRAY_SIZE(uic); i++) {
 312         /*
 313          * UICs 1, 2 and 3 are cascaded through UIC 0.
 314          * input_ints[n] is the interrupt number on UIC 0 which
 315          * the INT output of UIC n is connected to. The CINT output
 316          * of UIC n connects to input_ints[n] + 1.
 317          * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's
 318          * INT and CINT outputs are connected to the CPU.
 319          */
 320         const int input_ints[] = { -1, 30, 10, 16 };
 321
 322         uic[i] = qdev_new(TYPE_PPC_UIC);
 323         qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10);
 324         ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal);
 325         object_unref(OBJECT(uic[i]));
 326
 327         sbdev = SYS_BUS_DEVICE(uic[i]);
 328         if (i == 0) {
 329             sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT,
 330                              qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
 331             sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT,
 332                              qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
 333         } else {
 334             sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT,
 335                                qdev_get_gpio_in(uic[0], input_ints[i]));
 336             sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT,
 337                                qdev_get_gpio_in(uic[0], input_ints[i] + 1));
 338         }
 339     }
 340
 341     /* SDRAM controller */
 342     /* The SoC could also handle 4 GiB but firmware does not work with that. */
 343     if (machine->ram_size > 2 * GiB) {
 344         error_report("Memory over 2 GiB is not supported");
 345         exit(1);
 346     }
 347     /* Firmware needs at least 64 MiB */
 348     if (machine->ram_size < 64 * MiB) {
 349         error_report("Memory below 64 MiB is not supported");
 350         exit(1);
 351     }
 352     dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2);
 353     object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
 354                              &error_abort);
 355     /*
 356      * Put all RAM on first bank because board has one slot
 357      * and firmware only checks that
 358      */
 359     object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort);
 360     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
 361     object_unref(OBJECT(dev));
 362     /* FIXME: does 460EX have ECC interrupts? */
 363     /* Enable SDRAM memory regions as we may boot without firmware */
 364     ppc4xx_sdram_ddr2_enable(PPC4xx_SDRAM_DDR2(dev));
 365
 366     /* IIC controllers and devices */
 367     dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
 368                                qdev_get_gpio_in(uic[0], 2));
 369     i2c = PPC4xx_I2C(dev)->bus;
 370     /* SPD EEPROM on RAM module */
 371     spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2,
 372                                  machine->ram_size);
 373     spd_data[20] = 4; /* SO-DIMM module */
 374     smbus_eeprom_init_one(i2c, 0x50, spd_data);
 375     /* RTC */
 376     i2c_slave_create_simple(i2c, "m41t80", 0x68);
 377
 378     dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800,
 379                                qdev_get_gpio_in(uic[0], 3));
 380
 381     /* External bus controller */
 382     dev = qdev_new(TYPE_PPC4xx_EBC);
 383     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
 384     object_unref(OBJECT(dev));
 385
 386     /* CPR */
 387     ppc4xx_cpr_init(env);
 388
 389     /* PLB to AHB bridge */
 390     ppc4xx_ahb_init(env);
 391
 392     /* System DCRs */
 393     ppc4xx_sdr_init(env);
 394
 395     /* MAL */
 396     dev = qdev_new(TYPE_PPC4xx_MAL);
 397     qdev_prop_set_uint8(dev, "txc-num", 4);
 398     qdev_prop_set_uint8(dev, "rxc-num", 16);
 399     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
 400     object_unref(OBJECT(dev));
 401     sbdev = SYS_BUS_DEVICE(dev);
 402     for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) {
 403         sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i));
 404     }
 405
 406     /* DMA */
 407     ppc4xx_dma_init(env, 0x200);
 408
 409     /* 256K of L2 cache as memory */
 410     ppc4xx_l2sram_init(env);
 411     /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
 412     memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB,
 413                            &error_abort);
 414     memory_region_add_subregion(get_system_memory(), 0x400000000LL,
 415                                 l2cache_ram);
 416
 417     /* USB */
 418     sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400,
 419                          qdev_get_gpio_in(uic[2], 29));
 420     dev = qdev_new("sysbus-ohci");
 421     qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
 422     qdev_prop_set_uint32(dev, "num-ports", 6);
 423     sbdev = SYS_BUS_DEVICE(dev);
 424     sysbus_realize_and_unref(sbdev, &error_fatal);
 425     sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
 426     sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30));
 427     usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS,
 428                                                       &error_abort));
 429     usb_create_simple(usb_bus, "usb-kbd");
 430     usb_create_simple(usb_bus, "usb-mouse");
 431
 432     /* PCIe buses */
 433     dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
 434     qdev_prop_set_int32(dev, "busnum", 0);
 435     qdev_prop_set_int32(dev, "dcrn-base", PCIE0_DCRN_BASE);
 436     object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
 437     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 438
 439     dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
 440     qdev_prop_set_int32(dev, "busnum", 1);
 441     qdev_prop_set_int32(dev, "dcrn-base", PCIE1_DCRN_BASE);
 442     object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
 443     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 444
 445     /* PCI bus */
 446     /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */
 447     dev = sysbus_create_simple(TYPE_PPC440_PCIX_HOST, 0xc0ec00000,
 448                                qdev_get_gpio_in(uic[1], 0));
 449     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, 0xc08000000);
 450     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
 451
 452     /* PCI devices */
 453     pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
 454     /*
 455      * SoC has a single SATA port but we don't emulate that
 456      * However, firmware and usual clients have driver for SiI311x
 457      * PCI SATA card so add one for convenience by default
 458      */
 459     if (defaults_enabled()) {
 460         PCIIDEState *s = PCI_IDE(pci_create_simple(pci_bus, -1, "sii3112"));
 461         DriveInfo *di;
 462
 463         di = drive_get_by_index(IF_IDE, 0);
 464         if (di) {
 465             ide_bus_create_drive(&s->bus[0], 0, di);
 466         }
 467         /* Use index 2 only if 1 does not exist, this allows -cdrom */
 468         di = drive_get_by_index(IF_IDE, 1) ?: drive_get_by_index(IF_IDE, 2);
 469         if (di) {
 470             ide_bus_create_drive(&s->bus[1], 0, di);
 471         }
 472     }
 473
 474     /* SoC has 4 UARTs but board has only one wired and two described in fdt */
 475     if (serial_hd(0) != NULL) {
 476         serial_mm_init(get_system_memory(), 0x4ef600300, 0,
 477                        qdev_get_gpio_in(uic[1], 1),
 478                        PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
 479                        DEVICE_BIG_ENDIAN);
 480     }
 481     if (serial_hd(1) != NULL) {
 482         serial_mm_init(get_system_memory(), 0x4ef600400, 0,
 483                        qdev_get_gpio_in(uic[0], 1),
 484                        PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
 485                        DEVICE_BIG_ENDIAN);
 486     }
 487
 488     /* Load U-Boot image. */
 489     if (!machine->kernel_filename) {
 490         success = sam460ex_load_uboot();
 491         if (success < 0) {
 492             error_report("could not load firmware");
 493             exit(1);
 494         }
 495     }
 496
 497     /* Load kernel. */
 498     if (machine->kernel_filename) {
 499         hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
 500         success = load_uimage(machine->kernel_filename, &entry, &loadaddr,
 501                               NULL, NULL, NULL);
 502         if (success < 0) {
 503             uint64_t elf_entry;
 504
 505             success = load_elf(machine->kernel_filename, NULL, NULL, NULL,
 506                                &elf_entry, NULL, NULL, NULL,
 507                                1, PPC_ELF_MACHINE, 0, 0);
 508             entry = elf_entry;
 509         }
 510         /* XXX try again as binary */
 511         if (success < 0) {
 512             error_report("could not load kernel '%s'",
 513                     machine->kernel_filename);
 514             exit(1);
 515         }
 516     }
 517
 518     /* Load initrd. */
 519     if (machine->initrd_filename) {
 520         initrd_size = load_image_targphys(machine->initrd_filename,
 521                                           RAMDISK_ADDR,
 522                                           machine->ram_size - RAMDISK_ADDR);
 523         if (initrd_size < 0) {
 524             error_report("could not load ram disk '%s' at %x",
 525                     machine->initrd_filename, RAMDISK_ADDR);
 526             exit(1);
 527         }
 528     }
 529
 530     /* If we're loading a kernel directly, we must load the device tree too. */
 531     if (machine->kernel_filename) {
 532         int dt_size;
 533
 534         dt_size = sam460ex_load_device_tree(machine, FDT_ADDR,
 535                                             RAMDISK_ADDR, initrd_size);
 536
 537         boot_info->dt_base = FDT_ADDR;
 538         boot_info->dt_size = dt_size;
 539     }
 540
 541     boot_info->entry = entry;
 542 }
 543
 544 static void sam460ex_machine_init(MachineClass *mc)
 545 {
 546     mc->desc = "aCube Sam460ex";
 547     mc->init = sam460ex_init;
 548     mc->block_default_type = IF_IDE;
 549     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
 550     mc->default_ram_size = 512 * MiB;
 551     mc->default_ram_id = "ppc4xx.sdram";
 552 }
 553
 554 DEFINE_MACHINE("sam460ex", sam460ex_machine_init)