2 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
4 * Copyright (c) 2003-2005, 2007, 2017 Jocelyn Mayer
5 * Copyright (c) 2013 Hervé Poussineau
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
28 #include "hw/qdev-properties.h"
29 #include "hw/rtc/m48t59.h"
30 #include "qemu/timer.h"
31 #include "sysemu/runstate.h"
32 #include "sysemu/rtc.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/sysbus.h"
35 #include "qapi/error.h"
37 #include "qemu/module.h"
39 #include "sysemu/watchdog.h"
41 #include "m48t59-internal.h"
42 #include "migration/vmstate.h"
43 #include "qom/object.h"
45 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
46 typedef struct M48txxSysBusDeviceClass M48txxSysBusDeviceClass
;
47 typedef struct M48txxSysBusState M48txxSysBusState
;
48 DECLARE_OBJ_CHECKERS(M48txxSysBusState
, M48txxSysBusDeviceClass
,
49 M48TXX_SYS_BUS
, TYPE_M48TXX_SYS_BUS
)
53 * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
54 * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
55 * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
58 struct M48txxSysBusState
{
59 SysBusDevice parent_obj
;
64 struct M48txxSysBusDeviceClass
{
65 SysBusDeviceClass parent_class
;
69 static M48txxInfo m48txx_sysbus_info
[] = {
71 .bus_name
= "sysbus-m48t02",
75 .bus_name
= "sysbus-m48t08",
79 .bus_name
= "sysbus-m48t59",
86 /* Fake timer functions */
88 /* Alarm management */
89 static void alarm_cb (void *opaque
)
93 M48t59State
*NVRAM
= opaque
;
95 qemu_set_irq(NVRAM
->IRQ
, 1);
96 if ((NVRAM
->buffer
[0x1FF5] & 0x80) == 0 &&
97 (NVRAM
->buffer
[0x1FF4] & 0x80) == 0 &&
98 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
99 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
100 /* Repeat once a month */
101 qemu_get_timedate(&tm
, NVRAM
->time_offset
);
103 if (tm
.tm_mon
== 13) {
107 next_time
= qemu_timedate_diff(&tm
) - NVRAM
->time_offset
;
108 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
109 (NVRAM
->buffer
[0x1FF4] & 0x80) == 0 &&
110 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
111 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
112 /* Repeat once a day */
113 next_time
= 24 * 60 * 60;
114 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
115 (NVRAM
->buffer
[0x1FF4] & 0x80) != 0 &&
116 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
117 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
118 /* Repeat once an hour */
120 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
121 (NVRAM
->buffer
[0x1FF4] & 0x80) != 0 &&
122 (NVRAM
->buffer
[0x1FF3] & 0x80) != 0 &&
123 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
124 /* Repeat once a minute */
127 /* Repeat once a second */
130 timer_mod(NVRAM
->alrm_timer
, qemu_clock_get_ns(rtc_clock
) +
132 qemu_set_irq(NVRAM
->IRQ
, 0);
135 static void set_alarm(M48t59State
*NVRAM
)
138 if (NVRAM
->alrm_timer
!= NULL
) {
139 timer_del(NVRAM
->alrm_timer
);
140 diff
= qemu_timedate_diff(&NVRAM
->alarm
) - NVRAM
->time_offset
;
142 timer_mod(NVRAM
->alrm_timer
, diff
* 1000);
146 /* RTC management helpers */
147 static inline void get_time(M48t59State
*NVRAM
, struct tm
*tm
)
149 qemu_get_timedate(tm
, NVRAM
->time_offset
);
152 static void set_time(M48t59State
*NVRAM
, struct tm
*tm
)
154 NVRAM
->time_offset
= qemu_timedate_diff(tm
);
158 /* Watchdog management */
159 static void watchdog_cb (void *opaque
)
161 M48t59State
*NVRAM
= opaque
;
163 NVRAM
->buffer
[0x1FF0] |= 0x80;
164 if (NVRAM
->buffer
[0x1FF7] & 0x80) {
165 NVRAM
->buffer
[0x1FF7] = 0x00;
166 NVRAM
->buffer
[0x1FFC] &= ~0x40;
167 watchdog_perform_action();
169 qemu_set_irq(NVRAM
->IRQ
, 1);
170 qemu_set_irq(NVRAM
->IRQ
, 0);
174 static void set_up_watchdog(M48t59State
*NVRAM
, uint8_t value
)
176 uint64_t interval
; /* in 1/16 seconds */
178 NVRAM
->buffer
[0x1FF0] &= ~0x80;
179 if (NVRAM
->wd_timer
!= NULL
) {
180 timer_del(NVRAM
->wd_timer
);
182 interval
= (1 << (2 * (value
& 0x03))) * ((value
>> 2) & 0x1F);
183 timer_mod(NVRAM
->wd_timer
, ((uint64_t)time(NULL
) * 1000) +
184 ((interval
* 1000) >> 4));
189 /* Direct access to NVRAM */
190 void m48t59_write(M48t59State
*NVRAM
, uint32_t addr
, uint32_t val
)
195 trace_m48txx_nvram_mem_write(addr
, val
);
197 /* check for NVRAM access */
198 if ((NVRAM
->model
== 2 && addr
< 0x7f8) ||
199 (NVRAM
->model
== 8 && addr
< 0x1ff8) ||
200 (NVRAM
->model
== 59 && addr
< 0x1ff0)) {
207 /* flags register : read-only */
214 tmp
= from_bcd(val
& 0x7F);
215 if (tmp
>= 0 && tmp
<= 59) {
216 NVRAM
->alarm
.tm_sec
= tmp
;
217 NVRAM
->buffer
[0x1FF2] = val
;
223 tmp
= from_bcd(val
& 0x7F);
224 if (tmp
>= 0 && tmp
<= 59) {
225 NVRAM
->alarm
.tm_min
= tmp
;
226 NVRAM
->buffer
[0x1FF3] = val
;
232 tmp
= from_bcd(val
& 0x3F);
233 if (tmp
>= 0 && tmp
<= 23) {
234 NVRAM
->alarm
.tm_hour
= tmp
;
235 NVRAM
->buffer
[0x1FF4] = val
;
241 tmp
= from_bcd(val
& 0x3F);
243 NVRAM
->alarm
.tm_mday
= tmp
;
244 NVRAM
->buffer
[0x1FF5] = val
;
250 NVRAM
->buffer
[0x1FF6] = val
;
254 NVRAM
->buffer
[0x1FF7] = val
;
255 set_up_watchdog(NVRAM
, val
);
260 NVRAM
->buffer
[addr
] = (val
& ~0xA0) | 0x90;
265 tmp
= from_bcd(val
& 0x7F);
266 if (tmp
>= 0 && tmp
<= 59) {
267 get_time(NVRAM
, &tm
);
269 set_time(NVRAM
, &tm
);
271 if ((val
& 0x80) ^ (NVRAM
->buffer
[addr
] & 0x80)) {
273 NVRAM
->stop_time
= time(NULL
);
275 NVRAM
->time_offset
+= NVRAM
->stop_time
- time(NULL
);
276 NVRAM
->stop_time
= 0;
279 NVRAM
->buffer
[addr
] = val
& 0x80;
284 tmp
= from_bcd(val
& 0x7F);
285 if (tmp
>= 0 && tmp
<= 59) {
286 get_time(NVRAM
, &tm
);
288 set_time(NVRAM
, &tm
);
294 tmp
= from_bcd(val
& 0x3F);
295 if (tmp
>= 0 && tmp
<= 23) {
296 get_time(NVRAM
, &tm
);
298 set_time(NVRAM
, &tm
);
303 /* day of the week / century */
304 tmp
= from_bcd(val
& 0x07);
305 get_time(NVRAM
, &tm
);
307 set_time(NVRAM
, &tm
);
308 NVRAM
->buffer
[addr
] = val
& 0x40;
313 tmp
= from_bcd(val
& 0x3F);
315 get_time(NVRAM
, &tm
);
317 set_time(NVRAM
, &tm
);
323 tmp
= from_bcd(val
& 0x1F);
324 if (tmp
>= 1 && tmp
<= 12) {
325 get_time(NVRAM
, &tm
);
327 set_time(NVRAM
, &tm
);
334 if (tmp
>= 0 && tmp
<= 99) {
335 get_time(NVRAM
, &tm
);
336 tm
.tm_year
= from_bcd(val
) + NVRAM
->base_year
- 1900;
337 set_time(NVRAM
, &tm
);
341 /* Check lock registers state */
342 if (addr
>= 0x20 && addr
<= 0x2F && (NVRAM
->lock
& 1))
344 if (addr
>= 0x30 && addr
<= 0x3F && (NVRAM
->lock
& 2))
347 if (addr
< NVRAM
->size
) {
348 NVRAM
->buffer
[addr
] = val
& 0xFF;
354 uint32_t m48t59_read(M48t59State
*NVRAM
, uint32_t addr
)
357 uint32_t retval
= 0xFF;
359 /* check for NVRAM access */
360 if ((NVRAM
->model
== 2 && addr
< 0x078f) ||
361 (NVRAM
->model
== 8 && addr
< 0x1ff8) ||
362 (NVRAM
->model
== 59 && addr
< 0x1ff0)) {
391 /* A read resets the watchdog */
392 set_up_watchdog(NVRAM
, NVRAM
->buffer
[0x1FF7]);
401 get_time(NVRAM
, &tm
);
402 retval
= (NVRAM
->buffer
[addr
] & 0x80) | to_bcd(tm
.tm_sec
);
407 get_time(NVRAM
, &tm
);
408 retval
= to_bcd(tm
.tm_min
);
413 get_time(NVRAM
, &tm
);
414 retval
= to_bcd(tm
.tm_hour
);
418 /* day of the week / century */
419 get_time(NVRAM
, &tm
);
420 retval
= NVRAM
->buffer
[addr
] | tm
.tm_wday
;
425 get_time(NVRAM
, &tm
);
426 retval
= to_bcd(tm
.tm_mday
);
431 get_time(NVRAM
, &tm
);
432 retval
= to_bcd(tm
.tm_mon
+ 1);
437 get_time(NVRAM
, &tm
);
438 retval
= to_bcd((tm
.tm_year
+ 1900 - NVRAM
->base_year
) % 100);
441 /* Check lock registers state */
442 if (addr
>= 0x20 && addr
<= 0x2F && (NVRAM
->lock
& 1))
444 if (addr
>= 0x30 && addr
<= 0x3F && (NVRAM
->lock
& 2))
447 if (addr
< NVRAM
->size
) {
448 retval
= NVRAM
->buffer
[addr
];
452 trace_m48txx_nvram_mem_read(addr
, retval
);
457 /* IO access to NVRAM */
458 static void NVRAM_writeb(void *opaque
, hwaddr addr
, uint64_t val
,
461 M48t59State
*NVRAM
= opaque
;
463 trace_m48txx_nvram_io_write(addr
, val
);
466 NVRAM
->addr
&= ~0x00FF;
470 NVRAM
->addr
&= ~0xFF00;
471 NVRAM
->addr
|= val
<< 8;
474 m48t59_write(NVRAM
, NVRAM
->addr
, val
);
475 NVRAM
->addr
= 0x0000;
482 static uint64_t NVRAM_readb(void *opaque
, hwaddr addr
, unsigned size
)
484 M48t59State
*NVRAM
= opaque
;
489 retval
= m48t59_read(NVRAM
, NVRAM
->addr
);
495 trace_m48txx_nvram_io_read(addr
, retval
);
500 static uint64_t nvram_read(void *opaque
, hwaddr addr
, unsigned size
)
502 M48t59State
*NVRAM
= opaque
;
504 return m48t59_read(NVRAM
, addr
);
507 static void nvram_write(void *opaque
, hwaddr addr
, uint64_t value
,
510 M48t59State
*NVRAM
= opaque
;
512 return m48t59_write(NVRAM
, addr
, value
);
515 static const MemoryRegionOps nvram_ops
= {
517 .write
= nvram_write
,
518 .impl
.min_access_size
= 1,
519 .impl
.max_access_size
= 1,
520 .valid
.min_access_size
= 1,
521 .valid
.max_access_size
= 4,
522 .endianness
= DEVICE_BIG_ENDIAN
,
525 static const VMStateDescription vmstate_m48t59
= {
528 .minimum_version_id
= 1,
529 .fields
= (const VMStateField
[]) {
530 VMSTATE_UINT8(lock
, M48t59State
),
531 VMSTATE_UINT16(addr
, M48t59State
),
532 VMSTATE_VBUFFER_UINT32(buffer
, M48t59State
, 0, NULL
, size
),
533 VMSTATE_END_OF_LIST()
537 void m48t59_reset_common(M48t59State
*NVRAM
)
541 if (NVRAM
->alrm_timer
!= NULL
)
542 timer_del(NVRAM
->alrm_timer
);
544 if (NVRAM
->wd_timer
!= NULL
)
545 timer_del(NVRAM
->wd_timer
);
548 static void m48t59_reset_sysbus(DeviceState
*d
)
550 M48txxSysBusState
*sys
= M48TXX_SYS_BUS(d
);
551 M48t59State
*NVRAM
= &sys
->state
;
553 m48t59_reset_common(NVRAM
);
556 const MemoryRegionOps m48t59_io_ops
= {
558 .write
= NVRAM_writeb
,
560 .min_access_size
= 1,
561 .max_access_size
= 1,
563 .endianness
= DEVICE_LITTLE_ENDIAN
,
566 void m48t59_realize_common(M48t59State
*s
, Error
**errp
)
568 s
->buffer
= g_malloc0(s
->size
);
569 if (s
->model
== 59) {
570 s
->alrm_timer
= timer_new_ns(rtc_clock
, &alarm_cb
, s
);
571 s
->wd_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &watchdog_cb
, s
);
573 qemu_get_timedate(&s
->alarm
, 0);
576 static void m48t59_init1(Object
*obj
)
578 M48txxSysBusDeviceClass
*u
= M48TXX_SYS_BUS_GET_CLASS(obj
);
579 M48txxSysBusState
*d
= M48TXX_SYS_BUS(obj
);
580 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
581 M48t59State
*s
= &d
->state
;
583 s
->model
= u
->info
.model
;
584 s
->size
= u
->info
.size
;
585 sysbus_init_irq(dev
, &s
->IRQ
);
587 memory_region_init_io(&s
->iomem
, obj
, &nvram_ops
, s
, "m48t59.nvram",
589 memory_region_init_io(&d
->io
, obj
, &m48t59_io_ops
, s
, "m48t59", 4);
592 static void m48t59_realize(DeviceState
*dev
, Error
**errp
)
594 M48txxSysBusState
*d
= M48TXX_SYS_BUS(dev
);
595 M48t59State
*s
= &d
->state
;
596 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
598 sysbus_init_mmio(sbd
, &s
->iomem
);
599 sysbus_init_mmio(sbd
, &d
->io
);
600 m48t59_realize_common(s
, errp
);
603 static uint32_t m48txx_sysbus_read(Nvram
*obj
, uint32_t addr
)
605 M48txxSysBusState
*d
= M48TXX_SYS_BUS(obj
);
606 return m48t59_read(&d
->state
, addr
);
609 static void m48txx_sysbus_write(Nvram
*obj
, uint32_t addr
, uint32_t val
)
611 M48txxSysBusState
*d
= M48TXX_SYS_BUS(obj
);
612 m48t59_write(&d
->state
, addr
, val
);
615 static void m48txx_sysbus_toggle_lock(Nvram
*obj
, int lock
)
617 M48txxSysBusState
*d
= M48TXX_SYS_BUS(obj
);
618 m48t59_toggle_lock(&d
->state
, lock
);
621 static Property m48t59_sysbus_properties
[] = {
622 DEFINE_PROP_INT32("base-year", M48txxSysBusState
, state
.base_year
, 0),
623 DEFINE_PROP_END_OF_LIST(),
626 static void m48txx_sysbus_class_init(ObjectClass
*klass
, void *data
)
628 DeviceClass
*dc
= DEVICE_CLASS(klass
);
629 NvramClass
*nc
= NVRAM_CLASS(klass
);
631 dc
->realize
= m48t59_realize
;
632 device_class_set_legacy_reset(dc
, m48t59_reset_sysbus
);
633 device_class_set_props(dc
, m48t59_sysbus_properties
);
634 dc
->vmsd
= &vmstate_m48t59
;
635 nc
->read
= m48txx_sysbus_read
;
636 nc
->write
= m48txx_sysbus_write
;
637 nc
->toggle_lock
= m48txx_sysbus_toggle_lock
;
640 static void m48txx_sysbus_concrete_class_init(ObjectClass
*klass
, void *data
)
642 M48txxSysBusDeviceClass
*u
= M48TXX_SYS_BUS_CLASS(klass
);
643 M48txxInfo
*info
= data
;
648 static const TypeInfo nvram_info
= {
650 .parent
= TYPE_INTERFACE
,
651 .class_size
= sizeof(NvramClass
),
654 static const TypeInfo m48txx_sysbus_type_info
= {
655 .name
= TYPE_M48TXX_SYS_BUS
,
656 .parent
= TYPE_SYS_BUS_DEVICE
,
657 .instance_size
= sizeof(M48txxSysBusState
),
658 .instance_init
= m48t59_init1
,
660 .class_init
= m48txx_sysbus_class_init
,
661 .interfaces
= (InterfaceInfo
[]) {
667 static void m48t59_register_types(void)
669 TypeInfo sysbus_type_info
= {
670 .parent
= TYPE_M48TXX_SYS_BUS
,
671 .class_size
= sizeof(M48txxSysBusDeviceClass
),
672 .class_init
= m48txx_sysbus_concrete_class_init
,
676 type_register_static(&nvram_info
);
677 type_register_static(&m48txx_sysbus_type_info
);
679 for (i
= 0; i
< ARRAY_SIZE(m48txx_sysbus_info
); i
++) {
680 sysbus_type_info
.name
= m48txx_sysbus_info
[i
].bus_name
;
681 sysbus_type_info
.class_data
= &m48txx_sysbus_info
[i
];
682 type_register(&sysbus_type_info
);
686 type_init(m48t59_register_types
)