hw/timer/pxa2xx_timer.c

   1 /*
   2  * Intel XScale PXA255/270 OS Timers.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Copyright (c) 2006 Thorsten Zitterell
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/irq.h"
  12 #include "hw/qdev-properties.h"
  13 #include "qemu/timer.h"
  14 #include "sysemu/runstate.h"
  15 #include "hw/sysbus.h"
  16 #include "migration/vmstate.h"
  17 #include "qemu/log.h"
  18 #include "qemu/module.h"
  19 #include "qom/object.h"
  20 #include "sysemu/watchdog.h"
  21
  22 #define OSMR0   0x00
  23 #define OSMR1   0x04
  24 #define OSMR2   0x08
  25 #define OSMR3   0x0c
  26 #define OSMR4   0x80
  27 #define OSMR5   0x84
  28 #define OSMR6   0x88
  29 #define OSMR7   0x8c
  30 #define OSMR8   0x90
  31 #define OSMR9   0x94
  32 #define OSMR10  0x98
  33 #define OSMR11  0x9c
  34 #define OSCR    0x10    /* OS Timer Count */
  35 #define OSCR4   0x40
  36 #define OSCR5   0x44
  37 #define OSCR6   0x48
  38 #define OSCR7   0x4c
  39 #define OSCR8   0x50
  40 #define OSCR9   0x54
  41 #define OSCR10  0x58
  42 #define OSCR11  0x5c
  43 #define OSSR    0x14    /* Timer status register */
  44 #define OWER    0x18
  45 #define OIER    0x1c    /* Interrupt enable register  3-0 to E3-E0 */
  46 #define OMCR4   0xc0    /* OS Match Control registers */
  47 #define OMCR5   0xc4
  48 #define OMCR6   0xc8
  49 #define OMCR7   0xcc
  50 #define OMCR8   0xd0
  51 #define OMCR9   0xd4
  52 #define OMCR10  0xd8
  53 #define OMCR11  0xdc
  54 #define OSNR    0x20
  55
  56 #define PXA25X_FREQ     3686400 /* 3.6864 MHz */
  57
  58 static int pxa2xx_timer4_freq[8] = {
  59     [0] = 0,
  60     [1] = 32768,
  61     [2] = 1000,
  62     [3] = 1,
  63     [4] = 1000000,
  64     /* [5] is the "Externally supplied clock".  Assign if necessary.  */
  65     [5 ... 7] = 0,
  66 };
  67
  68 #define TYPE_PXA2XX_TIMER "pxa2xx-timer"
  69 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxTimerInfo, PXA2XX_TIMER)
  70
  71
  72 typedef struct {
  73     uint32_t value;
  74     qemu_irq irq;
  75     QEMUTimer *qtimer;
  76     int num;
  77     PXA2xxTimerInfo *info;
  78 } PXA2xxTimer0;
  79
  80 typedef struct {
  81     PXA2xxTimer0 tm;
  82     int32_t oldclock;
  83     int32_t clock;
  84     uint64_t lastload;
  85     uint32_t freq;
  86     uint32_t control;
  87 } PXA2xxTimer4;
  88
  89 struct PXA2xxTimerInfo {
  90     SysBusDevice parent_obj;
  91
  92     MemoryRegion iomem;
  93     uint32_t flags;
  94
  95     int32_t clock;
  96     int32_t oldclock;
  97     uint64_t lastload;
  98     uint32_t freq;
  99     PXA2xxTimer0 timer[4];
 100     uint32_t events;
 101     uint32_t irq_enabled;
 102     uint32_t reset3;
 103     uint32_t snapshot;
 104
 105     qemu_irq irq4;
 106     PXA2xxTimer4 tm4[8];
 107 };
 108
 109 #define PXA2XX_TIMER_HAVE_TM4   0
 110
 111 static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
 112 {
 113     return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
 114 }
 115
 116 static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
 117 {
 118     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 119     int i;
 120     uint32_t now_vm;
 121     uint64_t new_qemu;
 122
 123     now_vm = s->clock +
 124             muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND);
 125
 126     for (i = 0; i < 4; i ++) {
 127         new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
 128                         NANOSECONDS_PER_SECOND, s->freq);
 129         timer_mod(s->timer[i].qtimer, new_qemu);
 130     }
 131 }
 132
 133 static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
 134 {
 135     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 136     uint32_t now_vm;
 137     uint64_t new_qemu;
 138     static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
 139     int counter;
 140
 141     assert(n < ARRAY_SIZE(counters));
 142     if (s->tm4[n].control & (1 << 7))
 143         counter = n;
 144     else
 145         counter = counters[n];
 146
 147     if (!s->tm4[counter].freq) {
 148         timer_del(s->tm4[n].tm.qtimer);
 149         return;
 150     }
 151
 152     now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
 153                     s->tm4[counter].lastload,
 154                     s->tm4[counter].freq, NANOSECONDS_PER_SECOND);
 155
 156     new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
 157                     NANOSECONDS_PER_SECOND, s->tm4[counter].freq);
 158     timer_mod(s->tm4[n].tm.qtimer, new_qemu);
 159 }
 160
 161 static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
 162                                   unsigned size)
 163 {
 164     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 165     int tm = 0;
 166
 167     switch (offset) {
 168     case OSMR3:  tm ++;
 169         /* fall through */
 170     case OSMR2:  tm ++;
 171         /* fall through */
 172     case OSMR1:  tm ++;
 173         /* fall through */
 174     case OSMR0:
 175         return s->timer[tm].value;
 176     case OSMR11: tm ++;
 177         /* fall through */
 178     case OSMR10: tm ++;
 179         /* fall through */
 180     case OSMR9:  tm ++;
 181         /* fall through */
 182     case OSMR8:  tm ++;
 183         /* fall through */
 184     case OSMR7:  tm ++;
 185         /* fall through */
 186     case OSMR6:  tm ++;
 187         /* fall through */
 188     case OSMR5:  tm ++;
 189         /* fall through */
 190     case OSMR4:
 191         if (!pxa2xx_timer_has_tm4(s))
 192             goto badreg;
 193         return s->tm4[tm].tm.value;
 194     case OSCR:
 195         return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 196                         s->lastload, s->freq, NANOSECONDS_PER_SECOND);
 197     case OSCR11: tm ++;
 198         /* fall through */
 199     case OSCR10: tm ++;
 200         /* fall through */
 201     case OSCR9:  tm ++;
 202         /* fall through */
 203     case OSCR8:  tm ++;
 204         /* fall through */
 205     case OSCR7:  tm ++;
 206         /* fall through */
 207     case OSCR6:  tm ++;
 208         /* fall through */
 209     case OSCR5:  tm ++;
 210         /* fall through */
 211     case OSCR4:
 212         if (!pxa2xx_timer_has_tm4(s))
 213             goto badreg;
 214
 215         if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
 216             if (s->tm4[tm - 1].freq)
 217                 s->snapshot = s->tm4[tm - 1].clock + muldiv64(
 218                                 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 219                                 s->tm4[tm - 1].lastload,
 220                                 s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
 221             else
 222                 s->snapshot = s->tm4[tm - 1].clock;
 223         }
 224
 225         if (!s->tm4[tm].freq)
 226             return s->tm4[tm].clock;
 227         return s->tm4[tm].clock +
 228             muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 229                      s->tm4[tm].lastload, s->tm4[tm].freq,
 230                      NANOSECONDS_PER_SECOND);
 231     case OIER:
 232         return s->irq_enabled;
 233     case OSSR:  /* Status register */
 234         return s->events;
 235     case OWER:
 236         return s->reset3;
 237     case OMCR11: tm ++;
 238         /* fall through */
 239     case OMCR10: tm ++;
 240         /* fall through */
 241     case OMCR9:  tm ++;
 242         /* fall through */
 243     case OMCR8:  tm ++;
 244         /* fall through */
 245     case OMCR7:  tm ++;
 246         /* fall through */
 247     case OMCR6:  tm ++;
 248         /* fall through */
 249     case OMCR5:  tm ++;
 250         /* fall through */
 251     case OMCR4:
 252         if (!pxa2xx_timer_has_tm4(s))
 253             goto badreg;
 254         return s->tm4[tm].control;
 255     case OSNR:
 256         return s->snapshot;
 257     default:
 258         qemu_log_mask(LOG_UNIMP,
 259                       "%s: unknown register 0x%02" HWADDR_PRIx "\n",
 260                       __func__, offset);
 261         break;
 262     badreg:
 263         qemu_log_mask(LOG_GUEST_ERROR,
 264                       "%s: incorrect register 0x%02" HWADDR_PRIx "\n",
 265                       __func__, offset);
 266     }
 267
 268     return 0;
 269 }
 270
 271 static void pxa2xx_timer_write(void *opaque, hwaddr offset,
 272                                uint64_t value, unsigned size)
 273 {
 274     int i, tm = 0;
 275     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 276
 277     switch (offset) {
 278     case OSMR3:  tm ++;
 279         /* fall through */
 280     case OSMR2:  tm ++;
 281         /* fall through */
 282     case OSMR1:  tm ++;
 283         /* fall through */
 284     case OSMR0:
 285         s->timer[tm].value = value;
 286         pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 287         break;
 288     case OSMR11: tm ++;
 289         /* fall through */
 290     case OSMR10: tm ++;
 291         /* fall through */
 292     case OSMR9:  tm ++;
 293         /* fall through */
 294     case OSMR8:  tm ++;
 295         /* fall through */
 296     case OSMR7:  tm ++;
 297         /* fall through */
 298     case OSMR6:  tm ++;
 299         /* fall through */
 300     case OSMR5:  tm ++;
 301         /* fall through */
 302     case OSMR4:
 303         if (!pxa2xx_timer_has_tm4(s))
 304             goto badreg;
 305         s->tm4[tm].tm.value = value;
 306         pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
 307         break;
 308     case OSCR:
 309         s->oldclock = s->clock;
 310         s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 311         s->clock = value;
 312         pxa2xx_timer_update(s, s->lastload);
 313         break;
 314     case OSCR11: tm ++;
 315         /* fall through */
 316     case OSCR10: tm ++;
 317         /* fall through */
 318     case OSCR9:  tm ++;
 319         /* fall through */
 320     case OSCR8:  tm ++;
 321         /* fall through */
 322     case OSCR7:  tm ++;
 323         /* fall through */
 324     case OSCR6:  tm ++;
 325         /* fall through */
 326     case OSCR5:  tm ++;
 327         /* fall through */
 328     case OSCR4:
 329         if (!pxa2xx_timer_has_tm4(s))
 330             goto badreg;
 331         s->tm4[tm].oldclock = s->tm4[tm].clock;
 332         s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 333         s->tm4[tm].clock = value;
 334         pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
 335         break;
 336     case OIER:
 337         s->irq_enabled = value & 0xfff;
 338         break;
 339     case OSSR:  /* Status register */
 340         value &= s->events;
 341         s->events &= ~value;
 342         for (i = 0; i < 4; i ++, value >>= 1)
 343             if (value & 1)
 344                 qemu_irq_lower(s->timer[i].irq);
 345         if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
 346             qemu_irq_lower(s->irq4);
 347         break;
 348     case OWER:  /* XXX: Reset on OSMR3 match? */
 349         s->reset3 = value;
 350         break;
 351     case OMCR7:  tm ++;
 352         /* fall through */
 353     case OMCR6:  tm ++;
 354         /* fall through */
 355     case OMCR5:  tm ++;
 356         /* fall through */
 357     case OMCR4:
 358         if (!pxa2xx_timer_has_tm4(s))
 359             goto badreg;
 360         s->tm4[tm].control = value & 0x0ff;
 361         /* XXX Stop if running (shouldn't happen) */
 362         if ((value & (1 << 7)) || tm == 0)
 363             s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
 364         else {
 365             s->tm4[tm].freq = 0;
 366             pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
 367         }
 368         break;
 369     case OMCR11: tm ++;
 370         /* fall through */
 371     case OMCR10: tm ++;
 372         /* fall through */
 373     case OMCR9:  tm ++;
 374         /* fall through */
 375     case OMCR8:  tm += 4;
 376         if (!pxa2xx_timer_has_tm4(s))
 377             goto badreg;
 378         s->tm4[tm].control = value & 0x3ff;
 379         /* XXX Stop if running (shouldn't happen) */
 380         if ((value & (1 << 7)) || !(tm & 1))
 381             s->tm4[tm].freq =
 382                     pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
 383         else {
 384             s->tm4[tm].freq = 0;
 385             pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
 386         }
 387         break;
 388     default:
 389         qemu_log_mask(LOG_UNIMP,
 390                       "%s: unknown register 0x%02" HWADDR_PRIx " "
 391                       "(value 0x%08" PRIx64 ")\n",  __func__, offset, value);
 392         break;
 393     badreg:
 394         qemu_log_mask(LOG_GUEST_ERROR,
 395                       "%s: incorrect register 0x%02" HWADDR_PRIx " "
 396                       "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
 397     }
 398 }
 399
 400 static const MemoryRegionOps pxa2xx_timer_ops = {
 401     .read = pxa2xx_timer_read,
 402     .write = pxa2xx_timer_write,
 403     .endianness = DEVICE_NATIVE_ENDIAN,
 404 };
 405
 406 static void pxa2xx_timer_tick(void *opaque)
 407 {
 408     PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
 409     PXA2xxTimerInfo *i = t->info;
 410
 411     if (i->irq_enabled & (1 << t->num)) {
 412         i->events |= 1 << t->num;
 413         qemu_irq_raise(t->irq);
 414     }
 415
 416     if (t->num == 3)
 417         if (i->reset3 & 1) {
 418             i->reset3 = 0;
 419             watchdog_perform_action();
 420         }
 421 }
 422
 423 static void pxa2xx_timer_tick4(void *opaque)
 424 {
 425     PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
 426     PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;
 427
 428     pxa2xx_timer_tick(&t->tm);
 429     if (t->control & (1 << 3))
 430         t->clock = 0;
 431     if (t->control & (1 << 6))
 432         pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
 433     if (i->events & 0xff0)
 434         qemu_irq_raise(i->irq4);
 435 }
 436
 437 static int pxa25x_timer_post_load(void *opaque, int version_id)
 438 {
 439     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 440     int64_t now;
 441     int i;
 442
 443     now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 444     pxa2xx_timer_update(s, now);
 445
 446     if (pxa2xx_timer_has_tm4(s))
 447         for (i = 0; i < 8; i ++)
 448             pxa2xx_timer_update4(s, now, i);
 449
 450     return 0;
 451 }
 452
 453 static void pxa2xx_timer_init(Object *obj)
 454 {
 455     PXA2xxTimerInfo *s = PXA2XX_TIMER(obj);
 456     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 457
 458     s->irq_enabled = 0;
 459     s->oldclock = 0;
 460     s->clock = 0;
 461     s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 462     s->reset3 = 0;
 463
 464     memory_region_init_io(&s->iomem, obj, &pxa2xx_timer_ops, s,
 465                           "pxa2xx-timer", 0x00001000);
 466     sysbus_init_mmio(dev, &s->iomem);
 467 }
 468
 469 static void pxa2xx_timer_realize(DeviceState *dev, Error **errp)
 470 {
 471     PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
 472     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 473     int i;
 474
 475     for (i = 0; i < 4; i ++) {
 476         s->timer[i].value = 0;
 477         sysbus_init_irq(sbd, &s->timer[i].irq);
 478         s->timer[i].info = s;
 479         s->timer[i].num = i;
 480         s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 481                                           pxa2xx_timer_tick, &s->timer[i]);
 482     }
 483
 484     if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
 485         sysbus_init_irq(sbd, &s->irq4);
 486
 487         for (i = 0; i < 8; i ++) {
 488             s->tm4[i].tm.value = 0;
 489             s->tm4[i].tm.info = s;
 490             s->tm4[i].tm.num = i + 4;
 491             s->tm4[i].freq = 0;
 492             s->tm4[i].control = 0x0;
 493             s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 494                                                pxa2xx_timer_tick4, &s->tm4[i]);
 495         }
 496     }
 497 }
 498
 499 static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
 500     .name = "pxa2xx_timer0",
 501     .version_id = 2,
 502     .minimum_version_id = 2,
 503     .fields = (const VMStateField[]) {
 504         VMSTATE_UINT32(value, PXA2xxTimer0),
 505         VMSTATE_END_OF_LIST(),
 506     },
 507 };
 508
 509 static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
 510     .name = "pxa2xx_timer4",
 511     .version_id = 1,
 512     .minimum_version_id = 1,
 513     .fields = (const VMStateField[]) {
 514         VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
 515                         vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
 516         VMSTATE_INT32(oldclock, PXA2xxTimer4),
 517         VMSTATE_INT32(clock, PXA2xxTimer4),
 518         VMSTATE_UINT64(lastload, PXA2xxTimer4),
 519         VMSTATE_UINT32(freq, PXA2xxTimer4),
 520         VMSTATE_UINT32(control, PXA2xxTimer4),
 521         VMSTATE_END_OF_LIST(),
 522     },
 523 };
 524
 525 static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
 526 {
 527     return pxa2xx_timer_has_tm4(opaque);
 528 }
 529
 530 static const VMStateDescription vmstate_pxa2xx_timer_regs = {
 531     .name = "pxa2xx_timer",
 532     .version_id = 1,
 533     .minimum_version_id = 1,
 534     .post_load = pxa25x_timer_post_load,
 535     .fields = (const VMStateField[]) {
 536         VMSTATE_INT32(clock, PXA2xxTimerInfo),
 537         VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
 538         VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
 539         VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
 540                         vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
 541         VMSTATE_UINT32(events, PXA2xxTimerInfo),
 542         VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
 543         VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
 544         VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
 545         VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
 546                         pxa2xx_timer_has_tm4_test, 0,
 547                         vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
 548         VMSTATE_END_OF_LIST(),
 549     }
 550 };
 551
 552 static Property pxa25x_timer_dev_properties[] = {
 553     DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
 554     DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
 555                     PXA2XX_TIMER_HAVE_TM4, false),
 556     DEFINE_PROP_END_OF_LIST(),
 557 };
 558
 559 static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data)
 560 {
 561     DeviceClass *dc = DEVICE_CLASS(klass);
 562
 563     dc->desc = "PXA25x timer";
 564     device_class_set_props(dc, pxa25x_timer_dev_properties);
 565 }
 566
 567 static const TypeInfo pxa25x_timer_dev_info = {
 568     .name          = "pxa25x-timer",
 569     .parent        = TYPE_PXA2XX_TIMER,
 570     .instance_size = sizeof(PXA2xxTimerInfo),
 571     .class_init    = pxa25x_timer_dev_class_init,
 572 };
 573
 574 static void pxa2xx_timer_class_init(ObjectClass *oc, void *data)
 575 {
 576     DeviceClass *dc = DEVICE_CLASS(oc);
 577
 578     dc->realize  = pxa2xx_timer_realize;
 579     dc->vmsd = &vmstate_pxa2xx_timer_regs;
 580 }
 581
 582 static const TypeInfo pxa2xx_timer_type_info = {
 583     .name          = TYPE_PXA2XX_TIMER,
 584     .parent        = TYPE_SYS_BUS_DEVICE,
 585     .instance_size = sizeof(PXA2xxTimerInfo),
 586     .instance_init = pxa2xx_timer_init,
 587     .abstract      = true,
 588     .class_init    = pxa2xx_timer_class_init,
 589 };
 590
 591 static void pxa2xx_timer_register_types(void)
 592 {
 593     type_register_static(&pxa2xx_timer_type_info);
 594     type_register_static(&pxa25x_timer_dev_info);
 595 }
 596
 597 type_init(pxa2xx_timer_register_types)