include/hw/arm/npcm7xx.h

   1 /*
   2  * Nuvoton NPCM7xx SoC family.
   3  *
   4  * Copyright 2020 Google LLC
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  * for more details.
  15  */
  16 #ifndef NPCM7XX_H
  17 #define NPCM7XX_H
  18
  19 #include "hw/boards.h"
  20 #include "hw/adc/npcm7xx_adc.h"
  21 #include "hw/core/split-irq.h"
  22 #include "hw/cpu/a9mpcore.h"
  23 #include "hw/gpio/npcm7xx_gpio.h"
  24 #include "hw/i2c/npcm7xx_smbus.h"
  25 #include "hw/mem/npcm7xx_mc.h"
  26 #include "hw/misc/npcm7xx_clk.h"
  27 #include "hw/misc/npcm7xx_gcr.h"
  28 #include "hw/misc/npcm7xx_mft.h"
  29 #include "hw/misc/npcm7xx_pwm.h"
  30 #include "hw/misc/npcm7xx_rng.h"
  31 #include "hw/net/npcm7xx_emc.h"
  32 #include "hw/net/npcm_gmac.h"
  33 #include "hw/nvram/npcm7xx_otp.h"
  34 #include "hw/timer/npcm7xx_timer.h"
  35 #include "hw/ssi/npcm7xx_fiu.h"
  36 #include "hw/ssi/npcm_pspi.h"
  37 #include "hw/usb/hcd-ehci.h"
  38 #include "hw/usb/hcd-ohci.h"
  39 #include "target/arm/cpu.h"
  40 #include "hw/sd/npcm7xx_sdhci.h"
  41
  42 #define NPCM7XX_MAX_NUM_CPUS    (2)
  43
  44 /* The first half of the address space is reserved for DDR4 DRAM. */
  45 #define NPCM7XX_DRAM_BA         (0x00000000)
  46 #define NPCM7XX_DRAM_SZ         (2 * GiB)
  47
  48 /* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
  49 #define NPCM7XX_LOADER_START            (0x00000000)  /* Start of SDRAM */
  50 #define NPCM7XX_SMP_LOADER_START        (0xffff0000)  /* Boot ROM */
  51 #define NPCM7XX_SMP_BOOTREG_ADDR        (0xf080013c)  /* GCR.SCRPAD */
  52 #define NPCM7XX_GIC_CPU_IF_ADDR         (0xf03fe100)  /* GIC within A9 */
  53 #define NPCM7XX_BOARD_SETUP_ADDR        (0xffff1000)  /* Boot ROM */
  54
  55 #define NPCM7XX_NR_PWM_MODULES 2
  56
  57 struct NPCM7xxMachine {
  58     MachineState        parent;
  59     /*
  60      * PWM fan splitter. each splitter connects to one PWM output and
  61      * multiple MFT inputs.
  62      */
  63     SplitIRQ            fan_splitter[NPCM7XX_NR_PWM_MODULES *
  64                                      NPCM7XX_PWM_PER_MODULE];
  65 };
  66
  67 #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
  68 OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMachine, NPCM7XX_MACHINE)
  69
  70 typedef struct NPCM7xxMachineClass {
  71     MachineClass        parent;
  72
  73     const char          *soc_type;
  74 } NPCM7xxMachineClass;
  75
  76 #define NPCM7XX_MACHINE_CLASS(klass)                                    \
  77     OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE)
  78 #define NPCM7XX_MACHINE_GET_CLASS(obj)                                  \
  79     OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
  80
  81 struct NPCM7xxState {
  82     DeviceState         parent;
  83
  84     ARMCPU              cpu[NPCM7XX_MAX_NUM_CPUS];
  85     A9MPPrivState       a9mpcore;
  86
  87     MemoryRegion        sram;
  88     MemoryRegion        irom;
  89     MemoryRegion        ram3;
  90     MemoryRegion        *dram;
  91
  92     NPCM7xxGCRState     gcr;
  93     NPCM7xxCLKState     clk;
  94     NPCM7xxTimerCtrlState tim[3];
  95     NPCM7xxADCState     adc;
  96     NPCM7xxPWMState     pwm[NPCM7XX_NR_PWM_MODULES];
  97     NPCM7xxMFTState     mft[8];
  98     NPCM7xxOTPState     key_storage;
  99     NPCM7xxOTPState     fuse_array;
 100     NPCM7xxMCState      mc;
 101     NPCM7xxRNGState     rng;
 102     NPCM7xxGPIOState    gpio[8];
 103     NPCM7xxSMBusState   smbus[16];
 104     EHCISysBusState     ehci;
 105     OHCISysBusState     ohci;
 106     NPCM7xxFIUState     fiu[2];
 107     NPCM7xxEMCState     emc[2];
 108     NPCMGMACState       gmac[2];
 109     NPCM7xxSDHCIState   mmc;
 110     NPCMPSPIState       pspi[2];
 111 };
 112
 113 #define TYPE_NPCM7XX    "npcm7xx"
 114 OBJECT_DECLARE_TYPE(NPCM7xxState, NPCM7xxClass, NPCM7XX)
 115
 116 #define TYPE_NPCM730    "npcm730"
 117 #define TYPE_NPCM750    "npcm750"
 118
 119 typedef struct NPCM7xxClass {
 120     DeviceClass         parent;
 121
 122     /* Bitmask of modules that are permanently disabled on this chip. */
 123     uint32_t            disabled_modules;
 124     /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */
 125     uint32_t            num_cpus;
 126 } NPCM7xxClass;
 127
 128 /**
 129  * npcm7xx_load_kernel - Loads memory with everything needed to boot
 130  * @machine - The machine containing the SoC to be booted.
 131  * @soc - The SoC containing the CPU to be booted.
 132  *
 133  * This will set up the ARM boot info structure for the specific NPCM7xx
 134  * derivative and call arm_load_kernel() to set up loading of the kernel, etc.
 135  * into memory, if requested by the user.
 136  */
 137 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc);
 138
 139 #endif /* NPCM7XX_H */