include/hw/arm/omap.h

   1 /*
   2  * Texas Instruments OMAP processors.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef HW_ARM_OMAP_H
  21 #define HW_ARM_OMAP_H
  22
  23 #include "exec/memory.h"
  24 #include "target/arm/cpu-qom.h"
  25 #include "qemu/log.h"
  26 #include "qom/object.h"
  27
  28 # define OMAP_EMIFS_BASE        0x00000000
  29 # define OMAP_CS0_BASE          0x00000000
  30 # define OMAP_CS1_BASE          0x04000000
  31 # define OMAP_CS2_BASE          0x08000000
  32 # define OMAP_CS3_BASE          0x0c000000
  33 # define OMAP_EMIFF_BASE        0x10000000
  34 # define OMAP_IMIF_BASE         0x20000000
  35 # define OMAP_LOCALBUS_BASE     0x30000000
  36 # define OMAP_MPUI_BASE         0xe1000000
  37
  38 # define OMAP730_SRAM_SIZE      0x00032000
  39 # define OMAP15XX_SRAM_SIZE     0x00030000
  40 # define OMAP16XX_SRAM_SIZE     0x00004000
  41 # define OMAP1611_SRAM_SIZE     0x0003e800
  42 # define OMAP_CS0_SIZE          0x04000000
  43 # define OMAP_CS1_SIZE          0x04000000
  44 # define OMAP_CS2_SIZE          0x04000000
  45 # define OMAP_CS3_SIZE          0x04000000
  46
  47 /* omap_clk.c */
  48 struct omap_mpu_state_s;
  49 typedef struct clk *omap_clk;
  50 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
  51 void omap_clk_init(struct omap_mpu_state_s *mpu);
  52 void omap_clk_adduser(struct clk *clk, qemu_irq user);
  53 void omap_clk_get(omap_clk clk);
  54 void omap_clk_put(omap_clk clk);
  55 void omap_clk_onoff(omap_clk clk, int on);
  56 void omap_clk_canidle(omap_clk clk, int can);
  57 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
  58 int64_t omap_clk_getrate(omap_clk clk);
  59 void omap_clk_reparent(omap_clk clk, omap_clk parent);
  60
  61 /* omap_intc.c */
  62 #define TYPE_OMAP_INTC "omap-intc"
  63 typedef struct OMAPIntcState OMAPIntcState;
  64 DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC)
  65
  66
  67 /*
  68  * TODO: Ideally we should have a clock framework that
  69  * let us wire these clocks up with QOM properties or links.
  70  *
  71  * qdev should support a generic means of defining a 'port' with
  72  * an arbitrary interface for connecting two devices. Then we
  73  * could reframe the omap clock API in terms of clock ports,
  74  * and get some type safety. For now the best qdev provides is
  75  * passing an arbitrary pointer.
  76  * (It's not possible to pass in the string which is the clock
  77  * name, because this device does not have the necessary information
  78  * (ie the struct omap_mpu_state_s*) to do the clockname to pointer
  79  * translation.)
  80  */
  81 void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk);
  82 void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk);
  83
  84 /* omap_i2c.c */
  85 #define TYPE_OMAP_I2C "omap_i2c"
  86 OBJECT_DECLARE_SIMPLE_TYPE(OMAPI2CState, OMAP_I2C)
  87
  88
  89 /* TODO: clock framework (see above) */
  90 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk);
  91 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk);
  92
  93 /* omap_gpio.c */
  94 #define TYPE_OMAP1_GPIO "omap-gpio"
  95 typedef struct Omap1GpioState Omap1GpioState;
  96 DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO,
  97                          TYPE_OMAP1_GPIO)
  98
  99 /* TODO: clock framework (see above) */
 100 void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
 101
 102 /*
 103  * Common IRQ numbers for level 1 interrupt handler
 104  * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
 105  */
 106 # define OMAP_INT_CAMERA                1
 107 # define OMAP_INT_FIQ                   3
 108 # define OMAP_INT_RTDX                  6
 109 # define OMAP_INT_DSP_MMU_ABORT         7
 110 # define OMAP_INT_HOST                  8
 111 # define OMAP_INT_ABORT                 9
 112 # define OMAP_INT_BRIDGE_PRIV           13
 113 # define OMAP_INT_GPIO_BANK1            14
 114 # define OMAP_INT_UART3                 15
 115 # define OMAP_INT_TIMER3                16
 116 # define OMAP_INT_DMA_CH0_6             19
 117 # define OMAP_INT_DMA_CH1_7             20
 118 # define OMAP_INT_DMA_CH2_8             21
 119 # define OMAP_INT_DMA_CH3               22
 120 # define OMAP_INT_DMA_CH4               23
 121 # define OMAP_INT_DMA_CH5               24
 122 # define OMAP_INT_DMA_LCD               25
 123 # define OMAP_INT_TIMER1                26
 124 # define OMAP_INT_WD_TIMER              27
 125 # define OMAP_INT_BRIDGE_PUB            28
 126 # define OMAP_INT_TIMER2                30
 127 # define OMAP_INT_LCD_CTRL              31
 128
 129 /*
 130  * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
 131  */
 132 # define OMAP_INT_15XX_IH2_IRQ          0
 133 # define OMAP_INT_15XX_LB_MMU           17
 134 # define OMAP_INT_15XX_LOCAL_BUS        29
 135
 136 /*
 137  * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
 138  */
 139 # define OMAP_INT_1510_SPI_TX           4
 140 # define OMAP_INT_1510_SPI_RX           5
 141 # define OMAP_INT_1510_DSP_MAILBOX1     10
 142 # define OMAP_INT_1510_DSP_MAILBOX2     11
 143
 144 /*
 145  * OMAP-310 specific IRQ numbers for level 1 interrupt handler
 146  */
 147 # define OMAP_INT_310_McBSP2_TX         4
 148 # define OMAP_INT_310_McBSP2_RX         5
 149 # define OMAP_INT_310_HSB_MAILBOX1      12
 150 # define OMAP_INT_310_HSAB_MMU          18
 151
 152 /*
 153  * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
 154  */
 155 # define OMAP_INT_1610_IH2_IRQ          0
 156 # define OMAP_INT_1610_IH2_FIQ          2
 157 # define OMAP_INT_1610_McBSP2_TX        4
 158 # define OMAP_INT_1610_McBSP2_RX        5
 159 # define OMAP_INT_1610_DSP_MAILBOX1     10
 160 # define OMAP_INT_1610_DSP_MAILBOX2     11
 161 # define OMAP_INT_1610_LCD_LINE         12
 162 # define OMAP_INT_1610_GPTIMER1         17
 163 # define OMAP_INT_1610_GPTIMER2         18
 164 # define OMAP_INT_1610_SSR_FIFO_0       29
 165
 166 /*
 167  * OMAP-730 specific IRQ numbers for level 1 interrupt handler
 168  */
 169 # define OMAP_INT_730_IH2_FIQ           0
 170 # define OMAP_INT_730_IH2_IRQ           1
 171 # define OMAP_INT_730_USB_NON_ISO       2
 172 # define OMAP_INT_730_USB_ISO           3
 173 # define OMAP_INT_730_ICR               4
 174 # define OMAP_INT_730_EAC               5
 175 # define OMAP_INT_730_GPIO_BANK1        6
 176 # define OMAP_INT_730_GPIO_BANK2        7
 177 # define OMAP_INT_730_GPIO_BANK3        8
 178 # define OMAP_INT_730_McBSP2TX          10
 179 # define OMAP_INT_730_McBSP2RX          11
 180 # define OMAP_INT_730_McBSP2RX_OVF      12
 181 # define OMAP_INT_730_LCD_LINE          14
 182 # define OMAP_INT_730_GSM_PROTECT       15
 183 # define OMAP_INT_730_TIMER3            16
 184 # define OMAP_INT_730_GPIO_BANK5        17
 185 # define OMAP_INT_730_GPIO_BANK6        18
 186 # define OMAP_INT_730_SPGIO_WR          29
 187
 188 /*
 189  * Common IRQ numbers for level 2 interrupt handler
 190  */
 191 # define OMAP_INT_KEYBOARD              1
 192 # define OMAP_INT_uWireTX               2
 193 # define OMAP_INT_uWireRX               3
 194 # define OMAP_INT_I2C                   4
 195 # define OMAP_INT_MPUIO                 5
 196 # define OMAP_INT_USB_HHC_1             6
 197 # define OMAP_INT_McBSP3TX              10
 198 # define OMAP_INT_McBSP3RX              11
 199 # define OMAP_INT_McBSP1TX              12
 200 # define OMAP_INT_McBSP1RX              13
 201 # define OMAP_INT_UART1                 14
 202 # define OMAP_INT_UART2                 15
 203 # define OMAP_INT_USB_W2FC              20
 204 # define OMAP_INT_1WIRE                 21
 205 # define OMAP_INT_OS_TIMER              22
 206 # define OMAP_INT_OQN                   23
 207 # define OMAP_INT_GAUGE_32K             24
 208 # define OMAP_INT_RTC_TIMER             25
 209 # define OMAP_INT_RTC_ALARM             26
 210 # define OMAP_INT_DSP_MMU               28
 211
 212 /*
 213  * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
 214  */
 215 # define OMAP_INT_1510_BT_MCSI1TX       16
 216 # define OMAP_INT_1510_BT_MCSI1RX       17
 217 # define OMAP_INT_1510_SoSSI_MATCH      19
 218 # define OMAP_INT_1510_MEM_STICK        27
 219 # define OMAP_INT_1510_COM_SPI_RO       31
 220
 221 /*
 222  * OMAP-310 specific IRQ numbers for level 2 interrupt handler
 223  */
 224 # define OMAP_INT_310_FAC               0
 225 # define OMAP_INT_310_USB_HHC_2         7
 226 # define OMAP_INT_310_MCSI1_FE          16
 227 # define OMAP_INT_310_MCSI2_FE          17
 228 # define OMAP_INT_310_USB_W2FC_ISO      29
 229 # define OMAP_INT_310_USB_W2FC_NON_ISO  30
 230 # define OMAP_INT_310_McBSP2RX_OF       31
 231
 232 /*
 233  * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
 234  */
 235 # define OMAP_INT_1610_FAC              0
 236 # define OMAP_INT_1610_USB_HHC_2        7
 237 # define OMAP_INT_1610_USB_OTG          8
 238 # define OMAP_INT_1610_SoSSI            9
 239 # define OMAP_INT_1610_BT_MCSI1TX       16
 240 # define OMAP_INT_1610_BT_MCSI1RX       17
 241 # define OMAP_INT_1610_SoSSI_MATCH      19
 242 # define OMAP_INT_1610_MEM_STICK        27
 243 # define OMAP_INT_1610_McBSP2RX_OF      31
 244 # define OMAP_INT_1610_STI              32
 245 # define OMAP_INT_1610_STI_WAKEUP       33
 246 # define OMAP_INT_1610_GPTIMER3         34
 247 # define OMAP_INT_1610_GPTIMER4         35
 248 # define OMAP_INT_1610_GPTIMER5         36
 249 # define OMAP_INT_1610_GPTIMER6         37
 250 # define OMAP_INT_1610_GPTIMER7         38
 251 # define OMAP_INT_1610_GPTIMER8         39
 252 # define OMAP_INT_1610_GPIO_BANK2       40
 253 # define OMAP_INT_1610_GPIO_BANK3       41
 254 # define OMAP_INT_1610_MMC2             42
 255 # define OMAP_INT_1610_CF               43
 256 # define OMAP_INT_1610_WAKE_UP_REQ      46
 257 # define OMAP_INT_1610_GPIO_BANK4       48
 258 # define OMAP_INT_1610_SPI              49
 259 # define OMAP_INT_1610_DMA_CH6          53
 260 # define OMAP_INT_1610_DMA_CH7          54
 261 # define OMAP_INT_1610_DMA_CH8          55
 262 # define OMAP_INT_1610_DMA_CH9          56
 263 # define OMAP_INT_1610_DMA_CH10         57
 264 # define OMAP_INT_1610_DMA_CH11         58
 265 # define OMAP_INT_1610_DMA_CH12         59
 266 # define OMAP_INT_1610_DMA_CH13         60
 267 # define OMAP_INT_1610_DMA_CH14         61
 268 # define OMAP_INT_1610_DMA_CH15         62
 269 # define OMAP_INT_1610_NAND             63
 270
 271 /*
 272  * OMAP-730 specific IRQ numbers for level 2 interrupt handler
 273  */
 274 # define OMAP_INT_730_HW_ERRORS         0
 275 # define OMAP_INT_730_NFIQ_PWR_FAIL     1
 276 # define OMAP_INT_730_CFCD              2
 277 # define OMAP_INT_730_CFIREQ            3
 278 # define OMAP_INT_730_I2C               4
 279 # define OMAP_INT_730_PCC               5
 280 # define OMAP_INT_730_MPU_EXT_NIRQ      6
 281 # define OMAP_INT_730_SPI_100K_1        7
 282 # define OMAP_INT_730_SYREN_SPI         8
 283 # define OMAP_INT_730_VLYNQ             9
 284 # define OMAP_INT_730_GPIO_BANK4        10
 285 # define OMAP_INT_730_McBSP1TX          11
 286 # define OMAP_INT_730_McBSP1RX          12
 287 # define OMAP_INT_730_McBSP1RX_OF       13
 288 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
 289 # define OMAP_INT_730_UART_MODEM_1      15
 290 # define OMAP_INT_730_MCSI              16
 291 # define OMAP_INT_730_uWireTX           17
 292 # define OMAP_INT_730_uWireRX           18
 293 # define OMAP_INT_730_SMC_CD            19
 294 # define OMAP_INT_730_SMC_IREQ          20
 295 # define OMAP_INT_730_HDQ_1WIRE         21
 296 # define OMAP_INT_730_TIMER32K          22
 297 # define OMAP_INT_730_MMC_SDIO          23
 298 # define OMAP_INT_730_UPLD              24
 299 # define OMAP_INT_730_USB_HHC_1         27
 300 # define OMAP_INT_730_USB_HHC_2         28
 301 # define OMAP_INT_730_USB_GENI          29
 302 # define OMAP_INT_730_USB_OTG           30
 303 # define OMAP_INT_730_CAMERA_IF         31
 304 # define OMAP_INT_730_RNG               32
 305 # define OMAP_INT_730_DUAL_MODE_TIMER   33
 306 # define OMAP_INT_730_DBB_RF_EN         34
 307 # define OMAP_INT_730_MPUIO_KEYPAD      35
 308 # define OMAP_INT_730_SHA1_MD5          36
 309 # define OMAP_INT_730_SPI_100K_2        37
 310 # define OMAP_INT_730_RNG_IDLE          38
 311 # define OMAP_INT_730_MPUIO             39
 312 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
 313 # define OMAP_INT_730_LLPC_OE_FALLING   41
 314 # define OMAP_INT_730_LLPC_OE_RISING    42
 315 # define OMAP_INT_730_LLPC_VSYNC        43
 316 # define OMAP_INT_730_WAKE_UP_REQ       46
 317 # define OMAP_INT_730_DMA_CH6           53
 318 # define OMAP_INT_730_DMA_CH7           54
 319 # define OMAP_INT_730_DMA_CH8           55
 320 # define OMAP_INT_730_DMA_CH9           56
 321 # define OMAP_INT_730_DMA_CH10          57
 322 # define OMAP_INT_730_DMA_CH11          58
 323 # define OMAP_INT_730_DMA_CH12          59
 324 # define OMAP_INT_730_DMA_CH13          60
 325 # define OMAP_INT_730_DMA_CH14          61
 326 # define OMAP_INT_730_DMA_CH15          62
 327 # define OMAP_INT_730_NAND              63
 328
 329 /* omap_dma.c */
 330 enum omap_dma_model {
 331     omap_dma_3_0,
 332     omap_dma_3_1,
 333     omap_dma_3_2,
 334 };
 335
 336 struct soc_dma_s;
 337 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
 338                 MemoryRegion *sysmem,
 339                 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
 340                 enum omap_dma_model model);
 341 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
 342                 MemoryRegion *sysmem,
 343                 struct omap_mpu_state_s *mpu, int fifo,
 344                 int chans, omap_clk iclk, omap_clk fclk);
 345 void omap_dma_reset(struct soc_dma_s *s);
 346
 347 struct dma_irq_map {
 348     int ih;
 349     int intr;
 350 };
 351
 352 /* Only used in OMAP DMA 3.x gigacells */
 353 enum omap_dma_port {
 354     emiff = 0,
 355     emifs,
 356     imif,       /* omap16xx: ocp_t1 */
 357     tipb,
 358     local,      /* omap16xx: ocp_t2 */
 359     tipb_mpui,
 360     __omap_dma_port_last,
 361 };
 362
 363 typedef enum {
 364     constant = 0,
 365     post_incremented,
 366     single_index,
 367     double_index,
 368 } omap_dma_addressing_t;
 369
 370 /* Only used in OMAP DMA 3.x gigacells */
 371 struct omap_dma_lcd_channel_s {
 372     enum omap_dma_port src;
 373     hwaddr src_f1_top;
 374     hwaddr src_f1_bottom;
 375     hwaddr src_f2_top;
 376     hwaddr src_f2_bottom;
 377
 378     /* Used in OMAP DMA 3.2 gigacell */
 379     unsigned char brust_f1;
 380     unsigned char pack_f1;
 381     unsigned char data_type_f1;
 382     unsigned char brust_f2;
 383     unsigned char pack_f2;
 384     unsigned char data_type_f2;
 385     unsigned char end_prog;
 386     unsigned char repeat;
 387     unsigned char auto_init;
 388     unsigned char priority;
 389     unsigned char fs;
 390     unsigned char running;
 391     unsigned char bs;
 392     unsigned char omap_3_1_compatible_disable;
 393     unsigned char dst;
 394     unsigned char lch_type;
 395     int16_t element_index_f1;
 396     int16_t element_index_f2;
 397     int32_t frame_index_f1;
 398     int32_t frame_index_f2;
 399     uint16_t elements_f1;
 400     uint16_t frames_f1;
 401     uint16_t elements_f2;
 402     uint16_t frames_f2;
 403     omap_dma_addressing_t mode_f1;
 404     omap_dma_addressing_t mode_f2;
 405
 406     /* Destination port is fixed.  */
 407     int interrupts;
 408     int condition;
 409     int dual;
 410
 411     int current_frame;
 412     hwaddr phys_framebuffer[2];
 413     qemu_irq irq;
 414     struct omap_mpu_state_s *mpu;
 415 } *omap_dma_get_lcdch(struct soc_dma_s *s);
 416
 417 /*
 418  * DMA request numbers for OMAP1
 419  * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
 420  */
 421 # define OMAP_DMA_NO_DEVICE             0
 422 # define OMAP_DMA_MCSI1_TX              1
 423 # define OMAP_DMA_MCSI1_RX              2
 424 # define OMAP_DMA_I2C_RX                3
 425 # define OMAP_DMA_I2C_TX                4
 426 # define OMAP_DMA_EXT_NDMA_REQ0         5
 427 # define OMAP_DMA_EXT_NDMA_REQ1         6
 428 # define OMAP_DMA_UWIRE_TX              7
 429 # define OMAP_DMA_MCBSP1_TX             8
 430 # define OMAP_DMA_MCBSP1_RX             9
 431 # define OMAP_DMA_MCBSP3_TX             10
 432 # define OMAP_DMA_MCBSP3_RX             11
 433 # define OMAP_DMA_UART1_TX              12
 434 # define OMAP_DMA_UART1_RX              13
 435 # define OMAP_DMA_UART2_TX              14
 436 # define OMAP_DMA_UART2_RX              15
 437 # define OMAP_DMA_MCBSP2_TX             16
 438 # define OMAP_DMA_MCBSP2_RX             17
 439 # define OMAP_DMA_UART3_TX              18
 440 # define OMAP_DMA_UART3_RX              19
 441 # define OMAP_DMA_CAMERA_IF_RX          20
 442 # define OMAP_DMA_MMC_TX                21
 443 # define OMAP_DMA_MMC_RX                22
 444 # define OMAP_DMA_NAND                  23      /* Not in OMAP310 */
 445 # define OMAP_DMA_IRQ_LCD_LINE          24      /* Not in OMAP310 */
 446 # define OMAP_DMA_MEMORY_STICK          25      /* Not in OMAP310 */
 447 # define OMAP_DMA_USB_W2FC_RX0          26
 448 # define OMAP_DMA_USB_W2FC_RX1          27
 449 # define OMAP_DMA_USB_W2FC_RX2          28
 450 # define OMAP_DMA_USB_W2FC_TX0          29
 451 # define OMAP_DMA_USB_W2FC_TX1          30
 452 # define OMAP_DMA_USB_W2FC_TX2          31
 453
 454 /* These are only for 1610 */
 455 # define OMAP_DMA_CRYPTO_DES_IN         32
 456 # define OMAP_DMA_SPI_TX                33
 457 # define OMAP_DMA_SPI_RX                34
 458 # define OMAP_DMA_CRYPTO_HASH           35
 459 # define OMAP_DMA_CCP_ATTN              36
 460 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY    37
 461 # define OMAP_DMA_CMT_APE_TX_CHAN_0     38
 462 # define OMAP_DMA_CMT_APE_RV_CHAN_0     39
 463 # define OMAP_DMA_CMT_APE_TX_CHAN_1     40
 464 # define OMAP_DMA_CMT_APE_RV_CHAN_1     41
 465 # define OMAP_DMA_CMT_APE_TX_CHAN_2     42
 466 # define OMAP_DMA_CMT_APE_RV_CHAN_2     43
 467 # define OMAP_DMA_CMT_APE_TX_CHAN_3     44
 468 # define OMAP_DMA_CMT_APE_RV_CHAN_3     45
 469 # define OMAP_DMA_CMT_APE_TX_CHAN_4     46
 470 # define OMAP_DMA_CMT_APE_RV_CHAN_4     47
 471 # define OMAP_DMA_CMT_APE_TX_CHAN_5     48
 472 # define OMAP_DMA_CMT_APE_RV_CHAN_5     49
 473 # define OMAP_DMA_CMT_APE_TX_CHAN_6     50
 474 # define OMAP_DMA_CMT_APE_RV_CHAN_6     51
 475 # define OMAP_DMA_CMT_APE_TX_CHAN_7     52
 476 # define OMAP_DMA_CMT_APE_RV_CHAN_7     53
 477 # define OMAP_DMA_MMC2_TX               54
 478 # define OMAP_DMA_MMC2_RX               55
 479 # define OMAP_DMA_CRYPTO_DES_OUT        56
 480
 481 struct omap_uart_s;
 482 struct omap_uart_s *omap_uart_init(hwaddr base,
 483                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 484                 qemu_irq txdma, qemu_irq rxdma,
 485                 const char *label, Chardev *chr);
 486 void omap_uart_reset(struct omap_uart_s *s);
 487
 488 struct omap_mpuio_s;
 489 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
 490 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
 491 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
 492
 493 struct omap_uwire_s;
 494
 495 struct I2SCodec {
 496     void *opaque;
 497
 498     /* The CPU can call this if it is generating the clock signal on the
 499      * i2s port.  The CODEC can ignore it if it is set up as a clock
 500      * master and generates its own clock.  */
 501     void (*set_rate)(void *opaque, int in, int out);
 502
 503     void (*tx_swallow)(void *opaque);
 504     qemu_irq rx_swallow;
 505     qemu_irq tx_start;
 506
 507     int tx_rate;
 508     int cts;
 509     int rx_rate;
 510     int rts;
 511
 512     struct i2s_fifo_s {
 513         uint8_t *fifo;
 514         int len;
 515         int start;
 516         int size;
 517     } in, out;
 518 };
 519 struct omap_mcbsp_s;
 520 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
 521
 522 /* omap_lcdc.c */
 523 struct omap_lcd_panel_s;
 524 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
 525 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
 526                                         hwaddr base,
 527                                         qemu_irq irq,
 528                                         struct omap_dma_lcd_channel_s *dma,
 529                                         omap_clk clk);
 530
 531 /* omap_mmc.c */
 532 struct omap_mmc_s;
 533 struct omap_mmc_s *omap_mmc_init(hwaddr base,
 534                 MemoryRegion *sysmem,
 535                 BlockBackend *blk,
 536                 qemu_irq irq, qemu_irq dma[], omap_clk clk);
 537 void omap_mmc_reset(struct omap_mmc_s *s);
 538
 539 /* omap_i2c.c */
 540 I2CBus *omap_i2c_bus(DeviceState *omap_i2c);
 541
 542 # define cpu_is_omap310(cpu)            (cpu->mpu_model == omap310)
 543 # define cpu_is_omap1510(cpu)           (cpu->mpu_model == omap1510)
 544 # define cpu_is_omap1610(cpu)           (cpu->mpu_model == omap1610)
 545 # define cpu_is_omap1710(cpu)           (cpu->mpu_model == omap1710)
 546
 547 # define cpu_is_omap15xx(cpu)           \
 548         (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
 549 # define cpu_is_omap16xx(cpu)           \
 550         (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
 551
 552 struct omap_mpu_state_s {
 553     enum omap_mpu_model {
 554         omap310,
 555         omap1510,
 556         omap1610,
 557         omap1710,
 558     } mpu_model;
 559
 560     ARMCPU *cpu;
 561
 562     qemu_irq *drq;
 563
 564     qemu_irq wakeup;
 565
 566     MemoryRegion ulpd_pm_iomem;
 567     MemoryRegion pin_cfg_iomem;
 568     MemoryRegion id_iomem;
 569     MemoryRegion id_iomem_e18;
 570     MemoryRegion id_iomem_ed4;
 571     MemoryRegion id_iomem_e20;
 572     MemoryRegion mpui_iomem;
 573     MemoryRegion tcmi_iomem;
 574     MemoryRegion clkm_iomem;
 575     MemoryRegion clkdsp_iomem;
 576     MemoryRegion mpui_io_iomem;
 577     MemoryRegion tap_iomem;
 578     MemoryRegion imif_ram;
 579     MemoryRegion sram;
 580
 581     struct omap_dma_port_if_s {
 582         uint32_t (*read[3])(struct omap_mpu_state_s *s,
 583                         hwaddr offset);
 584         void (*write[3])(struct omap_mpu_state_s *s,
 585                         hwaddr offset, uint32_t value);
 586         int (*addr_valid)(struct omap_mpu_state_s *s,
 587                         hwaddr addr);
 588     } port[__omap_dma_port_last];
 589
 590     uint64_t sdram_size;
 591     unsigned long sram_size;
 592
 593     /* MPUI-TIPB peripherals */
 594     struct omap_uart_s *uart[3];
 595
 596     DeviceState *gpio;
 597
 598     struct omap_mcbsp_s *mcbsp1;
 599     struct omap_mcbsp_s *mcbsp3;
 600
 601     /* MPU public TIPB peripherals */
 602     struct omap_32khz_timer_s *os_timer;
 603
 604     struct omap_mmc_s *mmc;
 605
 606     struct omap_mpuio_s *mpuio;
 607
 608     struct omap_uwire_s *microwire;
 609
 610     struct omap_pwl_s *pwl;
 611     struct omap_pwt_s *pwt;
 612     DeviceState *i2c[2];
 613
 614     struct omap_rtc_s *rtc;
 615
 616     struct omap_mcbsp_s *mcbsp2;
 617
 618     struct omap_lpg_s *led[2];
 619
 620     /* MPU private TIPB peripherals */
 621     DeviceState *ih[2];
 622
 623     struct soc_dma_s *dma;
 624
 625     struct omap_mpu_timer_s *timer[3];
 626     struct omap_watchdog_timer_s *wdt;
 627
 628     struct omap_lcd_panel_s *lcd;
 629
 630     uint32_t ulpd_pm_regs[21];
 631     int64_t ulpd_gauge_start;
 632
 633     uint32_t func_mux_ctrl[14];
 634     uint32_t comp_mode_ctrl[1];
 635     uint32_t pull_dwn_ctrl[4];
 636     uint32_t gate_inh_ctrl[1];
 637     uint32_t voltage_ctrl[1];
 638     uint32_t test_dbg_ctrl[1];
 639     uint32_t mod_conf_ctrl[1];
 640     int compat1509;
 641
 642     uint32_t mpui_ctrl;
 643
 644     struct omap_tipb_bridge_s *private_tipb;
 645     struct omap_tipb_bridge_s *public_tipb;
 646
 647     uint32_t tcmi_regs[17];
 648
 649     struct dpll_ctl_s *dpll[3];
 650
 651     omap_clk clks;
 652     struct {
 653         int cold_start;
 654         int clocking_scheme;
 655         uint16_t arm_ckctl;
 656         uint16_t arm_idlect1;
 657         uint16_t arm_idlect2;
 658         uint16_t arm_ewupct;
 659         uint16_t arm_rstct1;
 660         uint16_t arm_rstct2;
 661         uint16_t arm_ckout1;
 662         int dpll1_mode;
 663         uint16_t dsp_idlect1;
 664         uint16_t dsp_idlect2;
 665         uint16_t dsp_rstct2;
 666     } clkm;
 667 };
 668
 669 /* omap1.c */
 670 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram,
 671                 const char *core);
 672
 673 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
 674 void omap_badwidth_write8(void *opaque, hwaddr addr,
 675                 uint32_t value);
 676 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr);
 677 void omap_badwidth_write16(void *opaque, hwaddr addr,
 678                 uint32_t value);
 679 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr);
 680 void omap_badwidth_write32(void *opaque, hwaddr addr,
 681                 uint32_t value);
 682
 683 void omap_mpu_wakeup(void *opaque, int irq, int req);
 684
 685 # define OMAP_BAD_REG(paddr)            \
 686         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \
 687                       __func__, paddr)
 688 # define OMAP_RO_REG(paddr)             \
 689         qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \
 690                                        HWADDR_PRIx "\n", \
 691                       __func__, paddr)
 692
 693 # define OMAP_MPUI_REG_MASK             0x000007ff
 694
 695 #endif