include/hw/intc/armv7m_nvic.h

   1 /*
   2  * ARMv7M NVIC object
   3  *
   4  * Copyright (c) 2017 Linaro Ltd
   5  * Written by Peter Maydell <peter.maydell@linaro.org>
   6  *
   7  * This code is licensed under the GPL version 2 or later.
   8  */
   9
  10 #ifndef HW_ARM_ARMV7M_NVIC_H
  11 #define HW_ARM_ARMV7M_NVIC_H
  12
  13 #include "target/arm/cpu-qom.h"
  14 #include "hw/sysbus.h"
  15 #include "hw/timer/armv7m_systick.h"
  16 #include "qom/object.h"
  17
  18 #define TYPE_NVIC "armv7m_nvic"
  19 OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC)
  20
  21 /* Highest permitted number of exceptions (architectural limit) */
  22 #define NVIC_MAX_VECTORS 512
  23 /* Number of internal exceptions */
  24 #define NVIC_INTERNAL_VECTORS 16
  25
  26 typedef struct VecInfo {
  27     /* Exception priorities can range from -3 to 255; only the unmodifiable
  28      * priority values for RESET, NMI and HardFault can be negative.
  29      */
  30     int16_t prio;
  31     uint8_t enabled;
  32     uint8_t pending;
  33     uint8_t active;
  34     uint8_t level; /* exceptions <=15 never set level */
  35 } VecInfo;
  36
  37 struct NVICState {
  38     /*< private >*/
  39     SysBusDevice parent_obj;
  40     /*< public >*/
  41
  42     ARMCPU *cpu;
  43
  44     VecInfo vectors[NVIC_MAX_VECTORS];
  45     /* If the v8M security extension is implemented, some of the internal
  46      * exceptions are banked between security states (ie there exists both
  47      * a Secure and a NonSecure version of the exception and its state):
  48      *  HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
  49      * The rest (including all the external exceptions) are not banked, though
  50      * they may be configurable to target either Secure or NonSecure state.
  51      * We store the secure exception state in sec_vectors[] for the banked
  52      * exceptions, and otherwise use only vectors[] (including for exceptions
  53      * like SecureFault that unconditionally target Secure state).
  54      * Entries in sec_vectors[] for non-banked exception numbers are unused.
  55      */
  56     VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
  57     /* The PRIGROUP field in AIRCR is banked */
  58     uint32_t prigroup[M_REG_NUM_BANKS];
  59     uint8_t num_prio_bits;
  60
  61     /* v8M NVIC_ITNS state (stored as a bool per bit) */
  62     bool itns[NVIC_MAX_VECTORS];
  63
  64     /* The following fields are all cached state that can be recalculated
  65      * from the vectors[] and sec_vectors[] arrays and the prigroup field:
  66      *  - vectpending
  67      *  - vectpending_is_secure
  68      *  - exception_prio
  69      *  - vectpending_prio
  70      */
  71     unsigned int vectpending; /* highest prio pending enabled exception */
  72     /* true if vectpending is a banked secure exception, ie it is in
  73      * sec_vectors[] rather than vectors[]
  74      */
  75     bool vectpending_is_s_banked;
  76     int exception_prio; /* group prio of the highest prio active exception */
  77     int vectpending_prio; /* group prio of the exception in vectpending */
  78
  79     MemoryRegion sysregmem;
  80
  81     uint32_t num_irq;
  82     qemu_irq excpout;
  83     qemu_irq sysresetreq;
  84 };
  85
  86 /* Interface between CPU and Interrupt controller.  */
  87 /**
  88  * armv7m_nvic_set_pending: mark the specified exception as pending
  89  * @s: the NVIC
  90  * @irq: the exception number to mark pending
  91  * @secure: false for non-banked exceptions or for the nonsecure
  92  * version of a banked exception, true for the secure version of a banked
  93  * exception.
  94  *
  95  * Marks the specified exception as pending. Note that we will assert()
  96  * if @secure is true and @irq does not specify one of the fixed set
  97  * of architecturally banked exceptions.
  98  */
  99 void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 100 /**
 101  * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 102  * @s: the NVIC
 103  * @irq: the exception number to mark pending
 104  * @secure: false for non-banked exceptions or for the nonsecure
 105  * version of a banked exception, true for the secure version of a banked
 106  * exception.
 107  *
 108  * Similar to armv7m_nvic_set_pending(), but specifically for derived
 109  * exceptions (exceptions generated in the course of trying to take
 110  * a different exception).
 111  */
 112 void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 113 /**
 114  * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 115  * @s: the NVIC
 116  * @irq: the exception number to mark pending
 117  * @secure: false for non-banked exceptions or for the nonsecure
 118  * version of a banked exception, true for the secure version of a banked
 119  * exception.
 120  *
 121  * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
 122  * generated in the course of lazy stacking of FP registers.
 123  */
 124 void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 125 /**
 126  * armv7m_nvic_get_pending_irq_info: return highest priority pending
 127  *    exception, and whether it targets Secure state
 128  * @s: the NVIC
 129  * @pirq: set to pending exception number
 130  * @ptargets_secure: set to whether pending exception targets Secure
 131  *
 132  * This function writes the number of the highest priority pending
 133  * exception (the one which would be made active by
 134  * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
 135  * to true if the current highest priority pending exception should
 136  * be taken to Secure state, false for NS.
 137  */
 138 void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
 139                                       bool *ptargets_secure);
 140 /**
 141  * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 142  * @s: the NVIC
 143  *
 144  * Move the current highest priority pending exception from the pending
 145  * state to the active state, and update v7m.exception to indicate that
 146  * it is the exception currently being handled.
 147  */
 148 void armv7m_nvic_acknowledge_irq(NVICState *s);
 149 /**
 150  * armv7m_nvic_complete_irq: complete specified interrupt or exception
 151  * @s: the NVIC
 152  * @irq: the exception number to complete
 153  * @secure: true if this exception was secure
 154  *
 155  * Returns: -1 if the irq was not active
 156  *           1 if completing this irq brought us back to base (no active irqs)
 157  *           0 if there is still an irq active after this one was completed
 158  * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
 159  */
 160 int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 161 /**
 162  * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 163  * @s: the NVIC
 164  * @irq: the exception number to mark pending
 165  * @secure: false for non-banked exceptions or for the nonsecure
 166  * version of a banked exception, true for the secure version of a banked
 167  * exception.
 168  *
 169  * Return whether an exception is "ready", i.e. whether the exception is
 170  * enabled and is configured at a priority which would allow it to
 171  * interrupt the current execution priority. This controls whether the
 172  * RDY bit for it in the FPCCR is set.
 173  */
 174 bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 175 /**
 176  * armv7m_nvic_raw_execution_priority: return the raw execution priority
 177  * @s: the NVIC
 178  *
 179  * Returns: the raw execution priority as defined by the v8M architecture.
 180  * This is the execution priority minus the effects of AIRCR.PRIS,
 181  * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
 182  * (v8M ARM ARM I_PKLD.)
 183  */
 184 int armv7m_nvic_raw_execution_priority(NVICState *s);
 185 /**
 186  * armv7m_nvic_neg_prio_requested: return true if the requested execution
 187  * priority is negative for the specified security state.
 188  * @s: the NVIC
 189  * @secure: the security state to test
 190  * This corresponds to the pseudocode IsReqExecPriNeg().
 191  */
 192 #ifndef CONFIG_USER_ONLY
 193 bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 194 #else
 195 static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 196 {
 197     return false;
 198 }
 199 #endif
 200 #ifndef CONFIG_USER_ONLY
 201 bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 202 #else
 203 static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 204 {
 205     return true;
 206 }
 207 #endif
 208
 209 #endif