include/hw/ppc/pnv_core.h

   1 /*
   2  * QEMU PowerPC PowerNV CPU Core model
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public License
   8  * as published by the Free Software Foundation; either version 2.1 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PPC_PNV_CORE_H
  21 #define PPC_PNV_CORE_H
  22
  23 #include "hw/cpu/core.h"
  24 #include "target/ppc/cpu.h"
  25 #include "hw/ppc/pnv.h"
  26 #include "qom/object.h"
  27
  28 /* Per-core ChipTOD / TimeBase state */
  29 typedef struct PnvCoreTODState {
  30     /*
  31      * POWER10 DD2.0 - big core TFMR drives the state machine on the even
  32      * small core. Skiboot has a workaround that targets the even small core
  33      * for CHIPTOD_TO_TB ops.
  34      */
  35     bool big_core_quirk;
  36
  37     int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */
  38     int tod_sent_to_tb;   /* chiptod sent TOD to the core TB */
  39
  40     /*
  41      * "Timers" for async TBST events are simulated by mfTFAC because TFAC
  42      * is polled for such events. These are just used to ensure firmware
  43      * performs the polling at least a few times.
  44      */
  45     int tb_state_timer;
  46     int tb_sync_pulse_timer;
  47 } PnvCoreTODState;
  48
  49 #define TYPE_PNV_CORE "powernv-cpu-core"
  50 OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass,
  51                     PNV_CORE)
  52
  53 struct PnvCore {
  54     /*< private >*/
  55     CPUCore parent_obj;
  56
  57     /*< public >*/
  58     PowerPCCPU **threads;
  59     bool big_core;
  60     bool lpar_per_core;
  61     uint32_t pir;
  62     uint32_t hwid;
  63     uint64_t hrmor;
  64
  65     target_ulong scratch[8]; /* SPRC/SPRD indirect SCRATCH registers */
  66     PnvCoreTODState tod_state;
  67
  68     PnvChip *chip;
  69
  70     MemoryRegion xscom_regs;
  71 };
  72
  73 struct PnvCoreClass {
  74     DeviceClass parent_class;
  75
  76     const MemoryRegionOps *xscom_ops;
  77     uint64_t xscom_size;
  78 };
  79
  80 #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
  81 #define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
  82
  83 typedef struct PnvCPUState {
  84     PnvCore *pnv_core;
  85     Object *intc;
  86 } PnvCPUState;
  87
  88 static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
  89 {
  90     return (PnvCPUState *)cpu->machine_data;
  91 }
  92
  93 struct PnvQuadClass {
  94     DeviceClass parent_class;
  95
  96     const MemoryRegionOps *xscom_ops;
  97     uint64_t xscom_size;
  98
  99     const MemoryRegionOps *xscom_qme_ops;
 100     uint64_t xscom_qme_size;
 101 };
 102
 103 #define TYPE_PNV_QUAD "powernv-cpu-quad"
 104
 105 #define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD
 106 #define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX
 107
 108 OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD)
 109
 110 struct PnvQuad {
 111     DeviceState parent_obj;
 112
 113     bool special_wakeup_done;
 114     bool special_wakeup[4];
 115
 116     uint32_t quad_id;
 117     MemoryRegion xscom_regs;
 118     MemoryRegion xscom_qme_regs;
 119 };
 120 #endif /* PPC_PNV_CORE_H */