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Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / target / arm / tcg / cpu64.c
blob0168920828651492b1114d66ab0fc72c20dda2a8
1 /*
2 * QEMU AArch64 TCG CPUs
3 *
4 * Copyright (c) 2013 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "cpu.h"
24 #include "qemu/module.h"
25 #include "qapi/visitor.h"
26 #include "hw/qdev-properties.h"
27 #include "qemu/units.h"
28 #include "internals.h"
29 #include "cpu-features.h"
30 #include "cpregs.h"
31
32 static void aarch64_a35_initfn(Object *obj)
33 {
34 ARMCPU *cpu = ARM_CPU(obj);
35
36 cpu->dtb_compatible = "arm,cortex-a35";
37 set_feature(&cpu->env, ARM_FEATURE_V8);
38 set_feature(&cpu->env, ARM_FEATURE_NEON);
39 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
40 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
41 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
42 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
43 set_feature(&cpu->env, ARM_FEATURE_EL2);
44 set_feature(&cpu->env, ARM_FEATURE_EL3);
45 set_feature(&cpu->env, ARM_FEATURE_PMU);
46
47 /* From B2.2 AArch64 identification registers. */
48 cpu->midr = 0x411fd040;
49 cpu->revidr = 0;
50 cpu->ctr = 0x84448004;
51 cpu->isar.id_pfr0 = 0x00000131;
52 cpu->isar.id_pfr1 = 0x00011011;
53 cpu->isar.id_dfr0 = 0x03010066;
54 cpu->id_afr0 = 0;
55 cpu->isar.id_mmfr0 = 0x10201105;
56 cpu->isar.id_mmfr1 = 0x40000000;
57 cpu->isar.id_mmfr2 = 0x01260000;
58 cpu->isar.id_mmfr3 = 0x02102211;
59 cpu->isar.id_isar0 = 0x02101110;
60 cpu->isar.id_isar1 = 0x13112111;
61 cpu->isar.id_isar2 = 0x21232042;
62 cpu->isar.id_isar3 = 0x01112131;
63 cpu->isar.id_isar4 = 0x00011142;
64 cpu->isar.id_isar5 = 0x00011121;
65 cpu->isar.id_aa64pfr0 = 0x00002222;
66 cpu->isar.id_aa64pfr1 = 0;
67 cpu->isar.id_aa64dfr0 = 0x10305106;
68 cpu->isar.id_aa64dfr1 = 0;
69 cpu->isar.id_aa64isar0 = 0x00011120;
70 cpu->isar.id_aa64isar1 = 0;
71 cpu->isar.id_aa64mmfr0 = 0x00101122;
72 cpu->isar.id_aa64mmfr1 = 0;
73 cpu->clidr = 0x0a200023;
74 cpu->dcz_blocksize = 4;
75
76 /* From B2.4 AArch64 Virtual Memory control registers */
77 cpu->reset_sctlr = 0x00c50838;
78
79 /* From B2.10 AArch64 performance monitor registers */
80 cpu->isar.reset_pmcr_el0 = 0x410a3000;
81
82 /* From B2.29 Cache ID registers */
83 /* 32KB L1 dcache */
84 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
85 /* 32KB L1 icache */
86 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2);
87 /* 512KB L2 cache */
88 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7);
89
90 /* From B3.5 VGIC Type register */
91 cpu->gic_num_lrs = 4;
92 cpu->gic_vpribits = 5;
93 cpu->gic_vprebits = 5;
94 cpu->gic_pribits = 5;
95
96 /* From C6.4 Debug ID Register */
97 cpu->isar.dbgdidr = 0x3516d000;
98 /* From C6.5 Debug Device ID Register */
99 cpu->isar.dbgdevid = 0x00110f13;
100 /* From C6.6 Debug Device ID Register 1 */
101 cpu->isar.dbgdevid1 = 0x2;
102
103 /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
104 /* From 3.2 AArch32 register summary */
105 cpu->reset_fpsid = 0x41034043;
106
107 /* From 2.2 AArch64 register summary */
108 cpu->isar.mvfr0 = 0x10110222;
109 cpu->isar.mvfr1 = 0x12111111;
110 cpu->isar.mvfr2 = 0x00000043;
111
112 /* These values are the same with A53/A57/A72. */
113 define_cortex_a72_a57_a53_cp_reginfo(cpu);
114 }
115
116 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
117 void *opaque, Error **errp)
118 {
119 ARMCPU *cpu = ARM_CPU(obj);
120 uint32_t value;
121
122 /* All vector lengths are disabled when SVE is off. */
123 if (!cpu_isar_feature(aa64_sve, cpu)) {
124 value = 0;
125 } else {
126 value = cpu->sve_max_vq;
127 }
128 visit_type_uint32(v, name, &value, errp);
129 }
130
131 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
132 void *opaque, Error **errp)
133 {
134 ARMCPU *cpu = ARM_CPU(obj);
135 uint32_t max_vq;
136
137 if (!visit_type_uint32(v, name, &max_vq, errp)) {
138 return;
139 }
140
141 if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
142 error_setg(errp, "unsupported SVE vector length");
143 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
144 ARM_MAX_VQ);
145 return;
146 }
147
148 cpu->sve_max_vq = max_vq;
149 }
150
151 static bool cpu_arm_get_rme(Object *obj, Error **errp)
152 {
153 ARMCPU *cpu = ARM_CPU(obj);
154 return cpu_isar_feature(aa64_rme, cpu);
155 }
156
157 static void cpu_arm_set_rme(Object *obj, bool value, Error **errp)
158 {
159 ARMCPU *cpu = ARM_CPU(obj);
160 uint64_t t;
161
162 t = cpu->isar.id_aa64pfr0;
163 t = FIELD_DP64(t, ID_AA64PFR0, RME, value);
164 cpu->isar.id_aa64pfr0 = t;
165 }
166
167 static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name,
168 void *opaque, Error **errp)
169 {
170 ARMCPU *cpu = ARM_CPU(obj);
171 uint32_t value;
172
173 if (!visit_type_uint32(v, name, &value, errp)) {
174 return;
175 }
176
177 /* Encode the value for the GPCCR_EL3 field. */
178 switch (value) {
179 case 30:
180 case 34:
181 case 36:
182 case 39:
183 cpu->reset_l0gptsz = value - 30;
184 break;
185 default:
186 error_setg(errp, "invalid value for l0gptsz");
187 error_append_hint(errp, "valid values are 30, 34, 36, 39\n");
188 break;
189 }
190 }
191
192 static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name,
193 void *opaque, Error **errp)
194 {
195 ARMCPU *cpu = ARM_CPU(obj);
196 uint32_t value = cpu->reset_l0gptsz + 30;
197
198 visit_type_uint32(v, name, &value, errp);
199 }
200
201 static Property arm_cpu_lpa2_property =
202 DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
203
204 static void aarch64_a55_initfn(Object *obj)
205 {
206 ARMCPU *cpu = ARM_CPU(obj);
207
208 cpu->dtb_compatible = "arm,cortex-a55";
209 set_feature(&cpu->env, ARM_FEATURE_V8);
210 set_feature(&cpu->env, ARM_FEATURE_NEON);
211 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
212 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
213 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
214 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
215 set_feature(&cpu->env, ARM_FEATURE_EL2);
216 set_feature(&cpu->env, ARM_FEATURE_EL3);
217 set_feature(&cpu->env, ARM_FEATURE_PMU);
218
219 /* Ordered by B2.4 AArch64 registers by functional group */
220 cpu->clidr = 0x82000023;
221 cpu->ctr = 0x84448004; /* L1Ip = VIPT */
222 cpu->dcz_blocksize = 4; /* 64 bytes */
223 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
224 cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
225 cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
226 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
227 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
228 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
229 cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
230 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
231 cpu->id_afr0 = 0x00000000;
232 cpu->isar.id_dfr0 = 0x04010088;
233 cpu->isar.id_isar0 = 0x02101110;
234 cpu->isar.id_isar1 = 0x13112111;
235 cpu->isar.id_isar2 = 0x21232042;
236 cpu->isar.id_isar3 = 0x01112131;
237 cpu->isar.id_isar4 = 0x00011142;
238 cpu->isar.id_isar5 = 0x01011121;
239 cpu->isar.id_isar6 = 0x00000010;
240 cpu->isar.id_mmfr0 = 0x10201105;
241 cpu->isar.id_mmfr1 = 0x40000000;
242 cpu->isar.id_mmfr2 = 0x01260000;
243 cpu->isar.id_mmfr3 = 0x02122211;
244 cpu->isar.id_mmfr4 = 0x00021110;
245 cpu->isar.id_pfr0 = 0x10010131;
246 cpu->isar.id_pfr1 = 0x00011011;
247 cpu->isar.id_pfr2 = 0x00000011;
248 cpu->midr = 0x412FD050; /* r2p0 */
249 cpu->revidr = 0;
250
251 /* From B2.23 CCSIDR_EL1 */
252 /* 32KB L1 dcache */
253 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
254 /* 32KB L1 icache */
255 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2);
256 /* 512KB L2 cache */
257 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7);
258
259 /* From B2.96 SCTLR_EL3 */
260 cpu->reset_sctlr = 0x30c50838;
261
262 /* From B4.45 ICH_VTR_EL2 */
263 cpu->gic_num_lrs = 4;
264 cpu->gic_vpribits = 5;
265 cpu->gic_vprebits = 5;
266 cpu->gic_pribits = 5;
267
268 cpu->isar.mvfr0 = 0x10110222;
269 cpu->isar.mvfr1 = 0x13211111;
270 cpu->isar.mvfr2 = 0x00000043;
271
272 /* From D5.4 AArch64 PMU register summary */
273 cpu->isar.reset_pmcr_el0 = 0x410b3000;
274 }
275
276 static void aarch64_a72_initfn(Object *obj)
277 {
278 ARMCPU *cpu = ARM_CPU(obj);
279
280 cpu->dtb_compatible = "arm,cortex-a72";
281 set_feature(&cpu->env, ARM_FEATURE_V8);
282 set_feature(&cpu->env, ARM_FEATURE_NEON);
283 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
284 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
285 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
286 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
287 set_feature(&cpu->env, ARM_FEATURE_EL2);
288 set_feature(&cpu->env, ARM_FEATURE_EL3);
289 set_feature(&cpu->env, ARM_FEATURE_PMU);
290 cpu->midr = 0x410fd083;
291 cpu->revidr = 0x00000000;
292 cpu->reset_fpsid = 0x41034080;
293 cpu->isar.mvfr0 = 0x10110222;
294 cpu->isar.mvfr1 = 0x12111111;
295 cpu->isar.mvfr2 = 0x00000043;
296 cpu->ctr = 0x8444c004;
297 cpu->reset_sctlr = 0x00c50838;
298 cpu->isar.id_pfr0 = 0x00000131;
299 cpu->isar.id_pfr1 = 0x00011011;
300 cpu->isar.id_dfr0 = 0x03010066;
301 cpu->id_afr0 = 0x00000000;
302 cpu->isar.id_mmfr0 = 0x10201105;
303 cpu->isar.id_mmfr1 = 0x40000000;
304 cpu->isar.id_mmfr2 = 0x01260000;
305 cpu->isar.id_mmfr3 = 0x02102211;
306 cpu->isar.id_isar0 = 0x02101110;
307 cpu->isar.id_isar1 = 0x13112111;
308 cpu->isar.id_isar2 = 0x21232042;
309 cpu->isar.id_isar3 = 0x01112131;
310 cpu->isar.id_isar4 = 0x00011142;
311 cpu->isar.id_isar5 = 0x00011121;
312 cpu->isar.id_aa64pfr0 = 0x00002222;
313 cpu->isar.id_aa64dfr0 = 0x10305106;
314 cpu->isar.id_aa64isar0 = 0x00011120;
315 cpu->isar.id_aa64mmfr0 = 0x00001124;
316 cpu->isar.dbgdidr = 0x3516d000;
317 cpu->isar.dbgdevid = 0x01110f13;
318 cpu->isar.dbgdevid1 = 0x2;
319 cpu->isar.reset_pmcr_el0 = 0x41023000;
320 cpu->clidr = 0x0a200023;
321 /* 32KB L1 dcache */
322 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
323 /* 48KB L1 dcache */
324 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
325 /* 1MB L2 cache */
326 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7);
327 cpu->dcz_blocksize = 4; /* 64 bytes */
328 cpu->gic_num_lrs = 4;
329 cpu->gic_vpribits = 5;
330 cpu->gic_vprebits = 5;
331 cpu->gic_pribits = 5;
332 define_cortex_a72_a57_a53_cp_reginfo(cpu);
333 }
334
335 static void aarch64_a76_initfn(Object *obj)
336 {
337 ARMCPU *cpu = ARM_CPU(obj);
338
339 cpu->dtb_compatible = "arm,cortex-a76";
340 set_feature(&cpu->env, ARM_FEATURE_V8);
341 set_feature(&cpu->env, ARM_FEATURE_NEON);
342 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
343 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
344 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
345 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
346 set_feature(&cpu->env, ARM_FEATURE_EL2);
347 set_feature(&cpu->env, ARM_FEATURE_EL3);
348 set_feature(&cpu->env, ARM_FEATURE_PMU);
349
350 /* Ordered by B2.4 AArch64 registers by functional group */
351 cpu->clidr = 0x82000023;
352 cpu->ctr = 0x8444C004;
353 cpu->dcz_blocksize = 4;
354 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
355 cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
356 cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
357 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
358 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
359 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
360 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
361 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
362 cpu->id_afr0 = 0x00000000;
363 cpu->isar.id_dfr0 = 0x04010088;
364 cpu->isar.id_isar0 = 0x02101110;
365 cpu->isar.id_isar1 = 0x13112111;
366 cpu->isar.id_isar2 = 0x21232042;
367 cpu->isar.id_isar3 = 0x01112131;
368 cpu->isar.id_isar4 = 0x00010142;
369 cpu->isar.id_isar5 = 0x01011121;
370 cpu->isar.id_isar6 = 0x00000010;
371 cpu->isar.id_mmfr0 = 0x10201105;
372 cpu->isar.id_mmfr1 = 0x40000000;
373 cpu->isar.id_mmfr2 = 0x01260000;
374 cpu->isar.id_mmfr3 = 0x02122211;
375 cpu->isar.id_mmfr4 = 0x00021110;
376 cpu->isar.id_pfr0 = 0x10010131;
377 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
378 cpu->isar.id_pfr2 = 0x00000011;
379 cpu->midr = 0x414fd0b1; /* r4p1 */
380 cpu->revidr = 0;
381
382 /* From B2.18 CCSIDR_EL1 */
383 /* 64KB L1 dcache */
384 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7);
385 /* 64KB L1 icache */
386 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2);
387 /* 512KB L2 cache */
388 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7);
389
390 /* From B2.93 SCTLR_EL3 */
391 cpu->reset_sctlr = 0x30c50838;
392
393 /* From B4.23 ICH_VTR_EL2 */
394 cpu->gic_num_lrs = 4;
395 cpu->gic_vpribits = 5;
396 cpu->gic_vprebits = 5;
397 cpu->gic_pribits = 5;
398
399 /* From B5.1 AdvSIMD AArch64 register summary */
400 cpu->isar.mvfr0 = 0x10110222;
401 cpu->isar.mvfr1 = 0x13211111;
402 cpu->isar.mvfr2 = 0x00000043;
403
404 /* From D5.1 AArch64 PMU register summary */
405 cpu->isar.reset_pmcr_el0 = 0x410b3000;
406 }
407
408 static void aarch64_a64fx_initfn(Object *obj)
409 {
410 ARMCPU *cpu = ARM_CPU(obj);
411
412 cpu->dtb_compatible = "arm,a64fx";
413 set_feature(&cpu->env, ARM_FEATURE_V8);
414 set_feature(&cpu->env, ARM_FEATURE_NEON);
415 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
416 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
417 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
418 set_feature(&cpu->env, ARM_FEATURE_EL2);
419 set_feature(&cpu->env, ARM_FEATURE_EL3);
420 set_feature(&cpu->env, ARM_FEATURE_PMU);
421 cpu->midr = 0x461f0010;
422 cpu->revidr = 0x00000000;
423 cpu->ctr = 0x86668006;
424 cpu->reset_sctlr = 0x30000180;
425 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
426 cpu->isar.id_aa64pfr1 = 0x0000000000000000;
427 cpu->isar.id_aa64dfr0 = 0x0000000010305408;
428 cpu->isar.id_aa64dfr1 = 0x0000000000000000;
429 cpu->id_aa64afr0 = 0x0000000000000000;
430 cpu->id_aa64afr1 = 0x0000000000000000;
431 cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
432 cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
433 cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
434 cpu->isar.id_aa64isar0 = 0x0000000010211120;
435 cpu->isar.id_aa64isar1 = 0x0000000000010001;
436 cpu->isar.id_aa64zfr0 = 0x0000000000000000;
437 cpu->clidr = 0x0000000080000023;
438 /* 64KB L1 dcache */
439 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7);
440 /* 64KB L1 icache */
441 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 2);
442 /* 8MB L2 cache */
443 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB, 7);
444 cpu->dcz_blocksize = 6; /* 256 bytes */
445 cpu->gic_num_lrs = 4;
446 cpu->gic_vpribits = 5;
447 cpu->gic_vprebits = 5;
448 cpu->gic_pribits = 5;
449
450 /* The A64FX supports only 128, 256 and 512 bit vector lengths */
451 aarch64_add_sve_properties(obj);
452 cpu->sve_vq.supported = (1 << 0) /* 128bit */
453 | (1 << 1) /* 256bit */
454 | (1 << 3); /* 512bit */
455
456 cpu->isar.reset_pmcr_el0 = 0x46014040;
457
458 /* TODO: Add A64FX specific HPC extension registers */
459 }
460
461 static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
462 bool read)
463 {
464 if (!read) {
465 int el = arm_current_el(env);
466
467 /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
468 if (el < 2 && arm_is_el2_enabled(env)) {
469 return CP_ACCESS_TRAP_EL2;
470 }
471 /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
472 if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
473 return CP_ACCESS_TRAP_EL3;
474 }
475 }
476 return CP_ACCESS_OK;
477 }
478
479 static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
480 { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
481 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
482 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
483 /* Traps and enables are the same as for TCR_EL1. */
484 .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
485 { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
486 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
487 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
488 { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
489 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
490 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
491 { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64,
492 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
493 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
494 { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
495 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
496 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
497 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
498 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
499 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
500 .accessfn = access_actlr_w },
501 { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
502 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
503 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
504 .accessfn = access_actlr_w },
505 { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
506 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
507 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
508 .accessfn = access_actlr_w },
509 /*
510 * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
511 * (and in particular its system registers).
512 */
513 { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
514 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
515 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
516 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
517 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
518 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
519 .accessfn = access_actlr_w },
520 { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
521 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
522 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
523 { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64,
524 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3,
525 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
526 { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64,
527 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2,
528 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
529 { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64,
530 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
531 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
532 { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
533 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
534 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
535 .accessfn = access_actlr_w },
536 { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
537 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
538 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
539 .accessfn = access_actlr_w },
540 { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
541 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
542 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
543 .accessfn = access_actlr_w },
544 { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
545 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
546 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
547 .accessfn = access_actlr_w },
548 };
549
550 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
551 {
552 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo);
553 }
554
555 static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
556 { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
557 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
558 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
559 .accessfn = access_actlr_w },
560 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
561 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
562 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
563 { .name = "CPUPPMCR2_EL3", .state = ARM_CP_STATE_AA64,
564 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 1,
565 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
566 { .name = "CPUPPMCR3_EL3", .state = ARM_CP_STATE_AA64,
567 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6,
568 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
569 };
570
571 static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu)
572 {
573 /*
574 * The Neoverse V1 has all of the Neoverse N1's IMPDEF
575 * registers and a few more of its own.
576 */
577 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo);
578 define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo);
579 }
580
581 static void aarch64_neoverse_n1_initfn(Object *obj)
582 {
583 ARMCPU *cpu = ARM_CPU(obj);
584
585 cpu->dtb_compatible = "arm,neoverse-n1";
586 set_feature(&cpu->env, ARM_FEATURE_V8);
587 set_feature(&cpu->env, ARM_FEATURE_NEON);
588 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
589 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
590 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
591 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
592 set_feature(&cpu->env, ARM_FEATURE_EL2);
593 set_feature(&cpu->env, ARM_FEATURE_EL3);
594 set_feature(&cpu->env, ARM_FEATURE_PMU);
595
596 /* Ordered by B2.4 AArch64 registers by functional group */
597 cpu->clidr = 0x82000023;
598 cpu->ctr = 0x8444c004;
599 cpu->dcz_blocksize = 4;
600 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
601 cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
602 cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
603 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
604 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
605 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
606 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
607 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
608 cpu->id_afr0 = 0x00000000;
609 cpu->isar.id_dfr0 = 0x04010088;
610 cpu->isar.id_isar0 = 0x02101110;
611 cpu->isar.id_isar1 = 0x13112111;
612 cpu->isar.id_isar2 = 0x21232042;
613 cpu->isar.id_isar3 = 0x01112131;
614 cpu->isar.id_isar4 = 0x00010142;
615 cpu->isar.id_isar5 = 0x01011121;
616 cpu->isar.id_isar6 = 0x00000010;
617 cpu->isar.id_mmfr0 = 0x10201105;
618 cpu->isar.id_mmfr1 = 0x40000000;
619 cpu->isar.id_mmfr2 = 0x01260000;
620 cpu->isar.id_mmfr3 = 0x02122211;
621 cpu->isar.id_mmfr4 = 0x00021110;
622 cpu->isar.id_pfr0 = 0x10010131;
623 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
624 cpu->isar.id_pfr2 = 0x00000011;
625 cpu->midr = 0x414fd0c1; /* r4p1 */
626 cpu->revidr = 0;
627
628 /* From B2.23 CCSIDR_EL1 */
629 /* 64KB L1 dcache */
630 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7);
631 /* 64KB L1 icache */
632 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2);
633 /* 1MB L2 dcache */
634 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7);
635
636 /* From B2.98 SCTLR_EL3 */
637 cpu->reset_sctlr = 0x30c50838;
638
639 /* From B4.23 ICH_VTR_EL2 */
640 cpu->gic_num_lrs = 4;
641 cpu->gic_vpribits = 5;
642 cpu->gic_vprebits = 5;
643 cpu->gic_pribits = 5;
644
645 /* From B5.1 AdvSIMD AArch64 register summary */
646 cpu->isar.mvfr0 = 0x10110222;
647 cpu->isar.mvfr1 = 0x13211111;
648 cpu->isar.mvfr2 = 0x00000043;
649
650 /* From D5.1 AArch64 PMU register summary */
651 cpu->isar.reset_pmcr_el0 = 0x410c3000;
652
653 define_neoverse_n1_cp_reginfo(cpu);
654 }
655
656 static void aarch64_neoverse_v1_initfn(Object *obj)
657 {
658 ARMCPU *cpu = ARM_CPU(obj);
659
660 cpu->dtb_compatible = "arm,neoverse-v1";
661 set_feature(&cpu->env, ARM_FEATURE_V8);
662 set_feature(&cpu->env, ARM_FEATURE_NEON);
663 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
664 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
665 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
666 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
667 set_feature(&cpu->env, ARM_FEATURE_EL2);
668 set_feature(&cpu->env, ARM_FEATURE_EL3);
669 set_feature(&cpu->env, ARM_FEATURE_PMU);
670
671 /* Ordered by 3.2.4 AArch64 registers by functional group */
672 cpu->clidr = 0x82000023;
673 cpu->ctr = 0xb444c004; /* With DIC and IDC set */
674 cpu->dcz_blocksize = 4;
675 cpu->id_aa64afr0 = 0x00000000;
676 cpu->id_aa64afr1 = 0x00000000;
677 cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
678 cpu->isar.id_aa64dfr1 = 0x00000000;
679 cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */
680 cpu->isar.id_aa64isar1 = 0x0011100001211032ull;
681 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
682 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
683 cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;
684 cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */
685 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
686 cpu->id_afr0 = 0x00000000;
687 cpu->isar.id_dfr0 = 0x15011099;
688 cpu->isar.id_isar0 = 0x02101110;
689 cpu->isar.id_isar1 = 0x13112111;
690 cpu->isar.id_isar2 = 0x21232042;
691 cpu->isar.id_isar3 = 0x01112131;
692 cpu->isar.id_isar4 = 0x00010142;
693 cpu->isar.id_isar5 = 0x11011121;
694 cpu->isar.id_isar6 = 0x01100111;
695 cpu->isar.id_mmfr0 = 0x10201105;
696 cpu->isar.id_mmfr1 = 0x40000000;
697 cpu->isar.id_mmfr2 = 0x01260000;
698 cpu->isar.id_mmfr3 = 0x02122211;
699 cpu->isar.id_mmfr4 = 0x01021110;
700 cpu->isar.id_pfr0 = 0x21110131;
701 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
702 cpu->isar.id_pfr2 = 0x00000011;
703 cpu->midr = 0x411FD402; /* r1p2 */
704 cpu->revidr = 0;
705
706 /*
707 * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
708 * but also says it implements CCIDX, which means they should be
709 * 64-bit format. So we here use values which are based on the textual
710 * information in chapter 2 of the TRM:
711 *
712 * L1: 4-way set associative 64-byte line size, total size 64K.
713 * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
714 * L3: No L3 (this matches the CLIDR_EL1 value).
715 */
716 /* 64KB L1 dcache */
717 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0);
718 /* 64KB L1 icache */
719 cpu->ccsidr[1] = cpu->ccsidr[0];
720 /* 1MB L2 cache */
721 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0);
722
723 /* From 3.2.115 SCTLR_EL3 */
724 cpu->reset_sctlr = 0x30c50838;
725
726 /* From 3.4.8 ICC_CTLR_EL3 and 3.4.23 ICH_VTR_EL2 */
727 cpu->gic_num_lrs = 4;
728 cpu->gic_vpribits = 5;
729 cpu->gic_vprebits = 5;
730 cpu->gic_pribits = 5;
731
732 /* From 3.5.1 AdvSIMD AArch64 register summary */
733 cpu->isar.mvfr0 = 0x10110222;
734 cpu->isar.mvfr1 = 0x13211111;
735 cpu->isar.mvfr2 = 0x00000043;
736
737 /* From 3.7.5 ID_AA64ZFR0_EL1 */
738 cpu->isar.id_aa64zfr0 = 0x0000100000100000;
739 cpu->sve_vq.supported = (1 << 0) /* 128bit */
740 | (1 << 1); /* 256bit */
741
742 /* From 5.5.1 AArch64 PMU register summary */
743 cpu->isar.reset_pmcr_el0 = 0x41213000;
744
745 define_neoverse_v1_cp_reginfo(cpu);
746
747 aarch64_add_pauth_properties(obj);
748 aarch64_add_sve_properties(obj);
749 }
750
751 static const ARMCPRegInfo cortex_a710_cp_reginfo[] = {
752 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
753 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
754 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
755 .accessfn = access_actlr_w },
756 { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
757 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
758 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
759 .accessfn = access_actlr_w },
760 { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
761 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
762 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
763 .accessfn = access_actlr_w },
764 { .name = "CPUACTLR4_EL1", .state = ARM_CP_STATE_AA64,
765 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 3,
766 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
767 .accessfn = access_actlr_w },
768 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
769 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
770 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
771 .accessfn = access_actlr_w },
772 { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
773 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
774 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
775 .accessfn = access_actlr_w },
776 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
777 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 4,
778 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
779 { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
780 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
781 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
782 .accessfn = access_actlr_w },
783 { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
784 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
785 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
786 { .name = "CPUACTLR5_EL1", .state = ARM_CP_STATE_AA64,
787 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 0,
788 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
789 .accessfn = access_actlr_w },
790 { .name = "CPUACTLR6_EL1", .state = ARM_CP_STATE_AA64,
791 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 1,
792 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
793 .accessfn = access_actlr_w },
794 { .name = "CPUACTLR7_EL1", .state = ARM_CP_STATE_AA64,
795 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 2,
796 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
797 .accessfn = access_actlr_w },
798 { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
799 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
800 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
801 { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
802 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
803 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
804 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
805 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
806 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
807 { .name = "CPUPPMCR2_EL3", .state = ARM_CP_STATE_AA64,
808 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 1,
809 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
810 { .name = "CPUPPMCR4_EL3", .state = ARM_CP_STATE_AA64,
811 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 4,
812 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
813 { .name = "CPUPPMCR5_EL3", .state = ARM_CP_STATE_AA64,
814 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 5,
815 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
816 { .name = "CPUPPMCR6_EL3", .state = ARM_CP_STATE_AA64,
817 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6,
818 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
819 { .name = "CPUACTLR_EL3", .state = ARM_CP_STATE_AA64,
820 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 4, .opc2 = 0,
821 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
822 { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
823 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
824 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
825 { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64,
826 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
827 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
828 { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
829 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
830 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
831 { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64,
832 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2,
833 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
834 { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64,
835 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3,
836 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
837 { .name = "CPUPOR2_EL3", .state = ARM_CP_STATE_AA64,
838 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 4,
839 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
840 { .name = "CPUPMR2_EL3", .state = ARM_CP_STATE_AA64,
841 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 5,
842 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
843 { .name = "CPUPFR_EL3", .state = ARM_CP_STATE_AA64,
844 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 6,
845 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
846 /*
847 * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
848 * (and in particular its system registers).
849 */
850 { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
851 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
852 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
853
854 /*
855 * Stub RAMINDEX, as we don't actually implement caches, BTB,
856 * or anything else with cpu internal memory.
857 * "Read" zeros into the IDATA* and DDATA* output registers.
858 */
859 { .name = "RAMINDEX_EL3", .state = ARM_CP_STATE_AA64,
860 .opc0 = 1, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0,
861 .access = PL3_W, .type = ARM_CP_CONST, .resetvalue = 0 },
862 { .name = "IDATA0_EL3", .state = ARM_CP_STATE_AA64,
863 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0,
864 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
865 { .name = "IDATA1_EL3", .state = ARM_CP_STATE_AA64,
866 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 1,
867 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
868 { .name = "IDATA2_EL3", .state = ARM_CP_STATE_AA64,
869 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 2,
870 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
871 { .name = "DDATA0_EL3", .state = ARM_CP_STATE_AA64,
872 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 0,
873 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
874 { .name = "DDATA1_EL3", .state = ARM_CP_STATE_AA64,
875 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 1,
876 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
877 { .name = "DDATA2_EL3", .state = ARM_CP_STATE_AA64,
878 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 2,
879 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 },
880 };
881
882 static void aarch64_a710_initfn(Object *obj)
883 {
884 ARMCPU *cpu = ARM_CPU(obj);
885
886 cpu->dtb_compatible = "arm,cortex-a710";
887 set_feature(&cpu->env, ARM_FEATURE_V8);
888 set_feature(&cpu->env, ARM_FEATURE_NEON);
889 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
890 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
891 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
892 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
893 set_feature(&cpu->env, ARM_FEATURE_EL2);
894 set_feature(&cpu->env, ARM_FEATURE_EL3);
895 set_feature(&cpu->env, ARM_FEATURE_PMU);
896
897 /* Ordered by Section B.4: AArch64 registers */
898 cpu->midr = 0x412FD471; /* r2p1 */
899 cpu->revidr = 0;
900 cpu->isar.id_pfr0 = 0x21110131;
901 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
902 cpu->isar.id_dfr0 = 0x16011099;
903 cpu->id_afr0 = 0;
904 cpu->isar.id_mmfr0 = 0x10201105;
905 cpu->isar.id_mmfr1 = 0x40000000;
906 cpu->isar.id_mmfr2 = 0x01260000;
907 cpu->isar.id_mmfr3 = 0x02122211;
908 cpu->isar.id_isar0 = 0x02101110;
909 cpu->isar.id_isar1 = 0x13112111;
910 cpu->isar.id_isar2 = 0x21232042;
911 cpu->isar.id_isar3 = 0x01112131;
912 cpu->isar.id_isar4 = 0x00010142;
913 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
914 cpu->isar.id_mmfr4 = 0x21021110;
915 cpu->isar.id_isar6 = 0x01111111;
916 cpu->isar.mvfr0 = 0x10110222;
917 cpu->isar.mvfr1 = 0x13211111;
918 cpu->isar.mvfr2 = 0x00000043;
919 cpu->isar.id_pfr2 = 0x00000011;
920 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
921 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
922 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
923 cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
924 cpu->isar.id_aa64dfr1 = 0;
925 cpu->id_aa64afr0 = 0;
926 cpu->id_aa64afr1 = 0;
927 cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
928 cpu->isar.id_aa64isar1 = 0x0010111101211052ull;
929 cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
930 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
931 cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull;
932 cpu->clidr = 0x0000001482000023ull;
933 cpu->gm_blocksize = 4;
934 cpu->ctr = 0x000000049444c004ull;
935 cpu->dcz_blocksize = 4;
936 /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_0006_003f */
937
938 /* Section B.5.2: PMCR_EL0 */
939 cpu->isar.reset_pmcr_el0 = 0xa000; /* with 20 counters */
940
941 /* Section B.6.7: ICH_VTR_EL2 */
942 cpu->gic_num_lrs = 4;
943 cpu->gic_vpribits = 5;
944 cpu->gic_vprebits = 5;
945 cpu->gic_pribits = 5;
946
947 /* Section 14: Scalable Vector Extensions support */
948 cpu->sve_vq.supported = 1 << 0; /* 128bit */
949
950 /*
951 * The cortex-a710 TRM does not list CCSIDR values. The layout of
952 * the caches are in text in Table 7-1, Table 8-1, and Table 9-1.
953 *
954 * L1: 4-way set associative 64-byte line size, total either 32K or 64K.
955 * L2: 8-way set associative 64 byte line size, total either 256K or 512K.
956 */
957 /* L1 dcache */
958 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0);
959 /* L1 icache */
960 cpu->ccsidr[1] = cpu->ccsidr[0];
961 /* L2 cache */
962 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0);
963
964 /* FIXME: Not documented -- copied from neoverse-v1 */
965 cpu->reset_sctlr = 0x30c50838;
966
967 define_arm_cp_regs(cpu, cortex_a710_cp_reginfo);
968
969 aarch64_add_pauth_properties(obj);
970 aarch64_add_sve_properties(obj);
971 }
972
973 /* Extra IMPDEF regs in the N2 beyond those in the A710 */
974 static const ARMCPRegInfo neoverse_n2_cp_reginfo[] = {
975 { .name = "CPURNDBR_EL3", .state = ARM_CP_STATE_AA64,
976 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 0,
977 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
978 { .name = "CPURNDPEID_EL3", .state = ARM_CP_STATE_AA64,
979 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 1,
980 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
981 };
982
983 static void aarch64_neoverse_n2_initfn(Object *obj)
984 {
985 ARMCPU *cpu = ARM_CPU(obj);
986
987 cpu->dtb_compatible = "arm,neoverse-n2";
988 set_feature(&cpu->env, ARM_FEATURE_V8);
989 set_feature(&cpu->env, ARM_FEATURE_NEON);
990 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
991 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
992 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
993 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
994 set_feature(&cpu->env, ARM_FEATURE_EL2);
995 set_feature(&cpu->env, ARM_FEATURE_EL3);
996 set_feature(&cpu->env, ARM_FEATURE_PMU);
997
998 /* Ordered by Section B.5: AArch64 ID registers */
999 cpu->midr = 0x410FD493; /* r0p3 */
1000 cpu->revidr = 0;
1001 cpu->isar.id_pfr0 = 0x21110131;
1002 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
1003 cpu->isar.id_dfr0 = 0x16011099;
1004 cpu->id_afr0 = 0;
1005 cpu->isar.id_mmfr0 = 0x10201105;
1006 cpu->isar.id_mmfr1 = 0x40000000;
1007 cpu->isar.id_mmfr2 = 0x01260000;
1008 cpu->isar.id_mmfr3 = 0x02122211;
1009 cpu->isar.id_isar0 = 0x02101110;
1010 cpu->isar.id_isar1 = 0x13112111;
1011 cpu->isar.id_isar2 = 0x21232042;
1012 cpu->isar.id_isar3 = 0x01112131;
1013 cpu->isar.id_isar4 = 0x00010142;
1014 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
1015 cpu->isar.id_mmfr4 = 0x01021110;
1016 cpu->isar.id_isar6 = 0x01111111;
1017 cpu->isar.mvfr0 = 0x10110222;
1018 cpu->isar.mvfr1 = 0x13211111;
1019 cpu->isar.mvfr2 = 0x00000043;
1020 cpu->isar.id_pfr2 = 0x00000011;
1021 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
1022 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
1023 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
1024 cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
1025 cpu->isar.id_aa64dfr1 = 0;
1026 cpu->id_aa64afr0 = 0;
1027 cpu->id_aa64afr1 = 0;
1028 cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */
1029 cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
1030 cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
1031 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
1032 cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull;
1033 cpu->clidr = 0x0000001482000023ull;
1034 cpu->gm_blocksize = 4;
1035 cpu->ctr = 0x00000004b444c004ull;
1036 cpu->dcz_blocksize = 4;
1037 /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_001e_01ff */
1038
1039 /* Section B.7.2: PMCR_EL0 */
1040 cpu->isar.reset_pmcr_el0 = 0x3000; /* with 6 counters */
1041
1042 /* Section B.8.9: ICH_VTR_EL2 */
1043 cpu->gic_num_lrs = 4;
1044 cpu->gic_vpribits = 5;
1045 cpu->gic_vprebits = 5;
1046 cpu->gic_pribits = 5;
1047
1048 /* Section 14: Scalable Vector Extensions support */
1049 cpu->sve_vq.supported = 1 << 0; /* 128bit */
1050
1051 /*
1052 * The Neoverse N2 TRM does not list CCSIDR values. The layout of
1053 * the caches are in text in Table 7-1, Table 8-1, and Table 9-1.
1054 *
1055 * L1: 4-way set associative 64-byte line size, total 64K.
1056 * L2: 8-way set associative 64 byte line size, total either 512K or 1024K.
1057 */
1058 /* L1 dcache */
1059 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0);
1060 /* L1 icache */
1061 cpu->ccsidr[1] = cpu->ccsidr[0];
1062 /* L2 cache */
1063 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0);
1064 /* FIXME: Not documented -- copied from neoverse-v1 */
1065 cpu->reset_sctlr = 0x30c50838;
1066
1067 /*
1068 * The Neoverse N2 has all of the Cortex-A710 IMPDEF registers,
1069 * and a few more RNG related ones.
1070 */
1071 define_arm_cp_regs(cpu, cortex_a710_cp_reginfo);
1072 define_arm_cp_regs(cpu, neoverse_n2_cp_reginfo);
1073
1074 aarch64_add_pauth_properties(obj);
1075 aarch64_add_sve_properties(obj);
1076 }
1077
1078 /*
1079 * -cpu max: a CPU with as many features enabled as our emulation supports.
1080 * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c;
1081 * this only needs to handle 64 bits.
1082 */
1083 void aarch64_max_tcg_initfn(Object *obj)
1084 {
1085 ARMCPU *cpu = ARM_CPU(obj);
1086 uint64_t t;
1087 uint32_t u;
1088
1089 /*
1090 * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
1091 * to because we started with aarch64_a57_initfn(). A 'max' CPU might
1092 * be a v8.6-or-later one, in which case the cntfrq must be 1GHz; and
1093 * because it is our "may change" CPU type we are OK with it not being
1094 * backwards-compatible with how it worked in old QEMU.
1095 */
1096 unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
1097
1098 /*
1099 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
1100 * one and try to apply errata workarounds or use impdef features we
1101 * don't provide.
1102 * An IMPLEMENTER field of 0 means "reserved for software use";
1103 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
1104 * to see which features are present";
1105 * the VARIANT, PARTNUM and REVISION fields are all implementation
1106 * defined and we choose to define PARTNUM just in case guest
1107 * code needs to distinguish this QEMU CPU from other software
1108 * implementations, though this shouldn't be needed.
1109 */
1110 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
1111 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
1112 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
1113 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
1114 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
1115 cpu->midr = t;
1116
1117 /*
1118 * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
1119 * are zero.
1120 */
1121 u = cpu->clidr;
1122 u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
1123 u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
1124 cpu->clidr = u;
1125
1126 /*
1127 * Set CTR_EL0.DIC and IDC to tell the guest it doesnt' need to
1128 * do any cache maintenance for data-to-instruction or
1129 * instruction-to-guest coherence. (Our cache ops are nops.)
1130 */
1131 t = cpu->ctr;
1132 t = FIELD_DP64(t, CTR_EL0, IDC, 1);
1133 t = FIELD_DP64(t, CTR_EL0, DIC, 1);
1134 cpu->ctr = t;
1135
1136 t = cpu->isar.id_aa64isar0;
1137 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
1138 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
1139 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
1140 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */
1141 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
1142 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
1143 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
1144 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
1145 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
1146 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
1147 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
1148 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
1149 t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
1150 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
1151 cpu->isar.id_aa64isar0 = t;
1152
1153 t = cpu->isar.id_aa64isar1;
1154 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
1155 t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED);
1156 t = FIELD_DP64(t, ID_AA64ISAR1, API, 1);
1157 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
1158 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
1159 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
1160 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
1161 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
1162 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
1163 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF16 */
1164 t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
1165 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
1166 cpu->isar.id_aa64isar1 = t;
1167
1168 t = cpu->isar.id_aa64isar2;
1169 t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */
1170 t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */
1171 t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */
1172 cpu->isar.id_aa64isar2 = t;
1173
1174 t = cpu->isar.id_aa64pfr0;
1175 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
1176 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
1177 t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
1178 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
1179 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
1180 t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
1181 t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */
1182 t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
1183 cpu->isar.id_aa64pfr0 = t;
1184
1185 t = cpu->isar.id_aa64pfr1;
1186 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
1187 t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
1188 /*
1189 * Begin with full support for MTE. This will be downgraded to MTE=0
1190 * during realize if the board provides no tag memory, much like
1191 * we do for EL2 with the virtualization=on property.
1192 */
1193 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
1194 t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
1195 t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
1196 t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */
1197 t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
1198 cpu->isar.id_aa64pfr1 = t;
1199
1200 t = cpu->isar.id_aa64mmfr0;
1201 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
1202 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
1203 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
1204 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
1205 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
1206 t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
1207 t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */
1208 cpu->isar.id_aa64mmfr0 = t;
1209
1210 t = cpu->isar.id_aa64mmfr1;
1211 t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
1212 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
1213 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
1214 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */
1215 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
1216 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */
1217 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
1218 t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */
1219 t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
1220 t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */
1221 cpu->isar.id_aa64mmfr1 = t;
1222
1223 t = cpu->isar.id_aa64mmfr2;
1224 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
1225 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
1226 t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
1227 t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
1228 t = FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* FEAT_NV2 */
1229 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
1230 t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */
1231 t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
1232 t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
1233 t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
1234 t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
1235 t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
1236 t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
1237 cpu->isar.id_aa64mmfr2 = t;
1238
1239 t = cpu->isar.id_aa64mmfr3;
1240 t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
1241 cpu->isar.id_aa64mmfr3 = t;
1242
1243 t = cpu->isar.id_aa64zfr0;
1244 t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
1245 t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
1246 t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
1247 t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* FEAT_BF16, FEAT_EBF16 */
1248 t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
1249 t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
1250 t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
1251 t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
1252 t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
1253 cpu->isar.id_aa64zfr0 = t;
1254
1255 t = cpu->isar.id_aa64dfr0;
1256 t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */
1257 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
1258 t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
1259 cpu->isar.id_aa64dfr0 = t;
1260
1261 t = cpu->isar.id_aa64smfr0;
1262 t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
1263 t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
1264 t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
1265 t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */
1266 t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
1267 t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
1268 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
1269 cpu->isar.id_aa64smfr0 = t;
1270
1271 /* Replicate the same data to the 32-bit id registers. */
1272 aa32_max_features(cpu);
1273
1274 #ifdef CONFIG_USER_ONLY
1275 /*
1276 * For usermode -cpu max we can use a larger and more efficient DCZ
1277 * blocksize since we don't have to follow what the hardware does.
1278 */
1279 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
1280 cpu->dcz_blocksize = 7; /* 512 bytes */
1281 #endif
1282 cpu->gm_blocksize = 6; /* 256 bytes */
1283
1284 cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
1285 cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
1286
1287 aarch64_add_pauth_properties(obj);
1288 aarch64_add_sve_properties(obj);
1289 aarch64_add_sme_properties(obj);
1290 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
1291 cpu_max_set_sve_max_vq, NULL, NULL);
1292 object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rme);
1293 object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz,
1294 cpu_max_set_l0gptsz, NULL, NULL);
1295 qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
1296 }
1297
1298 static const ARMCPUInfo aarch64_cpus[] = {
1299 { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
1300 { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
1301 { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
1302 { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
1303 { .name = "cortex-a710", .initfn = aarch64_a710_initfn },
1304 { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
1305 { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
1306 { .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn },
1307 { .name = "neoverse-n2", .initfn = aarch64_neoverse_n2_initfn },
1308 };
1309
1310 static void aarch64_cpu_register_types(void)
1311 {
1312 size_t i;
1313
1314 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
1315 aarch64_cpu_register(&aarch64_cpus[i]);
1316 }
1317 }
1318
1319 type_init(aarch64_cpu_register_types)
armbru's QEMU hackery