target/mips/gdbstub.c

   1 /*
   2  * MIPS gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2013 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "internal.h"
  23 #include "gdbstub/helpers.h"
  24 #include "fpu_helper.h"
  25
  26 int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
  27 {
  28     CPUMIPSState *env = cpu_env(cs);
  29
  30     if (n < 32) {
  31         return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
  32     }
  33     if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
  34         switch (n) {
  35         case 70:
  36             return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
  37         case 71:
  38             return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
  39         default:
  40             if (env->CP0_Status & (1 << CP0St_FR)) {
  41                 return gdb_get_regl(mem_buf,
  42                     env->active_fpu.fpr[n - 38].d);
  43             } else {
  44                 return gdb_get_regl(mem_buf,
  45                     env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
  46             }
  47         }
  48     }
  49     switch (n) {
  50     case 32:
  51         return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
  52     case 33:
  53         return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
  54     case 34:
  55         return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
  56     case 35:
  57         return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
  58     case 36:
  59         return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
  60     case 37:
  61         return gdb_get_regl(mem_buf, env->active_tc.PC |
  62                                      !!(env->hflags & MIPS_HFLAG_M16));
  63     case 72:
  64         return gdb_get_regl(mem_buf, 0); /* fp */
  65     case 89:
  66         return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
  67     default:
  68         if (n > 89) {
  69             return 0;
  70         }
  71         /* 16 embedded regs.  */
  72         return gdb_get_regl(mem_buf, 0);
  73     }
  74
  75     return 0;
  76 }
  77
  78 int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
  79 {
  80     CPUMIPSState *env = cpu_env(cs);
  81     target_ulong tmp;
  82
  83     tmp = ldtul_p(mem_buf);
  84
  85     if (n < 32) {
  86         env->active_tc.gpr[n] = tmp;
  87         return sizeof(target_ulong);
  88     }
  89     if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
  90         switch (n) {
  91         case 70:
  92             env->active_fpu.fcr31 = (tmp & env->active_fpu.fcr31_rw_bitmask) |
  93                   (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
  94             restore_fp_status(env);
  95             break;
  96         case 71:
  97             /* FIR is read-only.  Ignore writes.  */
  98             break;
  99         default:
 100             if (env->CP0_Status & (1 << CP0St_FR)) {
 101                 env->active_fpu.fpr[n - 38].d = tmp;
 102             } else {
 103                 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
 104             }
 105             break;
 106         }
 107         return sizeof(target_ulong);
 108     }
 109     switch (n) {
 110     case 32:
 111 #ifndef CONFIG_USER_ONLY
 112         cpu_mips_store_status(env, tmp);
 113 #endif
 114         break;
 115     case 33:
 116         env->active_tc.LO[0] = tmp;
 117         break;
 118     case 34:
 119         env->active_tc.HI[0] = tmp;
 120         break;
 121     case 35:
 122         env->CP0_BadVAddr = tmp;
 123         break;
 124     case 36:
 125 #ifndef CONFIG_USER_ONLY
 126         cpu_mips_store_cause(env, tmp);
 127 #endif
 128         break;
 129     case 37:
 130         env->active_tc.PC = tmp & ~(target_ulong)1;
 131         if (tmp & 1) {
 132             env->hflags |= MIPS_HFLAG_M16;
 133         } else {
 134             env->hflags &= ~(MIPS_HFLAG_M16);
 135         }
 136         break;
 137     case 72: /* fp, ignored */
 138         break;
 139     default:
 140         if (n > 89) {
 141             return 0;
 142         }
 143         /* Other registers are readonly.  Ignore writes.  */
 144         break;
 145     }
 146
 147     return sizeof(target_ulong);
 148 }