tcg/mips/tcg-target.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
   5  * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
   6  * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #ifndef MIPS_TCG_TARGET_H
  28 #define MIPS_TCG_TARGET_H
  29
  30 #define TCG_TARGET_INSN_UNIT_SIZE 4
  31 #define TCG_TARGET_NB_REGS 32
  32
  33 #define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
  34
  35 typedef enum {
  36     TCG_REG_ZERO = 0,
  37     TCG_REG_AT,
  38     TCG_REG_V0,
  39     TCG_REG_V1,
  40     TCG_REG_A0,
  41     TCG_REG_A1,
  42     TCG_REG_A2,
  43     TCG_REG_A3,
  44     TCG_REG_T0,
  45     TCG_REG_T1,
  46     TCG_REG_T2,
  47     TCG_REG_T3,
  48     TCG_REG_T4,
  49     TCG_REG_T5,
  50     TCG_REG_T6,
  51     TCG_REG_T7,
  52     TCG_REG_S0,
  53     TCG_REG_S1,
  54     TCG_REG_S2,
  55     TCG_REG_S3,
  56     TCG_REG_S4,
  57     TCG_REG_S5,
  58     TCG_REG_S6,
  59     TCG_REG_S7,
  60     TCG_REG_T8,
  61     TCG_REG_T9,
  62     TCG_REG_K0,
  63     TCG_REG_K1,
  64     TCG_REG_GP,
  65     TCG_REG_SP,
  66     TCG_REG_S8,
  67     TCG_REG_RA,
  68
  69     TCG_REG_CALL_STACK = TCG_REG_SP,
  70     TCG_AREG0 = TCG_REG_S8,
  71 } TCGReg;
  72
  73 /* used for function call generation */
  74 #define TCG_TARGET_STACK_ALIGN        16
  75 #if _MIPS_SIM == _ABIO32
  76 # define TCG_TARGET_CALL_STACK_OFFSET 16
  77 # define TCG_TARGET_CALL_ARG_I64      TCG_CALL_ARG_EVEN
  78 # define TCG_TARGET_CALL_RET_I128     TCG_CALL_RET_BY_REF
  79 #else
  80 # define TCG_TARGET_CALL_STACK_OFFSET 0
  81 # define TCG_TARGET_CALL_ARG_I64      TCG_CALL_ARG_NORMAL
  82 # define TCG_TARGET_CALL_RET_I128     TCG_CALL_RET_NORMAL
  83 #endif
  84 #define TCG_TARGET_CALL_ARG_I32       TCG_CALL_ARG_NORMAL
  85 #define TCG_TARGET_CALL_ARG_I128      TCG_CALL_ARG_EVEN
  86
  87 /* MOVN/MOVZ instructions detection */
  88 #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
  89     defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
  90     defined(_MIPS_ARCH_MIPS4)
  91 #define use_movnz_instructions  1
  92 #else
  93 extern bool use_movnz_instructions;
  94 #endif
  95
  96 /* MIPS32 instruction set detection */
  97 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
  98 #define use_mips32_instructions  1
  99 #else
 100 extern bool use_mips32_instructions;
 101 #endif
 102
 103 /* MIPS32R2 instruction set detection */
 104 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
 105 #define use_mips32r2_instructions  1
 106 #else
 107 extern bool use_mips32r2_instructions;
 108 #endif
 109
 110 /* MIPS32R6 instruction set detection */
 111 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
 112 #define use_mips32r6_instructions  1
 113 #else
 114 #define use_mips32r6_instructions  0
 115 #endif
 116
 117 /* optional instructions */
 118 #define TCG_TARGET_HAS_div_i32          1
 119 #define TCG_TARGET_HAS_rem_i32          1
 120 #define TCG_TARGET_HAS_not_i32          1
 121 #define TCG_TARGET_HAS_nor_i32          1
 122 #define TCG_TARGET_HAS_andc_i32         0
 123 #define TCG_TARGET_HAS_orc_i32          0
 124 #define TCG_TARGET_HAS_eqv_i32          0
 125 #define TCG_TARGET_HAS_nand_i32         0
 126 #define TCG_TARGET_HAS_mulu2_i32        (!use_mips32r6_instructions)
 127 #define TCG_TARGET_HAS_muls2_i32        (!use_mips32r6_instructions)
 128 #define TCG_TARGET_HAS_muluh_i32        1
 129 #define TCG_TARGET_HAS_mulsh_i32        1
 130 #define TCG_TARGET_HAS_bswap32_i32      1
 131 #define TCG_TARGET_HAS_negsetcond_i32   0
 132
 133 #if TCG_TARGET_REG_BITS == 64
 134 #define TCG_TARGET_HAS_add2_i32         0
 135 #define TCG_TARGET_HAS_sub2_i32         0
 136 #define TCG_TARGET_HAS_extr_i64_i32     1
 137 #define TCG_TARGET_HAS_div_i64          1
 138 #define TCG_TARGET_HAS_rem_i64          1
 139 #define TCG_TARGET_HAS_not_i64          1
 140 #define TCG_TARGET_HAS_nor_i64          1
 141 #define TCG_TARGET_HAS_andc_i64         0
 142 #define TCG_TARGET_HAS_orc_i64          0
 143 #define TCG_TARGET_HAS_eqv_i64          0
 144 #define TCG_TARGET_HAS_nand_i64         0
 145 #define TCG_TARGET_HAS_add2_i64         0
 146 #define TCG_TARGET_HAS_sub2_i64         0
 147 #define TCG_TARGET_HAS_mulu2_i64        (!use_mips32r6_instructions)
 148 #define TCG_TARGET_HAS_muls2_i64        (!use_mips32r6_instructions)
 149 #define TCG_TARGET_HAS_muluh_i64        1
 150 #define TCG_TARGET_HAS_mulsh_i64        1
 151 #define TCG_TARGET_HAS_ext32s_i64       1
 152 #define TCG_TARGET_HAS_ext32u_i64       1
 153 #define TCG_TARGET_HAS_negsetcond_i64   0
 154 #endif
 155
 156 /* optional instructions detected at runtime */
 157 #define TCG_TARGET_HAS_bswap16_i32      use_mips32r2_instructions
 158 #define TCG_TARGET_HAS_deposit_i32      use_mips32r2_instructions
 159 #define TCG_TARGET_HAS_extract_i32      use_mips32r2_instructions
 160 #define TCG_TARGET_HAS_sextract_i32     0
 161 #define TCG_TARGET_HAS_extract2_i32     0
 162 #define TCG_TARGET_HAS_ext8s_i32        use_mips32r2_instructions
 163 #define TCG_TARGET_HAS_ext16s_i32       use_mips32r2_instructions
 164 #define TCG_TARGET_HAS_rot_i32          use_mips32r2_instructions
 165 #define TCG_TARGET_HAS_clz_i32          use_mips32r2_instructions
 166 #define TCG_TARGET_HAS_ctz_i32          0
 167 #define TCG_TARGET_HAS_ctpop_i32        0
 168 #define TCG_TARGET_HAS_qemu_st8_i32     0
 169
 170 #if TCG_TARGET_REG_BITS == 64
 171 #define TCG_TARGET_HAS_bswap16_i64      use_mips32r2_instructions
 172 #define TCG_TARGET_HAS_bswap32_i64      use_mips32r2_instructions
 173 #define TCG_TARGET_HAS_bswap64_i64      use_mips32r2_instructions
 174 #define TCG_TARGET_HAS_deposit_i64      use_mips32r2_instructions
 175 #define TCG_TARGET_HAS_extract_i64      use_mips32r2_instructions
 176 #define TCG_TARGET_HAS_sextract_i64     0
 177 #define TCG_TARGET_HAS_extract2_i64     0
 178 #define TCG_TARGET_HAS_ext8s_i64        use_mips32r2_instructions
 179 #define TCG_TARGET_HAS_ext16s_i64       use_mips32r2_instructions
 180 #define TCG_TARGET_HAS_rot_i64          use_mips32r2_instructions
 181 #define TCG_TARGET_HAS_clz_i64          use_mips32r2_instructions
 182 #define TCG_TARGET_HAS_ctz_i64          0
 183 #define TCG_TARGET_HAS_ctpop_i64        0
 184 #endif
 185
 186 /* optional instructions automatically implemented */
 187 #define TCG_TARGET_HAS_ext8u_i32        0 /* andi rt, rs, 0xff   */
 188 #define TCG_TARGET_HAS_ext16u_i32       0 /* andi rt, rs, 0xffff */
 189
 190 #if TCG_TARGET_REG_BITS == 64
 191 #define TCG_TARGET_HAS_ext8u_i64        0 /* andi rt, rs, 0xff   */
 192 #define TCG_TARGET_HAS_ext16u_i64       0 /* andi rt, rs, 0xffff */
 193 #endif
 194
 195 #define TCG_TARGET_HAS_qemu_ldst_i128   0
 196
 197 #define TCG_TARGET_HAS_tst              0
 198
 199 #define TCG_TARGET_DEFAULT_MO           0
 200 #define TCG_TARGET_NEED_LDST_LABELS
 201 #define TCG_TARGET_NEED_POOL_LABELS
 202
 203 #endif