Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / tcg / riscv / tcg-target-con-str.h
blobd5c419dff1947c43db42642ea82148cdd34da785
1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define RISC-V target-specific operand constraints.
4 * Copyright (c) 2021 Linaro
5 */
7 /*
8 * Define constraint letters for register sets:
9 * REGS(letter, register_mask)
11 REGS('r', ALL_GENERAL_REGS)
14 * Define constraint letters for constants:
15 * CONST(letter, TCG_CT_CONST_* bit set)
17 CONST('I', TCG_CT_CONST_S12)
18 CONST('J', TCG_CT_CONST_J12)
19 CONST('N', TCG_CT_CONST_N12)
20 CONST('M', TCG_CT_CONST_M12)
21 CONST('Z', TCG_CT_CONST_ZERO)