tests/qtest/npcm7xx_emc-test.c

   1 /*
   2  * QTests for Nuvoton NPCM7xx EMC Modules.
   3  *
   4  * Copyright 2020 Google LLC
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  * for more details.
  15  */
  16
  17 #include "qemu/osdep.h"
  18 #include "libqos/libqos.h"
  19 #include "qapi/qmp/qdict.h"
  20 #include "qapi/qmp/qnum.h"
  21 #include "qemu/bitops.h"
  22 #include "qemu/iov.h"
  23
  24 /* Name of the emc device. */
  25 #define TYPE_NPCM7XX_EMC "npcm7xx-emc"
  26
  27 /* Timeout for various operations, in seconds. */
  28 #define TIMEOUT_SECONDS 10
  29
  30 /* Address in memory of the descriptor. */
  31 #define DESC_ADDR (1 << 20) /* 1 MiB */
  32
  33 /* Address in memory of the data packet. */
  34 #define DATA_ADDR (DESC_ADDR + 4096)
  35
  36 #define CRC_LENGTH 4
  37
  38 #define NUM_TX_DESCRIPTORS 3
  39 #define NUM_RX_DESCRIPTORS 2
  40
  41 /* Size of tx,rx test buffers. */
  42 #define TX_DATA_LEN 64
  43 #define RX_DATA_LEN 64
  44
  45 #define TX_STEP_COUNT 10000
  46 #define RX_STEP_COUNT 10000
  47
  48 /* 32-bit register indices. */
  49 typedef enum NPCM7xxPWMRegister {
  50     /* Control registers. */
  51     REG_CAMCMR,
  52     REG_CAMEN,
  53
  54     /* There are 16 CAMn[ML] registers. */
  55     REG_CAMM_BASE,
  56     REG_CAML_BASE,
  57
  58     REG_TXDLSA = 0x22,
  59     REG_RXDLSA,
  60     REG_MCMDR,
  61     REG_MIID,
  62     REG_MIIDA,
  63     REG_FFTCR,
  64     REG_TSDR,
  65     REG_RSDR,
  66     REG_DMARFC,
  67     REG_MIEN,
  68
  69     /* Status registers. */
  70     REG_MISTA,
  71     REG_MGSTA,
  72     REG_MPCNT,
  73     REG_MRPC,
  74     REG_MRPCC,
  75     REG_MREPC,
  76     REG_DMARFS,
  77     REG_CTXDSA,
  78     REG_CTXBSA,
  79     REG_CRXDSA,
  80     REG_CRXBSA,
  81
  82     NPCM7XX_NUM_EMC_REGS,
  83 } NPCM7xxPWMRegister;
  84
  85 enum { NUM_CAMML_REGS = 16 };
  86
  87 /* REG_CAMCMR fields */
  88 /* Enable CAM Compare */
  89 #define REG_CAMCMR_ECMP (1 << 4)
  90 /* Accept Unicast Packet */
  91 #define REG_CAMCMR_AUP (1 << 0)
  92
  93 /* REG_MCMDR fields */
  94 /* Software Reset */
  95 #define REG_MCMDR_SWR (1 << 24)
  96 /* Frame Transmission On */
  97 #define REG_MCMDR_TXON (1 << 8)
  98 /* Accept Long Packet */
  99 #define REG_MCMDR_ALP (1 << 1)
 100 /* Frame Reception On */
 101 #define REG_MCMDR_RXON (1 << 0)
 102
 103 /* REG_MIEN fields */
 104 /* Enable Transmit Completion Interrupt */
 105 #define REG_MIEN_ENTXCP (1 << 18)
 106 /* Enable Transmit Interrupt */
 107 #define REG_MIEN_ENTXINTR (1 << 16)
 108 /* Enable Receive Good Interrupt */
 109 #define REG_MIEN_ENRXGD (1 << 4)
 110 /* ENable Receive Interrupt */
 111 #define REG_MIEN_ENRXINTR (1 << 0)
 112
 113 /* REG_MISTA fields */
 114 /* Transmit Bus Error Interrupt */
 115 #define REG_MISTA_TXBERR (1 << 24)
 116 /* Transmit Descriptor Unavailable Interrupt */
 117 #define REG_MISTA_TDU (1 << 23)
 118 /* Transmit Completion Interrupt */
 119 #define REG_MISTA_TXCP (1 << 18)
 120 /* Transmit Interrupt */
 121 #define REG_MISTA_TXINTR (1 << 16)
 122 /* Receive Bus Error Interrupt */
 123 #define REG_MISTA_RXBERR (1 << 11)
 124 /* Receive Descriptor Unavailable Interrupt */
 125 #define REG_MISTA_RDU (1 << 10)
 126 /* DMA Early Notification Interrupt */
 127 #define REG_MISTA_DENI (1 << 9)
 128 /* Maximum Frame Length Interrupt */
 129 #define REG_MISTA_DFOI (1 << 8)
 130 /* Receive Good Interrupt */
 131 #define REG_MISTA_RXGD (1 << 4)
 132 /* Packet Too Long Interrupt */
 133 #define REG_MISTA_PTLE (1 << 3)
 134 /* Receive Interrupt */
 135 #define REG_MISTA_RXINTR (1 << 0)
 136
 137 typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc;
 138 typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc;
 139
 140 struct NPCM7xxEMCTxDesc {
 141     uint32_t flags;
 142     uint32_t txbsa;
 143     uint32_t status_and_length;
 144     uint32_t ntxdsa;
 145 };
 146
 147 struct NPCM7xxEMCRxDesc {
 148     uint32_t status_and_length;
 149     uint32_t rxbsa;
 150     uint32_t reserved;
 151     uint32_t nrxdsa;
 152 };
 153
 154 /* NPCM7xxEMCTxDesc.flags values */
 155 /* Owner: 0 = cpu, 1 = emc */
 156 #define TX_DESC_FLAG_OWNER_MASK (1 << 31)
 157 /* Transmit interrupt enable */
 158 #define TX_DESC_FLAG_INTEN (1 << 2)
 159
 160 /* NPCM7xxEMCTxDesc.status_and_length values */
 161 /* Transmission complete */
 162 #define TX_DESC_STATUS_TXCP (1 << 19)
 163 /* Transmit interrupt */
 164 #define TX_DESC_STATUS_TXINTR (1 << 16)
 165
 166 /* NPCM7xxEMCRxDesc.status_and_length values */
 167 /* Owner: 0b00 = cpu, 0b10 = emc */
 168 #define RX_DESC_STATUS_OWNER_SHIFT 30
 169 #define RX_DESC_STATUS_OWNER_MASK 0xc0000000
 170 /* Frame Reception Complete */
 171 #define RX_DESC_STATUS_RXGD (1 << 20)
 172 /* Packet too long */
 173 #define RX_DESC_STATUS_PTLE (1 << 19)
 174 /* Receive Interrupt */
 175 #define RX_DESC_STATUS_RXINTR (1 << 16)
 176
 177 #define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff)
 178
 179 typedef struct EMCModule {
 180     int rx_irq;
 181     int tx_irq;
 182     uint64_t base_addr;
 183 } EMCModule;
 184
 185 typedef struct TestData {
 186     const EMCModule *module;
 187 } TestData;
 188
 189 static const EMCModule emc_module_list[] = {
 190     {
 191         .rx_irq     = 15,
 192         .tx_irq     = 16,
 193         .base_addr  = 0xf0825000
 194     },
 195     {
 196         .rx_irq     = 114,
 197         .tx_irq     = 115,
 198         .base_addr  = 0xf0826000
 199     }
 200 };
 201
 202 /* Returns the index of the EMC module. */
 203 static int emc_module_index(const EMCModule *mod)
 204 {
 205     ptrdiff_t diff = mod - emc_module_list;
 206
 207     g_assert_true(diff >= 0 && diff < ARRAY_SIZE(emc_module_list));
 208
 209     return diff;
 210 }
 211
 212 #ifndef _WIN32
 213 static void packet_test_clear(void *sockets)
 214 {
 215     int *test_sockets = sockets;
 216
 217     close(test_sockets[0]);
 218     g_free(test_sockets);
 219 }
 220
 221 static int *packet_test_init(int module_num, GString *cmd_line)
 222 {
 223     int *test_sockets = g_new(int, 2);
 224     int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets);
 225     g_assert_cmpint(ret, != , -1);
 226
 227     /*
 228      * KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
 229      * in the 'model' field to specify the device to match.
 230      */
 231     g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d "
 232                            "-nic user,model=npcm7xx-emc "
 233                            "-nic user,model=npcm-gmac "
 234                            "-nic user,model=npcm-gmac",
 235                            test_sockets[1], module_num);
 236
 237     g_test_queue_destroy(packet_test_clear, test_sockets);
 238     return test_sockets;
 239 }
 240 #endif /* _WIN32 */
 241
 242 static uint32_t emc_read(QTestState *qts, const EMCModule *mod,
 243                          NPCM7xxPWMRegister regno)
 244 {
 245     return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t));
 246 }
 247
 248 #ifndef _WIN32
 249 static void emc_write(QTestState *qts, const EMCModule *mod,
 250                       NPCM7xxPWMRegister regno, uint32_t value)
 251 {
 252     qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value);
 253 }
 254
 255 static void emc_read_tx_desc(QTestState *qts, uint32_t addr,
 256                              NPCM7xxEMCTxDesc *desc)
 257 {
 258     qtest_memread(qts, addr, desc, sizeof(*desc));
 259     desc->flags = le32_to_cpu(desc->flags);
 260     desc->txbsa = le32_to_cpu(desc->txbsa);
 261     desc->status_and_length = le32_to_cpu(desc->status_and_length);
 262     desc->ntxdsa = le32_to_cpu(desc->ntxdsa);
 263 }
 264
 265 static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *desc,
 266                               uint32_t addr)
 267 {
 268     NPCM7xxEMCTxDesc le_desc;
 269
 270     le_desc.flags = cpu_to_le32(desc->flags);
 271     le_desc.txbsa = cpu_to_le32(desc->txbsa);
 272     le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
 273     le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa);
 274     qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));
 275 }
 276
 277 static void emc_read_rx_desc(QTestState *qts, uint32_t addr,
 278                              NPCM7xxEMCRxDesc *desc)
 279 {
 280     qtest_memread(qts, addr, desc, sizeof(*desc));
 281     desc->status_and_length = le32_to_cpu(desc->status_and_length);
 282     desc->rxbsa = le32_to_cpu(desc->rxbsa);
 283     desc->reserved = le32_to_cpu(desc->reserved);
 284     desc->nrxdsa = le32_to_cpu(desc->nrxdsa);
 285 }
 286
 287 static void emc_write_rx_desc(QTestState *qts, const NPCM7xxEMCRxDesc *desc,
 288                               uint32_t addr)
 289 {
 290     NPCM7xxEMCRxDesc le_desc;
 291
 292     le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
 293     le_desc.rxbsa = cpu_to_le32(desc->rxbsa);
 294     le_desc.reserved = cpu_to_le32(desc->reserved);
 295     le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa);
 296     qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));
 297 }
 298
 299 /*
 300  * Reset the EMC module.
 301  * The module must be reset before, e.g., TXDLSA,RXDLSA are changed.
 302  */
 303 static bool emc_soft_reset(QTestState *qts, const EMCModule *mod)
 304 {
 305     uint32_t val;
 306     uint64_t end_time;
 307
 308     emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR);
 309
 310     /*
 311      * Wait for device to reset as the linux driver does.
 312      * During reset the AHB reads 0 for all registers. So first wait for
 313      * something that resets to non-zero, and then wait for SWR becoming 0.
 314      */
 315     end_time = g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
 316
 317     do {
 318         qtest_clock_step(qts, 100);
 319         val = emc_read(qts, mod, REG_FFTCR);
 320     } while (val == 0 && g_get_monotonic_time() < end_time);
 321     if (val != 0) {
 322         do {
 323             qtest_clock_step(qts, 100);
 324             val = emc_read(qts, mod, REG_MCMDR);
 325             if ((val & REG_MCMDR_SWR) == 0) {
 326                 /*
 327                  * N.B. The CAMs have been reset here, so macaddr matching of
 328                  * incoming packets will not work.
 329                  */
 330                 return true;
 331             }
 332         } while (g_get_monotonic_time() < end_time);
 333     }
 334
 335     g_message("%s: Timeout expired", __func__);
 336     return false;
 337 }
 338 #endif /* _WIN32 */
 339
 340 /* Check emc registers are reset to default value. */
 341 static void test_init(gconstpointer test_data)
 342 {
 343     const TestData *td = test_data;
 344     const EMCModule *mod = td->module;
 345     QTestState *qts = qtest_init("-machine quanta-gsj");
 346     int i;
 347
 348 #define CHECK_REG(regno, value) \
 349   do { \
 350     g_assert_cmphex(emc_read(qts, mod, (regno)), ==, (value)); \
 351   } while (0)
 352
 353     CHECK_REG(REG_CAMCMR, 0);
 354     CHECK_REG(REG_CAMEN, 0);
 355     CHECK_REG(REG_TXDLSA, 0xfffffffc);
 356     CHECK_REG(REG_RXDLSA, 0xfffffffc);
 357     CHECK_REG(REG_MCMDR, 0);
 358     CHECK_REG(REG_MIID, 0);
 359     CHECK_REG(REG_MIIDA, 0x00900000);
 360     CHECK_REG(REG_FFTCR, 0x0101);
 361     CHECK_REG(REG_DMARFC, 0x0800);
 362     CHECK_REG(REG_MIEN, 0);
 363     CHECK_REG(REG_MISTA, 0);
 364     CHECK_REG(REG_MGSTA, 0);
 365     CHECK_REG(REG_MPCNT, 0x7fff);
 366     CHECK_REG(REG_MRPC, 0);
 367     CHECK_REG(REG_MRPCC, 0);
 368     CHECK_REG(REG_MREPC, 0);
 369     CHECK_REG(REG_DMARFS, 0);
 370     CHECK_REG(REG_CTXDSA, 0);
 371     CHECK_REG(REG_CTXBSA, 0);
 372     CHECK_REG(REG_CRXDSA, 0);
 373     CHECK_REG(REG_CRXBSA, 0);
 374
 375 #undef CHECK_REG
 376
 377     /* Skip over the MAC address registers, which is BASE+0 */
 378     for (i = 1; i < NUM_CAMML_REGS; ++i) {
 379         g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), ==,
 380                          0);
 381         g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), ==,
 382                          0);
 383     }
 384
 385     qtest_quit(qts);
 386 }
 387
 388 #ifndef _WIN32
 389 static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step,
 390                          bool is_tx)
 391 {
 392     uint64_t end_time =
 393         g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
 394
 395     do {
 396         if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) {
 397             return true;
 398         }
 399         qtest_clock_step(qts, step);
 400     } while (g_get_monotonic_time() < end_time);
 401
 402     g_message("%s: Timeout expired", __func__);
 403     return false;
 404 }
 405
 406 static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step,
 407                            uint32_t flag)
 408 {
 409     uint64_t end_time =
 410         g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
 411
 412     do {
 413         uint32_t mista = emc_read(qts, mod, REG_MISTA);
 414         if (mista & flag) {
 415             return true;
 416         }
 417         qtest_clock_step(qts, step);
 418     } while (g_get_monotonic_time() < end_time);
 419
 420     g_message("%s: Timeout expired", __func__);
 421     return false;
 422 }
 423
 424 static bool wait_socket_readable(int fd)
 425 {
 426     fd_set read_fds;
 427     struct timeval tv;
 428     int rv;
 429
 430     FD_ZERO(&read_fds);
 431     FD_SET(fd, &read_fds);
 432     tv.tv_sec = TIMEOUT_SECONDS;
 433     tv.tv_usec = 0;
 434     rv = select(fd + 1, &read_fds, NULL, NULL, &tv);
 435     if (rv == -1) {
 436         perror("select");
 437     } else if (rv == 0) {
 438         g_message("%s: Timeout expired", __func__);
 439     }
 440     return rv == 1;
 441 }
 442
 443 /* Initialize *desc (in host endian format). */
 444 static void init_tx_desc(NPCM7xxEMCTxDesc *desc, size_t count,
 445                          uint32_t desc_addr)
 446 {
 447     g_assert(count >= 2);
 448     memset(&desc[0], 0, sizeof(*desc) * count);
 449     /* Leave the last one alone, owned by the cpu -> stops transmission. */
 450     for (size_t i = 0; i < count - 1; ++i) {
 451         desc[i].flags =
 452             (TX_DESC_FLAG_OWNER_MASK | /* owner = 1: emc */
 453              TX_DESC_FLAG_INTEN |
 454              0 | /* crc append = 0 */
 455              0 /* padding enable = 0 */);
 456         desc[i].status_and_length =
 457             (0 | /* collision count = 0 */
 458              0 | /* SQE = 0 */
 459              0 | /* PAU = 0 */
 460              0 | /* TXHA = 0 */
 461              0 | /* LC = 0 */
 462              0 | /* TXABT = 0 */
 463              0 | /* NCS = 0 */
 464              0 | /* EXDEF = 0 */
 465              0 | /* TXCP = 0 */
 466              0 | /* DEF = 0 */
 467              0 | /* TXINTR = 0 */
 468              0 /* length filled in later */);
 469         desc[i].ntxdsa = desc_addr + (i + 1) * sizeof(*desc);
 470     }
 471 }
 472
 473 static void enable_tx(QTestState *qts, const EMCModule *mod,
 474                       const NPCM7xxEMCTxDesc *desc, size_t count,
 475                       uint32_t desc_addr, uint32_t mien_flags)
 476 {
 477     /* Write the descriptors to guest memory. */
 478     for (size_t i = 0; i < count; ++i) {
 479         emc_write_tx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));
 480     }
 481
 482     /* Trigger sending the packet. */
 483     /* The module must be reset before changing TXDLSA. */
 484     g_assert(emc_soft_reset(qts, mod));
 485     emc_write(qts, mod, REG_TXDLSA, desc_addr);
 486     emc_write(qts, mod, REG_CTXDSA, ~0);
 487     emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags);
 488     {
 489         uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);
 490         mcmdr |= REG_MCMDR_TXON;
 491         emc_write(qts, mod, REG_MCMDR, mcmdr);
 492     }
 493 }
 494
 495 static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd,
 496                              bool with_irq, uint32_t desc_addr,
 497                              uint32_t next_desc_addr,
 498                              const char *test_data, int test_size)
 499 {
 500     NPCM7xxEMCTxDesc result_desc;
 501     uint32_t expected_mask, expected_value, recv_len;
 502     int ret;
 503     char buffer[TX_DATA_LEN];
 504
 505     g_assert(wait_socket_readable(fd));
 506
 507     /* Read the descriptor back. */
 508     emc_read_tx_desc(qts, desc_addr, &result_desc);
 509     /* Descriptor should be owned by cpu now. */
 510     g_assert((result_desc.flags & TX_DESC_FLAG_OWNER_MASK) == 0);
 511     /* Test the status bits, ignoring the length field. */
 512     expected_mask = 0xffff << 16;
 513     expected_value = TX_DESC_STATUS_TXCP;
 514     if (with_irq) {
 515         expected_value |= TX_DESC_STATUS_TXINTR;
 516     }
 517     g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
 518                     expected_value);
 519
 520     /* Check data sent to the backend. */
 521     recv_len = ~0;
 522     ret = recv(fd, &recv_len, sizeof(recv_len), MSG_DONTWAIT);
 523     g_assert_cmpint(ret, == , sizeof(recv_len));
 524
 525     g_assert(wait_socket_readable(fd));
 526     memset(buffer, 0xff, sizeof(buffer));
 527     ret = recv(fd, buffer, test_size, MSG_DONTWAIT);
 528     g_assert_cmpmem(buffer, ret, test_data, test_size);
 529 }
 530
 531 static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd,
 532                             bool with_irq)
 533 {
 534     NPCM7xxEMCTxDesc desc[NUM_TX_DESCRIPTORS];
 535     uint32_t desc_addr = DESC_ADDR;
 536     static const char test1_data[] = "TEST1";
 537     static const char test2_data[] = "Testing 1 2 3 ...";
 538     uint32_t data1_addr = DATA_ADDR;
 539     uint32_t data2_addr = data1_addr + sizeof(test1_data);
 540     bool got_tdu;
 541     uint32_t end_desc_addr;
 542
 543     /* Prepare test data buffer. */
 544     qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data));
 545     qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data));
 546
 547     init_tx_desc(&desc[0], NUM_TX_DESCRIPTORS, desc_addr);
 548     desc[0].txbsa = data1_addr;
 549     desc[0].status_and_length |= sizeof(test1_data);
 550     desc[1].txbsa = data2_addr;
 551     desc[1].status_and_length |= sizeof(test2_data);
 552
 553     enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr,
 554               with_irq ? REG_MIEN_ENTXINTR : 0);
 555
 556     /* Prod the device to send the packet. */
 557     emc_write(qts, mod, REG_TSDR, 1);
 558
 559     /*
 560      * It's problematic to observe the interrupt for each packet.
 561      * Instead just wait until all the packets go out.
 562      */
 563     got_tdu = false;
 564     while (!got_tdu) {
 565         if (with_irq) {
 566             g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT,
 567                                        /*is_tx=*/true));
 568         } else {
 569             g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT,
 570                                          REG_MISTA_TXINTR));
 571         }
 572         got_tdu = !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU);
 573         /* If we don't have TDU yet, reset the interrupt. */
 574         if (!got_tdu) {
 575             emc_write(qts, mod, REG_MISTA,
 576                       emc_read(qts, mod, REG_MISTA) & 0xffff0000);
 577         }
 578     }
 579
 580     end_desc_addr = desc_addr + 2 * sizeof(desc[0]);
 581     g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), ==, end_desc_addr);
 582     g_assert_cmphex(emc_read(qts, mod, REG_MISTA), ==,
 583                     REG_MISTA_TXCP | REG_MISTA_TXINTR | REG_MISTA_TDU);
 584
 585     emc_send_verify1(qts, mod, fd, with_irq,
 586                      desc_addr, end_desc_addr,
 587                      test1_data, sizeof(test1_data));
 588     emc_send_verify1(qts, mod, fd, with_irq,
 589                      desc_addr + sizeof(desc[0]), end_desc_addr,
 590                      test2_data, sizeof(test2_data));
 591 }
 592
 593 /* Initialize *desc (in host endian format). */
 594 static void init_rx_desc(NPCM7xxEMCRxDesc *desc, size_t count,
 595                          uint32_t desc_addr, uint32_t data_addr)
 596 {
 597     g_assert_true(count >= 2);
 598     memset(desc, 0, sizeof(*desc) * count);
 599     desc[0].rxbsa = data_addr;
 600     desc[0].status_and_length =
 601         (0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner = 10: emc */
 602          0 | /* RP = 0 */
 603          0 | /* ALIE = 0 */
 604          0 | /* RXGD = 0 */
 605          0 | /* PTLE = 0 */
 606          0 | /* CRCE = 0 */
 607          0 | /* RXINTR = 0 */
 608          0   /* length (filled in later) */);
 609     /* Leave the last one alone, owned by the cpu -> stops transmission. */
 610     desc[0].nrxdsa = desc_addr + sizeof(*desc);
 611 }
 612
 613 static void enable_rx(QTestState *qts, const EMCModule *mod,
 614                       const NPCM7xxEMCRxDesc *desc, size_t count,
 615                       uint32_t desc_addr, uint32_t mien_flags,
 616                       uint32_t mcmdr_flags)
 617 {
 618     /*
 619      * Write the descriptor to guest memory.
 620      * FWIW, IWBN if the docs said the buffer needs to be at least DMARFC
 621      * bytes.
 622      */
 623     for (size_t i = 0; i < count; ++i) {
 624         emc_write_rx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));
 625     }
 626
 627     /* Trigger receiving the packet. */
 628     /* The module must be reset before changing RXDLSA. */
 629     g_assert(emc_soft_reset(qts, mod));
 630     emc_write(qts, mod, REG_RXDLSA, desc_addr);
 631     emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags);
 632
 633     /*
 634      * We don't know what the device's macaddr is, so just accept all
 635      * unicast packets (AUP).
 636      */
 637     emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP);
 638     emc_write(qts, mod, REG_CAMEN, 1 << 0);
 639     {
 640         uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);
 641         mcmdr |= REG_MCMDR_RXON | mcmdr_flags;
 642         emc_write(qts, mod, REG_MCMDR, mcmdr);
 643     }
 644 }
 645
 646 static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd,
 647                             bool with_irq, bool pump_rsdr)
 648 {
 649     NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS];
 650     uint32_t desc_addr = DESC_ADDR;
 651     uint32_t data_addr = DATA_ADDR;
 652     int ret;
 653     uint32_t expected_mask, expected_value;
 654     NPCM7xxEMCRxDesc result_desc;
 655
 656     /* Prepare test data buffer. */
 657     const char test[RX_DATA_LEN] = "TEST";
 658     int len = htonl(sizeof(test));
 659     const struct iovec iov[] = {
 660         {
 661             .iov_base = &len,
 662             .iov_len = sizeof(len),
 663         },{
 664             .iov_base = (char *) test,
 665             .iov_len = sizeof(test),
 666         },
 667     };
 668
 669     /*
 670      * Reset the device BEFORE sending a test packet, otherwise the packet
 671      * may get swallowed by an active device of an earlier test.
 672      */
 673     init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr);
 674     enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,
 675               with_irq ? REG_MIEN_ENRXINTR : 0, 0);
 676
 677     /*
 678      * If requested, prod the device to accept a packet.
 679      * This isn't necessary, the linux driver doesn't do this.
 680      * Test doing/not-doing this for robustness.
 681      */
 682     if (pump_rsdr) {
 683         emc_write(qts, mod, REG_RSDR, 1);
 684     }
 685
 686     /* Send test packet to device's socket. */
 687     ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test));
 688     g_assert_cmpint(ret, == , sizeof(test) + sizeof(len));
 689
 690     /* Wait for RX interrupt. */
 691     if (with_irq) {
 692         g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));
 693     } else {
 694         g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RXGD));
 695     }
 696
 697     g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), ==,
 698                     desc_addr + sizeof(desc[0]));
 699
 700     expected_mask = 0xffff;
 701     expected_value = (REG_MISTA_DENI |
 702                       REG_MISTA_RXGD |
 703                       REG_MISTA_RXINTR);
 704     g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask),
 705                     ==, expected_value);
 706
 707     /* Read the descriptor back. */
 708     emc_read_rx_desc(qts, desc_addr, &result_desc);
 709     /* Descriptor should be owned by cpu now. */
 710     g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0);
 711     /* Test the status bits, ignoring the length field. */
 712     expected_mask = 0xffff << 16;
 713     expected_value = RX_DESC_STATUS_RXGD;
 714     if (with_irq) {
 715         expected_value |= RX_DESC_STATUS_RXINTR;
 716     }
 717     g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
 718                     expected_value);
 719     g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==,
 720                     RX_DATA_LEN + CRC_LENGTH);
 721
 722     {
 723         char buffer[RX_DATA_LEN];
 724         qtest_memread(qts, data_addr, buffer, sizeof(buffer));
 725         g_assert_cmpstr(buffer, == , "TEST");
 726     }
 727 }
 728
 729 static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd)
 730 {
 731     NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS];
 732     uint32_t desc_addr = DESC_ADDR;
 733     uint32_t data_addr = DATA_ADDR;
 734     int ret;
 735     NPCM7xxEMCRxDesc result_desc;
 736     uint32_t expected_mask, expected_value;
 737
 738     /* Prepare test data buffer. */
 739 #define PTLE_DATA_LEN 1600
 740     char test_data[PTLE_DATA_LEN];
 741     int len = htonl(sizeof(test_data));
 742     const struct iovec iov[] = {
 743         {
 744             .iov_base = &len,
 745             .iov_len = sizeof(len),
 746         },{
 747             .iov_base = (char *) test_data,
 748             .iov_len = sizeof(test_data),
 749         },
 750     };
 751     memset(test_data, 42, sizeof(test_data));
 752
 753     /*
 754      * Reset the device BEFORE sending a test packet, otherwise the packet
 755      * may get swallowed by an active device of an earlier test.
 756      */
 757     init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr);
 758     enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,
 759               REG_MIEN_ENRXINTR, REG_MCMDR_ALP);
 760
 761     /* Send test packet to device's socket. */
 762     ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test_data));
 763     g_assert_cmpint(ret, == , sizeof(test_data) + sizeof(len));
 764
 765     /* Wait for RX interrupt. */
 766     g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));
 767
 768     /* Read the descriptor back. */
 769     emc_read_rx_desc(qts, desc_addr, &result_desc);
 770     /* Descriptor should be owned by cpu now. */
 771     g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0);
 772     /* Test the status bits, ignoring the length field. */
 773     expected_mask = 0xffff << 16;
 774     expected_value = (RX_DESC_STATUS_RXGD |
 775                       RX_DESC_STATUS_PTLE |
 776                       RX_DESC_STATUS_RXINTR);
 777     g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
 778                     expected_value);
 779     g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==,
 780                     PTLE_DATA_LEN + CRC_LENGTH);
 781
 782     {
 783         char buffer[PTLE_DATA_LEN];
 784         qtest_memread(qts, data_addr, buffer, sizeof(buffer));
 785         g_assert(memcmp(buffer, test_data, PTLE_DATA_LEN) == 0);
 786     }
 787 }
 788
 789 static void test_tx(gconstpointer test_data)
 790 {
 791     const TestData *td = test_data;
 792     g_autoptr(GString) cmd_line = g_string_new("-machine quanta-gsj");
 793     int *test_sockets = packet_test_init(emc_module_index(td->module),
 794                                          cmd_line);
 795     QTestState *qts = qtest_init(cmd_line->str);
 796
 797     /*
 798      * TODO: For pedantic correctness test_sockets[0] should be closed after
 799      * the fork and before the exec, but that will require some harness
 800      * improvements.
 801      */
 802     close(test_sockets[1]);
 803     /* Defensive programming */
 804     test_sockets[1] = -1;
 805
 806     qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 807
 808     emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/false);
 809     emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/true);
 810
 811     qtest_quit(qts);
 812 }
 813
 814 static void test_rx(gconstpointer test_data)
 815 {
 816     const TestData *td = test_data;
 817     g_autoptr(GString) cmd_line = g_string_new("-machine quanta-gsj");
 818     int *test_sockets = packet_test_init(emc_module_index(td->module),
 819                                          cmd_line);
 820     QTestState *qts = qtest_init(cmd_line->str);
 821
 822     /*
 823      * TODO: For pedantic correctness test_sockets[0] should be closed after
 824      * the fork and before the exec, but that will require some harness
 825      * improvements.
 826      */
 827     close(test_sockets[1]);
 828     /* Defensive programming */
 829     test_sockets[1] = -1;
 830
 831     qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 832
 833     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false,
 834                     /*pump_rsdr=*/false);
 835     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false,
 836                     /*pump_rsdr=*/true);
 837     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true,
 838                     /*pump_rsdr=*/false);
 839     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true,
 840                     /*pump_rsdr=*/true);
 841     emc_test_ptle(qts, td->module, test_sockets[0]);
 842
 843     qtest_quit(qts);
 844 }
 845 #endif /* _WIN32 */
 846
 847 static void emc_add_test(const char *name, const TestData* td,
 848                          GTestDataFunc fn)
 849 {
 850     g_autofree char *full_name = g_strdup_printf(
 851             "npcm7xx_emc/emc[%d]/%s", emc_module_index(td->module), name);
 852     qtest_add_data_func(full_name, td, fn);
 853 }
 854 #define add_test(name, td) emc_add_test(#name, td, test_##name)
 855
 856 int main(int argc, char **argv)
 857 {
 858     TestData test_data_list[ARRAY_SIZE(emc_module_list)];
 859
 860     g_test_init(&argc, &argv, NULL);
 861
 862     for (int i = 0; i < ARRAY_SIZE(emc_module_list); ++i) {
 863         TestData *td = &test_data_list[i];
 864
 865         td->module = &emc_module_list[i];
 866
 867         add_test(init, td);
 868 #ifndef _WIN32
 869         add_test(tx, td);
 870         add_test(rx, td);
 871 #endif
 872     }
 873
 874     return g_test_run();
 875 }