include/hw/riscv/sifive_e.h

   1 /*
   2  * SiFive E series machine interface
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef HW_SIFIVE_E_H
  20 #define HW_SIFIVE_E_H
  21
  22 #include "hw/riscv/riscv_hart.h"
  23 #include "hw/riscv/sifive_cpu.h"
  24 #include "hw/riscv/sifive_gpio.h"
  25
  26 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
  27 #define RISCV_E_SOC(obj) \
  28     OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC)
  29
  30 typedef struct SiFiveESoCState {
  31     /*< private >*/
  32     DeviceState parent_obj;
  33
  34     /*< public >*/
  35     RISCVHartArrayState cpus;
  36     DeviceState *plic;
  37     SIFIVEGPIOState gpio;
  38     MemoryRegion xip_mem;
  39     MemoryRegion mask_rom;
  40 } SiFiveESoCState;
  41
  42 typedef struct SiFiveEState {
  43     /*< private >*/
  44     SysBusDevice parent_obj;
  45
  46     /*< public >*/
  47     SiFiveESoCState soc;
  48 } SiFiveEState;
  49
  50 #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
  51 #define RISCV_E_MACHINE(obj) \
  52     OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
  53
  54 enum {
  55     SIFIVE_E_DEBUG,
  56     SIFIVE_E_MROM,
  57     SIFIVE_E_OTP,
  58     SIFIVE_E_CLINT,
  59     SIFIVE_E_PLIC,
  60     SIFIVE_E_AON,
  61     SIFIVE_E_PRCI,
  62     SIFIVE_E_OTP_CTRL,
  63     SIFIVE_E_GPIO0,
  64     SIFIVE_E_UART0,
  65     SIFIVE_E_QSPI0,
  66     SIFIVE_E_PWM0,
  67     SIFIVE_E_UART1,
  68     SIFIVE_E_QSPI1,
  69     SIFIVE_E_PWM1,
  70     SIFIVE_E_QSPI2,
  71     SIFIVE_E_PWM2,
  72     SIFIVE_E_XIP,
  73     SIFIVE_E_DTIM
  74 };
  75
  76 enum {
  77     SIFIVE_E_UART0_IRQ  = 3,
  78     SIFIVE_E_UART1_IRQ  = 4,
  79     SIFIVE_E_GPIO0_IRQ0 = 8
  80 };
  81
  82 #define SIFIVE_E_PLIC_HART_CONFIG "M"
  83 #define SIFIVE_E_PLIC_NUM_SOURCES 127
  84 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7
  85 #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
  86 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000
  87 #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
  88 #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
  89 #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000
  90 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000
  91
  92 #endif