include/hw/riscv/sifive_e_prci.h

   1 /*
   2  * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef HW_SIFIVE_E_PRCI_H
  20 #define HW_SIFIVE_E_PRCI_H
  21
  22 enum {
  23     SIFIVE_E_PRCI_HFROSCCFG = 0x0,
  24     SIFIVE_E_PRCI_HFXOSCCFG = 0x4,
  25     SIFIVE_E_PRCI_PLLCFG    = 0x8,
  26     SIFIVE_E_PRCI_PLLOUTDIV = 0xC
  27 };
  28
  29 enum {
  30     SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31),
  31     SIFIVE_E_PRCI_HFROSCCFG_EN  = (1 << 30)
  32 };
  33
  34 enum {
  35     SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31),
  36     SIFIVE_E_PRCI_HFXOSCCFG_EN  = (1 << 30)
  37 };
  38
  39 enum {
  40     SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16),
  41     SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17),
  42     SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18),
  43     SIFIVE_E_PRCI_PLLCFG_LOCK   = (1 << 31)
  44 };
  45
  46 enum {
  47     SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
  48 };
  49
  50 #define SIFIVE_E_PRCI_REG_SIZE  0x1000
  51
  52 #define TYPE_SIFIVE_E_PRCI      "riscv.sifive.e.prci"
  53
  54 #define SIFIVE_E_PRCI(obj) \
  55     OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI)
  56
  57 typedef struct SiFiveEPRCIState {
  58     /*< private >*/
  59     SysBusDevice parent_obj;
  60
  61     /*< public >*/
  62     MemoryRegion mmio;
  63     uint32_t hfrosccfg;
  64     uint32_t hfxosccfg;
  65     uint32_t pllcfg;
  66     uint32_t plloutdiv;
  67 } SiFiveEPRCIState;
  68
  69 DeviceState *sifive_e_prci_create(hwaddr addr);
  70
  71 #endif