MAINTAINERS: Make section QOM cover hw/core/*bus.c as well
[qemu/armbru.git] / include / hw / riscv / sifive_test.h
blob1ec416ac1ba98edec06720e68e3a4d9a69cf17f9
1 /*
2 * QEMU Test Finisher interface
4 * Copyright (c) 2018 SiFive, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef HW_SIFIVE_TEST_H
20 #define HW_SIFIVE_TEST_H
22 #include "hw/sysbus.h"
24 #define TYPE_SIFIVE_TEST "riscv.sifive.test"
26 #define SIFIVE_TEST(obj) \
27 OBJECT_CHECK(SiFiveTestState, (obj), TYPE_SIFIVE_TEST)
29 typedef struct SiFiveTestState {
30 /*< private >*/
31 SysBusDevice parent_obj;
33 /*< public >*/
34 MemoryRegion mmio;
35 } SiFiveTestState;
37 enum {
38 FINISHER_FAIL = 0x3333,
39 FINISHER_PASS = 0x5555,
40 FINISHER_RESET = 0x7777
43 DeviceState *sifive_test_create(hwaddr addr);
45 #endif