hw/arm/mainstone.c

   1 /*
   2  * PXA270-based Intel Mainstone platforms.
   3  *
   4  * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
   5  *                                    <akuster@mvista.com>
   6  *
   7  * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
   8  *
   9  * This code is licensed under the GNU GPL v2.
  10  *
  11  * Contributions after 2012-01-13 are licensed under the terms of the
  12  * GNU GPL, version 2 or (at your option) any later version.
  13  */
  14 #include "qemu/osdep.h"
  15 #include "qemu/error-report.h"
  16 #include "qapi/error.h"
  17 #include "hw/arm/pxa.h"
  18 #include "hw/arm/boot.h"
  19 #include "net/net.h"
  20 #include "hw/net/smc91c111.h"
  21 #include "hw/boards.h"
  22 #include "hw/block/flash.h"
  23 #include "hw/sysbus.h"
  24 #include "exec/address-spaces.h"
  25 #include "cpu.h"
  26
  27 /* Device addresses */
  28 #define MST_FPGA_PHYS   0x08000000
  29 #define MST_ETH_PHYS    0x10000300
  30 #define MST_FLASH_0             0x00000000
  31 #define MST_FLASH_1             0x04000000
  32
  33 /* IRQ definitions */
  34 #define MMC_IRQ       0
  35 #define USIM_IRQ      1
  36 #define USBC_IRQ      2
  37 #define ETHERNET_IRQ  3
  38 #define AC97_IRQ      4
  39 #define PEN_IRQ       5
  40 #define MSINS_IRQ     6
  41 #define EXBRD_IRQ     7
  42 #define S0_CD_IRQ     9
  43 #define S0_STSCHG_IRQ 10
  44 #define S0_IRQ        11
  45 #define S1_CD_IRQ     13
  46 #define S1_STSCHG_IRQ 14
  47 #define S1_IRQ        15
  48
  49 static const struct keymap map[0xE0] = {
  50     [0 ... 0xDF] = { -1, -1 },
  51     [0x1e] = {0,0}, /* a */
  52     [0x30] = {0,1}, /* b */
  53     [0x2e] = {0,2}, /* c */
  54     [0x20] = {0,3}, /* d */
  55     [0x12] = {0,4}, /* e */
  56     [0x21] = {0,5}, /* f */
  57     [0x22] = {1,0}, /* g */
  58     [0x23] = {1,1}, /* h */
  59     [0x17] = {1,2}, /* i */
  60     [0x24] = {1,3}, /* j */
  61     [0x25] = {1,4}, /* k */
  62     [0x26] = {1,5}, /* l */
  63     [0x32] = {2,0}, /* m */
  64     [0x31] = {2,1}, /* n */
  65     [0x18] = {2,2}, /* o */
  66     [0x19] = {2,3}, /* p */
  67     [0x10] = {2,4}, /* q */
  68     [0x13] = {2,5}, /* r */
  69     [0x1f] = {3,0}, /* s */
  70     [0x14] = {3,1}, /* t */
  71     [0x16] = {3,2}, /* u */
  72     [0x2f] = {3,3}, /* v */
  73     [0x11] = {3,4}, /* w */
  74     [0x2d] = {3,5}, /* x */
  75     [0x34] = {4,0}, /* . */
  76     [0x15] = {4,2}, /* y */
  77     [0x2c] = {4,3}, /* z */
  78     [0x35] = {4,4}, /* / */
  79     [0xc7] = {5,0}, /* Home */
  80     [0x2a] = {5,1}, /* shift */
  81     /*
  82      * There are two matrix positions which map to space,
  83      * but QEMU can only use one of them for the reverse
  84      * mapping, so simply use the second one.
  85      */
  86     /* [0x39] = {5,2}, space */
  87     [0x39] = {5,3}, /* space */
  88     /*
  89      * Matrix position {5,4} and other keys are missing here.
  90      * TODO: Compare with Linux code and test real hardware.
  91      */
  92     [0x1c] = {5,4}, /* enter */
  93     [0x0e] = {5,5}, /* backspace */
  94     [0xc8] = {6,0}, /* up */
  95     [0xd0] = {6,1}, /* down */
  96     [0xcb] = {6,2}, /* left */
  97     [0xcd] = {6,3}, /* right */
  98 };
  99
 100 enum mainstone_model_e { mainstone };
 101
 102 #define MAINSTONE_RAM   0x04000000
 103 #define MAINSTONE_ROM   0x00800000
 104 #define MAINSTONE_FLASH 0x02000000
 105
 106 static struct arm_boot_info mainstone_binfo = {
 107     .loader_start = PXA2XX_SDRAM_BASE,
 108     .ram_size = 0x04000000,
 109 };
 110
 111 static void mainstone_common_init(MemoryRegion *address_space_mem,
 112                                   MachineState *machine,
 113                                   enum mainstone_model_e model, int arm_id)
 114 {
 115     uint32_t sector_len = 256 * 1024;
 116     hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
 117     PXA2xxState *mpu;
 118     DeviceState *mst_irq;
 119     DriveInfo *dinfo;
 120     int i;
 121     MemoryRegion *rom = g_new(MemoryRegion, 1);
 122
 123     /* Setup CPU & memory */
 124     mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
 125                       machine->cpu_type);
 126     memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
 127                            &error_fatal);
 128     memory_region_add_subregion(address_space_mem, 0, rom);
 129
 130     /* There are two 32MiB flash devices on the board */
 131     for (i = 0; i < 2; i ++) {
 132         dinfo = drive_get(IF_PFLASH, 0, i);
 133         if (!pflash_cfi01_register(mainstone_flash_base[i],
 134                                    i ? "mainstone.flash1" : "mainstone.flash0",
 135                                    MAINSTONE_FLASH,
 136                                    dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 137                                    sector_len, 4, 0, 0, 0, 0, 0)) {
 138             error_report("Error registering flash memory");
 139             exit(1);
 140         }
 141     }
 142
 143     mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
 144                     qdev_get_gpio_in(mpu->gpio, 0));
 145
 146     /* setup keypad */
 147     pxa27x_register_keypad(mpu->kp, map, 0xe0);
 148
 149     /* MMC/SD host */
 150     pxa2xx_mmci_handlers(mpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
 151
 152     pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[0],
 153             qdev_get_gpio_in(mst_irq, S0_IRQ),
 154             qdev_get_gpio_in(mst_irq, S0_CD_IRQ));
 155     pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[1],
 156             qdev_get_gpio_in(mst_irq, S1_IRQ),
 157             qdev_get_gpio_in(mst_irq, S1_CD_IRQ));
 158
 159     smc91c111_init(&nd_table[0], MST_ETH_PHYS,
 160                     qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
 161
 162     mainstone_binfo.board_id = arm_id;
 163     arm_load_kernel(mpu->cpu, machine, &mainstone_binfo);
 164 }
 165
 166 static void mainstone_init(MachineState *machine)
 167 {
 168     mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
 169 }
 170
 171 static void mainstone2_machine_init(MachineClass *mc)
 172 {
 173     mc->desc = "Mainstone II (PXA27x)";
 174     mc->init = mainstone_init;
 175     mc->ignore_memory_transaction_failures = true;
 176     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
 177 }
 178
 179 DEFINE_MACHINE("mainstone", mainstone2_machine_init)