2 * SABRELITE Board System emulation.
4 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
6 * This code is licensed under the GPL, version 2 or later.
7 * See the file `COPYING' in the top level directory.
9 * It (partially) emulates a sabrelite board, with a Freescale
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "hw/arm/fsl-imx6.h"
16 #include "hw/boards.h"
17 #include "hw/qdev-properties.h"
18 #include "qemu/error-report.h"
19 #include "sysemu/qtest.h"
21 static struct arm_boot_info sabrelite_binfo
= {
22 /* DDR memory start */
23 .loader_start
= FSL_IMX6_MMDC_ADDR
,
24 /* No board ID, we boot from DT tree */
28 /* No need to do any particular setup for secondary boot */
29 static void sabrelite_write_secondary(ARMCPU
*cpu
,
30 const struct arm_boot_info
*info
)
34 /* Secondary cores are reset through SRC device */
35 static void sabrelite_reset_secondary(ARMCPU
*cpu
,
36 const struct arm_boot_info
*info
)
40 static void sabrelite_init(MachineState
*machine
)
44 /* Check the amount of memory is compatible with the SOC */
45 if (machine
->ram_size
> FSL_IMX6_MMDC_SIZE
) {
46 error_report("RAM size " RAM_ADDR_FMT
" above max supported (%08x)",
47 machine
->ram_size
, FSL_IMX6_MMDC_SIZE
);
51 s
= FSL_IMX6(object_new(TYPE_FSL_IMX6
));
52 object_property_add_child(OBJECT(machine
), "soc", OBJECT(s
));
54 /* Ethernet PHY address is 6 */
55 object_property_set_int(OBJECT(s
), "fec-phy-num", 6, &error_fatal
);
57 qdev_realize(DEVICE(s
), NULL
, &error_fatal
);
59 memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR
,
64 * TODO: Ideally we would expose the chip select and spi bus on the
65 * SoC object using alias properties; then we would not need to
66 * directly access the underlying spi device object.
68 /* Add the sst25vf016b NOR FLASH memory to first SPI */
71 spi_dev
= object_resolve_path_component(OBJECT(s
), "spi1");
75 spi_bus
= (SSIBus
*)qdev_get_child_bus(DEVICE(spi_dev
), "spi");
77 DeviceState
*flash_dev
;
79 DriveInfo
*dinfo
= drive_get_next(IF_MTD
);
81 flash_dev
= qdev_new("sst25vf016b");
83 qdev_prop_set_drive_err(flash_dev
, "drive",
84 blk_by_legacy_dinfo(dinfo
),
87 qdev_realize_and_unref(flash_dev
, BUS(spi_bus
), &error_fatal
);
89 cs_line
= qdev_get_gpio_in_named(flash_dev
, SSI_GPIO_CS
, 0);
90 sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev
), 1, cs_line
);
95 sabrelite_binfo
.ram_size
= machine
->ram_size
;
96 sabrelite_binfo
.nb_cpus
= machine
->smp
.cpus
;
97 sabrelite_binfo
.secure_boot
= true;
98 sabrelite_binfo
.write_secondary_boot
= sabrelite_write_secondary
;
99 sabrelite_binfo
.secondary_cpu_reset_hook
= sabrelite_reset_secondary
;
101 if (!qtest_enabled()) {
102 arm_load_kernel(&s
->cpu
[0], machine
, &sabrelite_binfo
);
106 static void sabrelite_machine_init(MachineClass
*mc
)
108 mc
->desc
= "Freescale i.MX6 Quad SABRE Lite Board (Cortex-A9)";
109 mc
->init
= sabrelite_init
;
110 mc
->max_cpus
= FSL_IMX6_NUM_CPUS
;
111 mc
->ignore_memory_transaction_failures
= true;
112 mc
->default_ram_id
= "sabrelite.ram";
115 DEFINE_MACHINE("sabrelite", sabrelite_machine_init
)