hw/riscv/sifive_e.c

   1 /*
   2  * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * Provides a board compatible with the SiFive Freedom E SDK:
   7  *
   8  * 0) UART
   9  * 1) CLINT (Core Level Interruptor)
  10  * 2) PLIC (Platform Level Interrupt Controller)
  11  * 3) PRCI (Power, Reset, Clock, Interrupt)
  12  * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
  13  * 5) Flash memory emulated as RAM
  14  *
  15  * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
  16  * The OTP ROM and Flash boot code will be emulated in a future version.
  17  *
  18  * This program is free software; you can redistribute it and/or modify it
  19  * under the terms and conditions of the GNU General Public License,
  20  * version 2 or later, as published by the Free Software Foundation.
  21  *
  22  * This program is distributed in the hope it will be useful, but WITHOUT
  23  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  24  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  25  * more details.
  26  *
  27  * You should have received a copy of the GNU General Public License along with
  28  * this program.  If not, see <http://www.gnu.org/licenses/>.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qemu/error-report.h"
  33 #include "qapi/error.h"
  34 #include "hw/boards.h"
  35 #include "hw/loader.h"
  36 #include "hw/sysbus.h"
  37 #include "hw/char/serial.h"
  38 #include "hw/misc/unimp.h"
  39 #include "target/riscv/cpu.h"
  40 #include "hw/riscv/riscv_hart.h"
  41 #include "hw/riscv/sifive_e.h"
  42 #include "hw/riscv/boot.h"
  43 #include "hw/char/sifive_uart.h"
  44 #include "hw/intc/sifive_clint.h"
  45 #include "hw/intc/sifive_plic.h"
  46 #include "hw/misc/sifive_e_prci.h"
  47 #include "chardev/char.h"
  48 #include "sysemu/arch_init.h"
  49 #include "sysemu/sysemu.h"
  50
  51 static const MemMapEntry sifive_e_memmap[] = {
  52     [SIFIVE_E_DEV_DEBUG] =    {        0x0,     0x1000 },
  53     [SIFIVE_E_DEV_MROM] =     {     0x1000,     0x2000 },
  54     [SIFIVE_E_DEV_OTP] =      {    0x20000,     0x2000 },
  55     [SIFIVE_E_DEV_CLINT] =    {  0x2000000,    0x10000 },
  56     [SIFIVE_E_DEV_PLIC] =     {  0xc000000,  0x4000000 },
  57     [SIFIVE_E_DEV_AON] =      { 0x10000000,     0x8000 },
  58     [SIFIVE_E_DEV_PRCI] =     { 0x10008000,     0x8000 },
  59     [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000,     0x1000 },
  60     [SIFIVE_E_DEV_GPIO0] =    { 0x10012000,     0x1000 },
  61     [SIFIVE_E_DEV_UART0] =    { 0x10013000,     0x1000 },
  62     [SIFIVE_E_DEV_QSPI0] =    { 0x10014000,     0x1000 },
  63     [SIFIVE_E_DEV_PWM0] =     { 0x10015000,     0x1000 },
  64     [SIFIVE_E_DEV_UART1] =    { 0x10023000,     0x1000 },
  65     [SIFIVE_E_DEV_QSPI1] =    { 0x10024000,     0x1000 },
  66     [SIFIVE_E_DEV_PWM1] =     { 0x10025000,     0x1000 },
  67     [SIFIVE_E_DEV_QSPI2] =    { 0x10034000,     0x1000 },
  68     [SIFIVE_E_DEV_PWM2] =     { 0x10035000,     0x1000 },
  69     [SIFIVE_E_DEV_XIP] =      { 0x20000000, 0x20000000 },
  70     [SIFIVE_E_DEV_DTIM] =     { 0x80000000,     0x4000 }
  71 };
  72
  73 static void sifive_e_machine_init(MachineState *machine)
  74 {
  75     const MemMapEntry *memmap = sifive_e_memmap;
  76
  77     SiFiveEState *s = RISCV_E_MACHINE(machine);
  78     MemoryRegion *sys_mem = get_system_memory();
  79     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
  80     int i;
  81
  82     /* Initialize SoC */
  83     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
  84     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
  85
  86     /* Data Tightly Integrated Memory */
  87     memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
  88         memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
  89     memory_region_add_subregion(sys_mem,
  90         memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
  91
  92     /* Mask ROM reset vector */
  93     uint32_t reset_vec[4];
  94
  95     if (s->revb) {
  96         reset_vec[1] = 0x200102b7;  /* 0x1004: lui     t0,0x20010 */
  97     } else {
  98         reset_vec[1] = 0x204002b7;  /* 0x1004: lui     t0,0x20400 */
  99     }
 100     reset_vec[2] = 0x00028067;      /* 0x1008: jr      t0 */
 101
 102     reset_vec[0] = reset_vec[3] = 0;
 103
 104     /* copy in the reset vector in little_endian byte order */
 105     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 106         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 107     }
 108     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 109                           memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
 110
 111     if (machine->kernel_filename) {
 112         riscv_load_kernel(machine->kernel_filename,
 113                           memmap[SIFIVE_E_DEV_DTIM].base, NULL);
 114     }
 115 }
 116
 117 static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
 118 {
 119     SiFiveEState *s = RISCV_E_MACHINE(obj);
 120
 121     return s->revb;
 122 }
 123
 124 static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
 125 {
 126     SiFiveEState *s = RISCV_E_MACHINE(obj);
 127
 128     s->revb = value;
 129 }
 130
 131 static void sifive_e_machine_instance_init(Object *obj)
 132 {
 133     SiFiveEState *s = RISCV_E_MACHINE(obj);
 134
 135     s->revb = false;
 136 }
 137
 138 static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
 139 {
 140     MachineClass *mc = MACHINE_CLASS(oc);
 141
 142     mc->desc = "RISC-V Board compatible with SiFive E SDK";
 143     mc->init = sifive_e_machine_init;
 144     mc->max_cpus = 1;
 145     mc->default_cpu_type = SIFIVE_E_CPU;
 146
 147     object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
 148                                    sifive_e_machine_set_revb);
 149     object_class_property_set_description(oc, "revb",
 150                                           "Set on to tell QEMU that it should model "
 151                                           "the revB HiFive1 board");
 152 }
 153
 154 static const TypeInfo sifive_e_machine_typeinfo = {
 155     .name       = MACHINE_TYPE_NAME("sifive_e"),
 156     .parent     = TYPE_MACHINE,
 157     .class_init = sifive_e_machine_class_init,
 158     .instance_init = sifive_e_machine_instance_init,
 159     .instance_size = sizeof(SiFiveEState),
 160 };
 161
 162 static void sifive_e_machine_init_register_types(void)
 163 {
 164     type_register_static(&sifive_e_machine_typeinfo);
 165 }
 166
 167 type_init(sifive_e_machine_init_register_types)
 168
 169 static void sifive_e_soc_init(Object *obj)
 170 {
 171     MachineState *ms = MACHINE(qdev_get_machine());
 172     SiFiveESoCState *s = RISCV_E_SOC(obj);
 173
 174     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
 175     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
 176                             &error_abort);
 177     object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
 178     object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
 179                             TYPE_SIFIVE_GPIO);
 180 }
 181
 182 static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
 183 {
 184     MachineState *ms = MACHINE(qdev_get_machine());
 185     const MemMapEntry *memmap = sifive_e_memmap;
 186     SiFiveESoCState *s = RISCV_E_SOC(dev);
 187     MemoryRegion *sys_mem = get_system_memory();
 188
 189     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
 190                             &error_abort);
 191     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
 192
 193     /* Mask ROM */
 194     memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
 195                            memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
 196     memory_region_add_subregion(sys_mem,
 197         memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
 198
 199     /* MMIO */
 200     s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
 201         (char *)SIFIVE_E_PLIC_HART_CONFIG, 0,
 202         SIFIVE_E_PLIC_NUM_SOURCES,
 203         SIFIVE_E_PLIC_NUM_PRIORITIES,
 204         SIFIVE_E_PLIC_PRIORITY_BASE,
 205         SIFIVE_E_PLIC_PENDING_BASE,
 206         SIFIVE_E_PLIC_ENABLE_BASE,
 207         SIFIVE_E_PLIC_ENABLE_STRIDE,
 208         SIFIVE_E_PLIC_CONTEXT_BASE,
 209         SIFIVE_E_PLIC_CONTEXT_STRIDE,
 210         memmap[SIFIVE_E_DEV_PLIC].size);
 211     sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base,
 212         memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus,
 213         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 214         SIFIVE_CLINT_TIMEBASE_FREQ, false);
 215     create_unimplemented_device("riscv.sifive.e.aon",
 216         memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
 217     sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
 218
 219     /* GPIO */
 220
 221     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
 222         return;
 223     }
 224
 225     /* Map GPIO registers */
 226     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
 227
 228     /* Pass all GPIOs to the SOC layer so they are available to the board */
 229     qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
 230
 231     /* Connect GPIO interrupts to the PLIC */
 232     for (int i = 0; i < 32; i++) {
 233         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
 234                            qdev_get_gpio_in(DEVICE(s->plic),
 235                                             SIFIVE_E_GPIO0_IRQ0 + i));
 236     }
 237
 238     sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
 239         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
 240     create_unimplemented_device("riscv.sifive.e.qspi0",
 241         memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
 242     create_unimplemented_device("riscv.sifive.e.pwm0",
 243         memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
 244     sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
 245         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
 246     create_unimplemented_device("riscv.sifive.e.qspi1",
 247         memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
 248     create_unimplemented_device("riscv.sifive.e.pwm1",
 249         memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
 250     create_unimplemented_device("riscv.sifive.e.qspi2",
 251         memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
 252     create_unimplemented_device("riscv.sifive.e.pwm2",
 253         memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
 254
 255     /* Flash memory */
 256     memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
 257                            memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
 258     memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
 259         &s->xip_mem);
 260 }
 261
 262 static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
 263 {
 264     DeviceClass *dc = DEVICE_CLASS(oc);
 265
 266     dc->realize = sifive_e_soc_realize;
 267     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 268     dc->user_creatable = false;
 269 }
 270
 271 static const TypeInfo sifive_e_soc_type_info = {
 272     .name = TYPE_RISCV_E_SOC,
 273     .parent = TYPE_DEVICE,
 274     .instance_size = sizeof(SiFiveESoCState),
 275     .instance_init = sifive_e_soc_init,
 276     .class_init = sifive_e_soc_class_init,
 277 };
 278
 279 static void sifive_e_soc_register_types(void)
 280 {
 281     type_register_static(&sifive_e_soc_type_info);
 282 }
 283
 284 type_init(sifive_e_soc_register_types)