target/hppa/op_helper.c

   1 /*
   2  * Helpers for HPPA instructions.
   3  *
   4  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/helper-proto.h"
  24 #include "exec/cpu_ldst.h"
  25 #include "qemu/timer.h"
  26 #include "sysemu/runstate.h"
  27 #include "fpu/softfloat.h"
  28 #include "trace.h"
  29
  30 void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp)
  31 {
  32     CPUState *cs = env_cpu(env);
  33
  34     cs->exception_index = excp;
  35     cpu_loop_exit(cs);
  36 }
  37
  38 void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra)
  39 {
  40     CPUState *cs = env_cpu(env);
  41
  42     cs->exception_index = excp;
  43     cpu_loop_exit_restore(cs, ra);
  44 }
  45
  46 void HELPER(tsv)(CPUHPPAState *env, target_ureg cond)
  47 {
  48     if (unlikely((target_sreg)cond < 0)) {
  49         hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC());
  50     }
  51 }
  52
  53 void HELPER(tcond)(CPUHPPAState *env, target_ureg cond)
  54 {
  55     if (unlikely(cond)) {
  56         hppa_dynamic_excp(env, EXCP_COND, GETPC());
  57     }
  58 }
  59
  60 static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t val,
  61                            uint32_t mask, uintptr_t ra)
  62 {
  63 #ifdef CONFIG_USER_ONLY
  64     uint32_t old, new, cmp;
  65
  66     uint32_t *haddr = g2h(env_cpu(env), addr - 1);
  67     old = *haddr;
  68     while (1) {
  69         new = (old & ~mask) | (val & mask);
  70         cmp = qatomic_cmpxchg(haddr, old, new);
  71         if (cmp == old) {
  72             return;
  73         }
  74         old = cmp;
  75     }
  76 #else
  77     /* FIXME -- we can do better.  */
  78     cpu_loop_exit_atomic(env_cpu(env), ra);
  79 #endif
  80 }
  81
  82 static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val,
  83                       bool parallel, uintptr_t ra)
  84 {
  85     switch (addr & 3) {
  86     case 3:
  87         cpu_stb_data_ra(env, addr, val, ra);
  88         break;
  89     case 2:
  90         cpu_stw_data_ra(env, addr, val, ra);
  91         break;
  92     case 1:
  93         /* The 3 byte store must appear atomic.  */
  94         if (parallel) {
  95             atomic_store_3(env, addr, val, 0x00ffffffu, ra);
  96         } else {
  97             cpu_stb_data_ra(env, addr, val >> 16, ra);
  98             cpu_stw_data_ra(env, addr + 1, val, ra);
  99         }
 100         break;
 101     default:
 102         cpu_stl_data_ra(env, addr, val, ra);
 103         break;
 104     }
 105 }
 106
 107 void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val)
 108 {
 109     do_stby_b(env, addr, val, false, GETPC());
 110 }
 111
 112 void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr,
 113                              target_ureg val)
 114 {
 115     do_stby_b(env, addr, val, true, GETPC());
 116 }
 117
 118 static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg val,
 119                       bool parallel, uintptr_t ra)
 120 {
 121     switch (addr & 3) {
 122     case 3:
 123         /* The 3 byte store must appear atomic.  */
 124         if (parallel) {
 125             atomic_store_3(env, addr - 3, val, 0xffffff00u, ra);
 126         } else {
 127             cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
 128             cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
 129         }
 130         break;
 131     case 2:
 132         cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
 133         break;
 134     case 1:
 135         cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
 136         break;
 137     default:
 138         /* Nothing is stored, but protection is checked and the
 139            cacheline is marked dirty.  */
 140         probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra);
 141         break;
 142     }
 143 }
 144
 145 void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val)
 146 {
 147     do_stby_e(env, addr, val, false, GETPC());
 148 }
 149
 150 void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr,
 151                              target_ureg val)
 152 {
 153     do_stby_e(env, addr, val, true, GETPC());
 154 }
 155
 156 void HELPER(ldc_check)(target_ulong addr)
 157 {
 158     if (unlikely(addr & 0xf)) {
 159         qemu_log_mask(LOG_GUEST_ERROR,
 160                       "Undefined ldc to unaligned address mod 16: "
 161                       TARGET_FMT_lx "\n", addr);
 162     }
 163 }
 164
 165 target_ureg HELPER(probe)(CPUHPPAState *env, target_ulong addr,
 166                           uint32_t level, uint32_t want)
 167 {
 168 #ifdef CONFIG_USER_ONLY
 169     return page_check_range(addr, 1, want);
 170 #else
 171     int prot, excp;
 172     hwaddr phys;
 173
 174     trace_hppa_tlb_probe(addr, level, want);
 175     /* Fail if the requested privilege level is higher than current.  */
 176     if (level < (env->iaoq_f & 3)) {
 177         return 0;
 178     }
 179
 180     excp = hppa_get_physical_address(env, addr, level, 0, &phys, &prot);
 181     if (excp >= 0) {
 182         if (env->psw & PSW_Q) {
 183             /* ??? Needs tweaking for hppa64.  */
 184             env->cr[CR_IOR] = addr;
 185             env->cr[CR_ISR] = addr >> 32;
 186         }
 187         if (excp == EXCP_DTLB_MISS) {
 188             excp = EXCP_NA_DTLB_MISS;
 189         }
 190         hppa_dynamic_excp(env, excp, GETPC());
 191     }
 192     return (want & prot) != 0;
 193 #endif
 194 }
 195
 196 void HELPER(loaded_fr0)(CPUHPPAState *env)
 197 {
 198     uint32_t shadow = env->fr[0] >> 32;
 199     int rm, d;
 200
 201     env->fr0_shadow = shadow;
 202
 203     switch (extract32(shadow, 9, 2)) {
 204     default:
 205         rm = float_round_nearest_even;
 206         break;
 207     case 1:
 208         rm = float_round_to_zero;
 209         break;
 210     case 2:
 211         rm = float_round_up;
 212         break;
 213     case 3:
 214         rm = float_round_down;
 215         break;
 216     }
 217     set_float_rounding_mode(rm, &env->fp_status);
 218
 219     d = extract32(shadow, 5, 1);
 220     set_flush_to_zero(d, &env->fp_status);
 221     set_flush_inputs_to_zero(d, &env->fp_status);
 222 }
 223
 224 void cpu_hppa_loaded_fr0(CPUHPPAState *env)
 225 {
 226     helper_loaded_fr0(env);
 227 }
 228
 229 #define CONVERT_BIT(X, SRC, DST)        \
 230     ((SRC) > (DST)                      \
 231      ? (X) / ((SRC) / (DST)) & (DST)    \
 232      : ((X) & (SRC)) * ((DST) / (SRC)))
 233
 234 static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
 235 {
 236     uint32_t soft_exp = get_float_exception_flags(&env->fp_status);
 237     uint32_t hard_exp = 0;
 238     uint32_t shadow = env->fr0_shadow;
 239
 240     if (likely(soft_exp == 0)) {
 241         env->fr[0] = (uint64_t)shadow << 32;
 242         return;
 243     }
 244     set_float_exception_flags(0, &env->fp_status);
 245
 246     hard_exp |= CONVERT_BIT(soft_exp, float_flag_inexact,   1u << 0);
 247     hard_exp |= CONVERT_BIT(soft_exp, float_flag_underflow, 1u << 1);
 248     hard_exp |= CONVERT_BIT(soft_exp, float_flag_overflow,  1u << 2);
 249     hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, 1u << 3);
 250     hard_exp |= CONVERT_BIT(soft_exp, float_flag_invalid,   1u << 4);
 251     shadow |= hard_exp << (32 - 5);
 252     env->fr0_shadow = shadow;
 253     env->fr[0] = (uint64_t)shadow << 32;
 254
 255     if (hard_exp & shadow) {
 256         hppa_dynamic_excp(env, EXCP_ASSIST, ra);
 257     }
 258 }
 259
 260 float32 HELPER(fsqrt_s)(CPUHPPAState *env, float32 arg)
 261 {
 262     float32 ret = float32_sqrt(arg, &env->fp_status);
 263     update_fr0_op(env, GETPC());
 264     return ret;
 265 }
 266
 267 float32 HELPER(frnd_s)(CPUHPPAState *env, float32 arg)
 268 {
 269     float32 ret = float32_round_to_int(arg, &env->fp_status);
 270     update_fr0_op(env, GETPC());
 271     return ret;
 272 }
 273
 274 float32 HELPER(fadd_s)(CPUHPPAState *env, float32 a, float32 b)
 275 {
 276     float32 ret = float32_add(a, b, &env->fp_status);
 277     update_fr0_op(env, GETPC());
 278     return ret;
 279 }
 280
 281 float32 HELPER(fsub_s)(CPUHPPAState *env, float32 a, float32 b)
 282 {
 283     float32 ret = float32_sub(a, b, &env->fp_status);
 284     update_fr0_op(env, GETPC());
 285     return ret;
 286 }
 287
 288 float32 HELPER(fmpy_s)(CPUHPPAState *env, float32 a, float32 b)
 289 {
 290     float32 ret = float32_mul(a, b, &env->fp_status);
 291     update_fr0_op(env, GETPC());
 292     return ret;
 293 }
 294
 295 float32 HELPER(fdiv_s)(CPUHPPAState *env, float32 a, float32 b)
 296 {
 297     float32 ret = float32_div(a, b, &env->fp_status);
 298     update_fr0_op(env, GETPC());
 299     return ret;
 300 }
 301
 302 float64 HELPER(fsqrt_d)(CPUHPPAState *env, float64 arg)
 303 {
 304     float64 ret = float64_sqrt(arg, &env->fp_status);
 305     update_fr0_op(env, GETPC());
 306     return ret;
 307 }
 308
 309 float64 HELPER(frnd_d)(CPUHPPAState *env, float64 arg)
 310 {
 311     float64 ret = float64_round_to_int(arg, &env->fp_status);
 312     update_fr0_op(env, GETPC());
 313     return ret;
 314 }
 315
 316 float64 HELPER(fadd_d)(CPUHPPAState *env, float64 a, float64 b)
 317 {
 318     float64 ret = float64_add(a, b, &env->fp_status);
 319     update_fr0_op(env, GETPC());
 320     return ret;
 321 }
 322
 323 float64 HELPER(fsub_d)(CPUHPPAState *env, float64 a, float64 b)
 324 {
 325     float64 ret = float64_sub(a, b, &env->fp_status);
 326     update_fr0_op(env, GETPC());
 327     return ret;
 328 }
 329
 330 float64 HELPER(fmpy_d)(CPUHPPAState *env, float64 a, float64 b)
 331 {
 332     float64 ret = float64_mul(a, b, &env->fp_status);
 333     update_fr0_op(env, GETPC());
 334     return ret;
 335 }
 336
 337 float64 HELPER(fdiv_d)(CPUHPPAState *env, float64 a, float64 b)
 338 {
 339     float64 ret = float64_div(a, b, &env->fp_status);
 340     update_fr0_op(env, GETPC());
 341     return ret;
 342 }
 343
 344 float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg)
 345 {
 346     float64 ret = float32_to_float64(arg, &env->fp_status);
 347     update_fr0_op(env, GETPC());
 348     return ret;
 349 }
 350
 351 float32 HELPER(fcnv_d_s)(CPUHPPAState *env, float64 arg)
 352 {
 353     float32 ret = float64_to_float32(arg, &env->fp_status);
 354     update_fr0_op(env, GETPC());
 355     return ret;
 356 }
 357
 358 float32 HELPER(fcnv_w_s)(CPUHPPAState *env, int32_t arg)
 359 {
 360     float32 ret = int32_to_float32(arg, &env->fp_status);
 361     update_fr0_op(env, GETPC());
 362     return ret;
 363 }
 364
 365 float32 HELPER(fcnv_dw_s)(CPUHPPAState *env, int64_t arg)
 366 {
 367     float32 ret = int64_to_float32(arg, &env->fp_status);
 368     update_fr0_op(env, GETPC());
 369     return ret;
 370 }
 371
 372 float64 HELPER(fcnv_w_d)(CPUHPPAState *env, int32_t arg)
 373 {
 374     float64 ret = int32_to_float64(arg, &env->fp_status);
 375     update_fr0_op(env, GETPC());
 376     return ret;
 377 }
 378
 379 float64 HELPER(fcnv_dw_d)(CPUHPPAState *env, int64_t arg)
 380 {
 381     float64 ret = int64_to_float64(arg, &env->fp_status);
 382     update_fr0_op(env, GETPC());
 383     return ret;
 384 }
 385
 386 int32_t HELPER(fcnv_s_w)(CPUHPPAState *env, float32 arg)
 387 {
 388     int32_t ret = float32_to_int32(arg, &env->fp_status);
 389     update_fr0_op(env, GETPC());
 390     return ret;
 391 }
 392
 393 int32_t HELPER(fcnv_d_w)(CPUHPPAState *env, float64 arg)
 394 {
 395     int32_t ret = float64_to_int32(arg, &env->fp_status);
 396     update_fr0_op(env, GETPC());
 397     return ret;
 398 }
 399
 400 int64_t HELPER(fcnv_s_dw)(CPUHPPAState *env, float32 arg)
 401 {
 402     int64_t ret = float32_to_int64(arg, &env->fp_status);
 403     update_fr0_op(env, GETPC());
 404     return ret;
 405 }
 406
 407 int64_t HELPER(fcnv_d_dw)(CPUHPPAState *env, float64 arg)
 408 {
 409     int64_t ret = float64_to_int64(arg, &env->fp_status);
 410     update_fr0_op(env, GETPC());
 411     return ret;
 412 }
 413
 414 int32_t HELPER(fcnv_t_s_w)(CPUHPPAState *env, float32 arg)
 415 {
 416     int32_t ret = float32_to_int32_round_to_zero(arg, &env->fp_status);
 417     update_fr0_op(env, GETPC());
 418     return ret;
 419 }
 420
 421 int32_t HELPER(fcnv_t_d_w)(CPUHPPAState *env, float64 arg)
 422 {
 423     int32_t ret = float64_to_int32_round_to_zero(arg, &env->fp_status);
 424     update_fr0_op(env, GETPC());
 425     return ret;
 426 }
 427
 428 int64_t HELPER(fcnv_t_s_dw)(CPUHPPAState *env, float32 arg)
 429 {
 430     int64_t ret = float32_to_int64_round_to_zero(arg, &env->fp_status);
 431     update_fr0_op(env, GETPC());
 432     return ret;
 433 }
 434
 435 int64_t HELPER(fcnv_t_d_dw)(CPUHPPAState *env, float64 arg)
 436 {
 437     int64_t ret = float64_to_int64_round_to_zero(arg, &env->fp_status);
 438     update_fr0_op(env, GETPC());
 439     return ret;
 440 }
 441
 442 float32 HELPER(fcnv_uw_s)(CPUHPPAState *env, uint32_t arg)
 443 {
 444     float32 ret = uint32_to_float32(arg, &env->fp_status);
 445     update_fr0_op(env, GETPC());
 446     return ret;
 447 }
 448
 449 float32 HELPER(fcnv_udw_s)(CPUHPPAState *env, uint64_t arg)
 450 {
 451     float32 ret = uint64_to_float32(arg, &env->fp_status);
 452     update_fr0_op(env, GETPC());
 453     return ret;
 454 }
 455
 456 float64 HELPER(fcnv_uw_d)(CPUHPPAState *env, uint32_t arg)
 457 {
 458     float64 ret = uint32_to_float64(arg, &env->fp_status);
 459     update_fr0_op(env, GETPC());
 460     return ret;
 461 }
 462
 463 float64 HELPER(fcnv_udw_d)(CPUHPPAState *env, uint64_t arg)
 464 {
 465     float64 ret = uint64_to_float64(arg, &env->fp_status);
 466     update_fr0_op(env, GETPC());
 467     return ret;
 468 }
 469
 470 uint32_t HELPER(fcnv_s_uw)(CPUHPPAState *env, float32 arg)
 471 {
 472     uint32_t ret = float32_to_uint32(arg, &env->fp_status);
 473     update_fr0_op(env, GETPC());
 474     return ret;
 475 }
 476
 477 uint32_t HELPER(fcnv_d_uw)(CPUHPPAState *env, float64 arg)
 478 {
 479     uint32_t ret = float64_to_uint32(arg, &env->fp_status);
 480     update_fr0_op(env, GETPC());
 481     return ret;
 482 }
 483
 484 uint64_t HELPER(fcnv_s_udw)(CPUHPPAState *env, float32 arg)
 485 {
 486     uint64_t ret = float32_to_uint64(arg, &env->fp_status);
 487     update_fr0_op(env, GETPC());
 488     return ret;
 489 }
 490
 491 uint64_t HELPER(fcnv_d_udw)(CPUHPPAState *env, float64 arg)
 492 {
 493     uint64_t ret = float64_to_uint64(arg, &env->fp_status);
 494     update_fr0_op(env, GETPC());
 495     return ret;
 496 }
 497
 498 uint32_t HELPER(fcnv_t_s_uw)(CPUHPPAState *env, float32 arg)
 499 {
 500     uint32_t ret = float32_to_uint32_round_to_zero(arg, &env->fp_status);
 501     update_fr0_op(env, GETPC());
 502     return ret;
 503 }
 504
 505 uint32_t HELPER(fcnv_t_d_uw)(CPUHPPAState *env, float64 arg)
 506 {
 507     uint32_t ret = float64_to_uint32_round_to_zero(arg, &env->fp_status);
 508     update_fr0_op(env, GETPC());
 509     return ret;
 510 }
 511
 512 uint64_t HELPER(fcnv_t_s_udw)(CPUHPPAState *env, float32 arg)
 513 {
 514     uint64_t ret = float32_to_uint64_round_to_zero(arg, &env->fp_status);
 515     update_fr0_op(env, GETPC());
 516     return ret;
 517 }
 518
 519 uint64_t HELPER(fcnv_t_d_udw)(CPUHPPAState *env, float64 arg)
 520 {
 521     uint64_t ret = float64_to_uint64_round_to_zero(arg, &env->fp_status);
 522     update_fr0_op(env, GETPC());
 523     return ret;
 524 }
 525
 526 static void update_fr0_cmp(CPUHPPAState *env, uint32_t y,
 527                            uint32_t c, FloatRelation r)
 528 {
 529     uint32_t shadow = env->fr0_shadow;
 530
 531     switch (r) {
 532     case float_relation_greater:
 533         c = extract32(c, 4, 1);
 534         break;
 535     case float_relation_less:
 536         c = extract32(c, 3, 1);
 537         break;
 538     case float_relation_equal:
 539         c = extract32(c, 2, 1);
 540         break;
 541     case float_relation_unordered:
 542         c = extract32(c, 1, 1);
 543         break;
 544     default:
 545         g_assert_not_reached();
 546     }
 547
 548     if (y) {
 549         /* targeted comparison */
 550         /* set fpsr[ca[y - 1]] to current compare */
 551         shadow = deposit32(shadow, 21 - (y - 1), 1, c);
 552     } else {
 553         /* queued comparison */
 554         /* shift cq right by one place */
 555         shadow = deposit32(shadow, 11, 10, extract32(shadow, 12, 10));
 556         /* move fpsr[c] to fpsr[cq[0]] */
 557         shadow = deposit32(shadow, 21, 1, extract32(shadow, 26, 1));
 558         /* set fpsr[c] to current compare */
 559         shadow = deposit32(shadow, 26, 1, c);
 560     }
 561
 562     env->fr0_shadow = shadow;
 563     env->fr[0] = (uint64_t)shadow << 32;
 564 }
 565
 566 void HELPER(fcmp_s)(CPUHPPAState *env, float32 a, float32 b,
 567                     uint32_t y, uint32_t c)
 568 {
 569     FloatRelation r;
 570     if (c & 1) {
 571         r = float32_compare(a, b, &env->fp_status);
 572     } else {
 573         r = float32_compare_quiet(a, b, &env->fp_status);
 574     }
 575     update_fr0_op(env, GETPC());
 576     update_fr0_cmp(env, y, c, r);
 577 }
 578
 579 void HELPER(fcmp_d)(CPUHPPAState *env, float64 a, float64 b,
 580                     uint32_t y, uint32_t c)
 581 {
 582     FloatRelation r;
 583     if (c & 1) {
 584         r = float64_compare(a, b, &env->fp_status);
 585     } else {
 586         r = float64_compare_quiet(a, b, &env->fp_status);
 587     }
 588     update_fr0_op(env, GETPC());
 589     update_fr0_cmp(env, y, c, r);
 590 }
 591
 592 float32 HELPER(fmpyfadd_s)(CPUHPPAState *env, float32 a, float32 b, float32 c)
 593 {
 594     float32 ret = float32_muladd(a, b, c, 0, &env->fp_status);
 595     update_fr0_op(env, GETPC());
 596     return ret;
 597 }
 598
 599 float32 HELPER(fmpynfadd_s)(CPUHPPAState *env, float32 a, float32 b, float32 c)
 600 {
 601     float32 ret = float32_muladd(a, b, c, float_muladd_negate_product,
 602                                  &env->fp_status);
 603     update_fr0_op(env, GETPC());
 604     return ret;
 605 }
 606
 607 float64 HELPER(fmpyfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c)
 608 {
 609     float64 ret = float64_muladd(a, b, c, 0, &env->fp_status);
 610     update_fr0_op(env, GETPC());
 611     return ret;
 612 }
 613
 614 float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c)
 615 {
 616     float64 ret = float64_muladd(a, b, c, float_muladd_negate_product,
 617                                  &env->fp_status);
 618     update_fr0_op(env, GETPC());
 619     return ret;
 620 }
 621
 622 target_ureg HELPER(read_interval_timer)(void)
 623 {
 624 #ifdef CONFIG_USER_ONLY
 625     /* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist.
 626        Just pass through the host cpu clock ticks.  */
 627     return cpu_get_host_ticks();
 628 #else
 629     /* In system mode we have access to a decent high-resolution clock.
 630        In order to make OS-level time accounting work with the cr16,
 631        present it with a well-timed clock fixed at 250MHz.  */
 632     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2;
 633 #endif
 634 }
 635
 636 #ifndef CONFIG_USER_ONLY
 637 void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val)
 638 {
 639     HPPACPU *cpu = env_archcpu(env);
 640     uint64_t current = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 641     uint64_t timeout;
 642
 643     /* Even in 64-bit mode, the comparator is always 32-bit.  But the
 644        value we expose to the guest is 1/4 of the speed of the clock,
 645        so moosh in 34 bits.  */
 646     timeout = deposit64(current, 0, 34, (uint64_t)val << 2);
 647
 648     /* If the mooshing puts the clock in the past, advance to next round.  */
 649     if (timeout < current + 1000) {
 650         timeout += 1ULL << 34;
 651     }
 652
 653     cpu->env.cr[CR_IT] = timeout;
 654     timer_mod(cpu->alarm_timer, timeout);
 655 }
 656
 657 void HELPER(halt)(CPUHPPAState *env)
 658 {
 659     qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 660     helper_excp(env, EXCP_HLT);
 661 }
 662
 663 void HELPER(reset)(CPUHPPAState *env)
 664 {
 665     qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 666     helper_excp(env, EXCP_HLT);
 667 }
 668
 669 target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm)
 670 {
 671     target_ulong psw = env->psw;
 672     /*
 673      * Setting the PSW Q bit to 1, if it was not already 1, is an
 674      * undefined operation.
 675      *
 676      * However, HP-UX 10.20 does this with the SSM instruction.
 677      * Tested this on HP9000/712 and HP9000/785/C3750 and both
 678      * machines set the Q bit from 0 to 1 without an exception,
 679      * so let this go without comment.
 680      */
 681     env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM);
 682     return psw & PSW_SM;
 683 }
 684
 685 void HELPER(rfi)(CPUHPPAState *env)
 686 {
 687     env->iasq_f = (uint64_t)env->cr[CR_IIASQ] << 32;
 688     env->iasq_b = (uint64_t)env->cr_back[0] << 32;
 689     env->iaoq_f = env->cr[CR_IIAOQ];
 690     env->iaoq_b = env->cr_back[1];
 691     cpu_hppa_put_psw(env, env->cr[CR_IPSW]);
 692 }
 693
 694 void HELPER(rfi_r)(CPUHPPAState *env)
 695 {
 696     env->gr[1] = env->shadow[0];
 697     env->gr[8] = env->shadow[1];
 698     env->gr[9] = env->shadow[2];
 699     env->gr[16] = env->shadow[3];
 700     env->gr[17] = env->shadow[4];
 701     env->gr[24] = env->shadow[5];
 702     env->gr[25] = env->shadow[6];
 703     helper_rfi(env);
 704 }
 705 #endif