3 *******************************
4 TCG Intermediate Representation
5 *******************************
10 TCG (Tiny Code Generator) began as a generic backend for a C compiler.
11 It was simplified to be used in QEMU. It also has its roots in the
12 QOP code generator written by Paul Brook.
17 The TCG *target* is the architecture for which we generate the code.
18 It is of course not the same as the "target" of QEMU which is the
19 emulated architecture. As TCG started as a generic C backend used
20 for cross compiling, the assumption was that TCG target might be
21 different from the host, although this is never the case for QEMU.
23 In this document, we use *guest* to specify what architecture we are
24 emulating; *target* always means the TCG target, the machine on which
27 An operation with *undefined behavior* may result in a crash.
29 An operation with *unspecified behavior* shall not crash. However,
30 the result may be one of several possibilities so may be considered
31 an *undefined result*.
36 A TCG *basic block* is a single entry, multiple exit region which
37 corresponds to a list of instructions terminated by a label, or
38 any branch instruction.
40 A TCG *extended basic block* is a single entry, multiple exit region
41 which corresponds to a list of instructions terminated by a label or
42 an unconditional branch. Specifically, an extended basic block is
43 a sequence of basic blocks connected by the fall-through paths of
44 zero or more conditional branch instructions.
49 TCG instructions or *ops* operate on TCG *variables*, both of which
50 are strongly typed. Each instruction has a fixed number of output
51 variable operands, input variable operands and constant operands.
52 Vector instructions have a field specifying the element size within
53 the vector. The notable exception is the call instruction which has
54 a variable number of outputs and inputs.
56 In the textual form, output operands usually come first, followed by
57 input operands, followed by constant operands. The output type is
58 included in the instruction name. Constants are prefixed with a '$'.
62 add_i32 t0, t1, t2 /* (t0 <- t1 + t2) */
69 There is one TCG *fixed global* variable, ``cpu_env``, which is
70 live in all translation blocks, and holds a pointer to ``CPUArchState``.
71 This variable is held in a host cpu register at all times in all
76 A TCG *global* is a variable which is live in all translation blocks,
77 and corresponds to memory location that is within ``CPUArchState``.
78 These may be specified as an offset from ``cpu_env``, in which case
79 they are called *direct globals*, or may be specified as an offset
80 from a direct global, in which case they are called *indirect globals*.
81 Even indirect globals should still reference memory within
82 ``CPUArchState``. All TCG globals are defined during
83 ``TCGCPUOps.initialize``, before any translation blocks are generated.
87 A TCG *constant* is a variable which is live throughout the entire
88 translation block, and contains a constant value. These variables
89 are allocated on demand during translation and are hashed so that
90 there is exactly one variable holding a given value.
94 A TCG *translation block temporary* is a variable which is live
95 throughout the entire translation block, but dies on any exit.
96 These temporaries are allocated explicitly during translation.
100 A TCG *extended basic block temporary* is a variable which is live
101 throughout an extended basic block, but dies on any exit.
102 These temporaries are allocated explicitly during translation.
113 A 64-bit integer. For 32-bit hosts, such variables are split into a pair
114 of variables with ``type=TCG_TYPE_I32`` and ``base_type=TCG_TYPE_I64``.
115 The ``temp_subindex`` for each indicates where it falls within the
116 host-endian representation.
120 An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size
121 of a pointer for the host.
125 An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size
126 of the integer registers for the host. This may be larger
127 than ``TCG_TYPE_PTR`` depending on the host ABI.
131 A 128-bit integer. For all hosts, such variables are split into a number
132 of variables with ``type=TCG_TYPE_REG`` and ``base_type=TCG_TYPE_I128``.
133 The ``temp_subindex`` for each indicates where it falls within the
134 host-endian representation.
138 A 64-bit vector. This type is valid only if the TCG target
139 sets ``TCG_TARGET_HAS_v64``.
143 A 128-bit vector. This type is valid only if the TCG target
144 sets ``TCG_TARGET_HAS_v128``.
148 A 256-bit vector. This type is valid only if the TCG target
149 sets ``TCG_TARGET_HAS_v256``.
154 Helpers are registered in a guest-specific ``helper.h``,
155 which is processed to generate ``tcg_gen_helper_*`` functions.
156 With these functions it is possible to call a function taking
157 i32, i64, i128 or pointer types.
159 By default, before calling a helper, all globals are stored at their
160 canonical location. By default, the helper is allowed to modify the
161 CPU state (including the state represented by tcg globals)
162 or may raise an exception. This default can be overridden using the
163 following function modifiers:
165 * ``TCG_CALL_NO_WRITE_GLOBALS``
167 The helper does not modify any globals, but may read them.
168 Globals will be saved to their canonical location before calling helpers,
169 but need not be reloaded afterwards.
171 * ``TCG_CALL_NO_READ_GLOBALS``
173 The helper does not read globals, either directly or via an exception.
174 They will not be saved to their canonical locations before calling
175 the helper. This implies ``TCG_CALL_NO_WRITE_GLOBALS``.
177 * ``TCG_CALL_NO_SIDE_EFFECTS``
179 The call to the helper function may be removed if the return value is
180 not used. This means that it may not modify any CPU state nor may it
186 When generating instructions, you can count on at least the following
189 - Single instructions are simplified, e.g.
193 and_i32 t0, t0, $0xffffffff
197 - A liveness analysis is done at the basic block level. The
198 information is used to suppress moves from a dead variable to
199 another one. It is also used to remove instructions which compute
200 dead results. The later is especially useful for condition code
201 optimization in QEMU.
203 In the following example:
211 only the last instruction is kept.
214 Instruction Reference
215 =====================
222 * - call *<ret>* *<params>* ptr
224 - | call function 'ptr' (pointer type)
226 | *<ret>* optional 32 bit or 64 bit return value
227 | *<params>* optional 32 bit or 64 bit parameters
236 - | Define label 'label' at the current program point.
242 * - brcond_i32/i64 *t0*, *t1*, *cond*, *label*
244 - | Conditional jump if *t0* *cond* *t1* is true. *cond* can be:
248 | ``TCG_COND_LT /* signed */``
249 | ``TCG_COND_GE /* signed */``
250 | ``TCG_COND_LE /* signed */``
251 | ``TCG_COND_GT /* signed */``
252 | ``TCG_COND_LTU /* unsigned */``
253 | ``TCG_COND_GEU /* unsigned */``
254 | ``TCG_COND_LEU /* unsigned */``
255 | ``TCG_COND_GTU /* unsigned */``
262 * - add_i32/i64 *t0*, *t1*, *t2*
264 - | *t0* = *t1* + *t2*
266 * - sub_i32/i64 *t0*, *t1*, *t2*
268 - | *t0* = *t1* - *t2*
270 * - neg_i32/i64 *t0*, *t1*
272 - | *t0* = -*t1* (two's complement)
274 * - mul_i32/i64 *t0*, *t1*, *t2*
276 - | *t0* = *t1* * *t2*
278 * - div_i32/i64 *t0*, *t1*, *t2*
280 - | *t0* = *t1* / *t2* (signed)
281 | Undefined behavior if division by zero or overflow.
283 * - divu_i32/i64 *t0*, *t1*, *t2*
285 - | *t0* = *t1* / *t2* (unsigned)
286 | Undefined behavior if division by zero.
288 * - rem_i32/i64 *t0*, *t1*, *t2*
290 - | *t0* = *t1* % *t2* (signed)
291 | Undefined behavior if division by zero or overflow.
293 * - remu_i32/i64 *t0*, *t1*, *t2*
295 - | *t0* = *t1* % *t2* (unsigned)
296 | Undefined behavior if division by zero.
304 * - and_i32/i64 *t0*, *t1*, *t2*
306 - | *t0* = *t1* & *t2*
308 * - or_i32/i64 *t0*, *t1*, *t2*
310 - | *t0* = *t1* | *t2*
312 * - xor_i32/i64 *t0*, *t1*, *t2*
314 - | *t0* = *t1* ^ *t2*
316 * - not_i32/i64 *t0*, *t1*
320 * - andc_i32/i64 *t0*, *t1*, *t2*
322 - | *t0* = *t1* & ~\ *t2*
324 * - eqv_i32/i64 *t0*, *t1*, *t2*
326 - | *t0* = ~(*t1* ^ *t2*), or equivalently, *t0* = *t1* ^ ~\ *t2*
328 * - nand_i32/i64 *t0*, *t1*, *t2*
330 - | *t0* = ~(*t1* & *t2*)
332 * - nor_i32/i64 *t0*, *t1*, *t2*
334 - | *t0* = ~(*t1* | *t2*)
336 * - orc_i32/i64 *t0*, *t1*, *t2*
338 - | *t0* = *t1* | ~\ *t2*
340 * - clz_i32/i64 *t0*, *t1*, *t2*
342 - | *t0* = *t1* ? clz(*t1*) : *t2*
344 * - ctz_i32/i64 *t0*, *t1*, *t2*
346 - | *t0* = *t1* ? ctz(*t1*) : *t2*
348 * - ctpop_i32/i64 *t0*, *t1*
350 - | *t0* = number of bits set in *t1*
352 | With *ctpop* short for "count population", matching
353 | the function name used in ``include/qemu/host-utils.h``.
361 * - shl_i32/i64 *t0*, *t1*, *t2*
363 - | *t0* = *t1* << *t2*
364 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
366 * - shr_i32/i64 *t0*, *t1*, *t2*
368 - | *t0* = *t1* >> *t2* (unsigned)
369 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
371 * - sar_i32/i64 *t0*, *t1*, *t2*
373 - | *t0* = *t1* >> *t2* (signed)
374 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
376 * - rotl_i32/i64 *t0*, *t1*, *t2*
378 - | Rotation of *t2* bits to the left
379 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
381 * - rotr_i32/i64 *t0*, *t1*, *t2*
383 - | Rotation of *t2* bits to the right.
384 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
392 * - mov_i32/i64 *t0*, *t1*
395 | Move *t1* to *t0* (both operands must have the same type).
397 * - ext8s_i32/i64 *t0*, *t1*
399 ext8u_i32/i64 *t0*, *t1*
401 ext16s_i32/i64 *t0*, *t1*
403 ext16u_i32/i64 *t0*, *t1*
405 ext32s_i64 *t0*, *t1*
407 ext32u_i64 *t0*, *t1*
409 - | 8, 16 or 32 bit sign/zero extension (both operands must have the same type)
411 * - bswap16_i32/i64 *t0*, *t1*, *flags*
413 - | 16 bit byte swap on the low bits of a 32/64 bit input.
415 | If *flags* & ``TCG_BSWAP_IZ``, then *t1* is known to be zero-extended from bit 15.
416 | If *flags* & ``TCG_BSWAP_OZ``, then *t0* will be zero-extended from bit 15.
417 | If *flags* & ``TCG_BSWAP_OS``, then *t0* will be sign-extended from bit 15.
419 | If neither ``TCG_BSWAP_OZ`` nor ``TCG_BSWAP_OS`` are set, then the bits of *t0* above bit 15 may contain any value.
421 * - bswap32_i64 *t0*, *t1*, *flags*
423 - | 32 bit byte swap on a 64-bit value. The flags are the same as for bswap16,
424 except they apply from bit 31 instead of bit 15.
426 * - bswap32_i32 *t0*, *t1*, *flags*
428 bswap64_i64 *t0*, *t1*, *flags*
430 - | 32/64 bit byte swap. The flags are ignored, but still present
431 for consistency with the other bswap opcodes.
433 * - discard_i32/i64 *t0*
435 - | Indicate that the value of *t0* won't be used later. It is useful to
436 force dead code elimination.
438 * - deposit_i32/i64 *dest*, *t1*, *t2*, *pos*, *len*
440 - | Deposit *t2* as a bitfield into *t1*, placing the result in *dest*.
442 | The bitfield is described by *pos*/*len*, which are immediate values:
444 | *len* - the length of the bitfield
445 | *pos* - the position of the first bit, counting from the LSB
447 | For example, "deposit_i32 dest, t1, t2, 8, 4" indicates a 4-bit field
448 at bit 8. This operation would be equivalent to
450 | *dest* = (*t1* & ~0x0f00) | ((*t2* << 8) & 0x0f00)
452 * - extract_i32/i64 *dest*, *t1*, *pos*, *len*
454 sextract_i32/i64 *dest*, *t1*, *pos*, *len*
456 - | Extract a bitfield from *t1*, placing the result in *dest*.
458 | The bitfield is described by *pos*/*len*, which are immediate values,
459 as above for deposit. For extract_*, the result will be extended
460 to the left with zeros; for sextract_*, the result will be extended
461 to the left with copies of the bitfield sign bit at *pos* + *len* - 1.
463 | For example, "sextract_i32 dest, t1, 8, 4" indicates a 4-bit field
464 at bit 8. This operation would be equivalent to
466 | *dest* = (*t1* << 20) >> 28
468 | (using an arithmetic right shift).
470 * - extract2_i32/i64 *dest*, *t1*, *t2*, *pos*
472 - | For N = {32,64}, extract an N-bit quantity from the concatenation
473 of *t2*:*t1*, beginning at *pos*. The tcg_gen_extract2_{i32,i64} expander
474 accepts 0 <= *pos* <= N as inputs. The backend code generator will
475 not see either 0 or N as inputs for these opcodes.
477 * - extrl_i64_i32 *t0*, *t1*
479 - | For 64-bit hosts only, extract the low 32-bits of input *t1* and place it
480 into 32-bit output *t0*. Depending on the host, this may be a simple move,
481 or may require additional canonicalization.
483 * - extrh_i64_i32 *t0*, *t1*
485 - | For 64-bit hosts only, extract the high 32-bits of input *t1* and place it
486 into 32-bit output *t0*. Depending on the host, this may be a simple shift,
487 or may require additional canonicalization.
495 * - setcond_i32/i64 *dest*, *t1*, *t2*, *cond*
497 - | *dest* = (*t1* *cond* *t2*)
499 | Set *dest* to 1 if (*t1* *cond* *t2*) is true, otherwise set to 0.
501 * - movcond_i32/i64 *dest*, *c1*, *c2*, *v1*, *v2*, *cond*
503 - | *dest* = (*c1* *cond* *c2* ? *v1* : *v2*)
505 | Set *dest* to *v1* if (*c1* *cond* *c2*) is true, otherwise set to *v2*.
513 * - ext_i32_i64 *t0*, *t1*
515 - | Convert *t1* (32 bit) to *t0* (64 bit) and does sign extension
517 * - extu_i32_i64 *t0*, *t1*
519 - | Convert *t1* (32 bit) to *t0* (64 bit) and does zero extension
521 * - trunc_i64_i32 *t0*, *t1*
523 - | Truncate *t1* (64 bit) to *t0* (32 bit)
525 * - concat_i32_i64 *t0*, *t1*, *t2*
527 - | Construct *t0* (64-bit) taking the low half from *t1* (32 bit) and the high half
530 * - concat32_i64 *t0*, *t1*, *t2*
532 - | Construct *t0* (64-bit) taking the low half from *t1* (64 bit) and the high half
541 * - ld_i32/i64 *t0*, *t1*, *offset*
543 ld8s_i32/i64 *t0*, *t1*, *offset*
545 ld8u_i32/i64 *t0*, *t1*, *offset*
547 ld16s_i32/i64 *t0*, *t1*, *offset*
549 ld16u_i32/i64 *t0*, *t1*, *offset*
551 ld32s_i64 t0, *t1*, *offset*
553 ld32u_i64 t0, *t1*, *offset*
555 - | *t0* = read(*t1* + *offset*)
557 | Load 8, 16, 32 or 64 bits with or without sign extension from host memory.
558 *offset* must be a constant.
560 * - st_i32/i64 *t0*, *t1*, *offset*
562 st8_i32/i64 *t0*, *t1*, *offset*
564 st16_i32/i64 *t0*, *t1*, *offset*
566 st32_i64 *t0*, *t1*, *offset*
568 - | write(*t0*, *t1* + *offset*)
570 | Write 8, 16, 32 or 64 bits to host memory.
572 All this opcodes assume that the pointed host memory doesn't correspond
573 to a global. In the latter case the behaviour is unpredictable.
576 Multiword arithmetic support
577 ----------------------------
581 * - add2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high*
583 sub2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high*
585 - | Similar to add/sub, except that the double-word inputs *t1* and *t2* are
586 formed from two single-word arguments, and the double-word output *t0*
587 is returned in two single-word outputs.
589 * - mulu2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2*
591 - | Similar to mul, except two unsigned inputs *t1* and *t2* yielding the full
592 double-word product *t0*. The latter is returned in two single-word outputs.
594 * - muls2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2*
596 - | Similar to mulu2, except the two inputs *t1* and *t2* are signed.
598 * - mulsh_i32/i64 *t0*, *t1*, *t2*
600 muluh_i32/i64 *t0*, *t1*, *t2*
602 - | Provide the high part of a signed or unsigned multiply, respectively.
604 | If mulu2/muls2 are not provided by the backend, the tcg-op generator
605 can obtain the same results by emitting a pair of opcodes, mul + muluh/mulsh.
608 Memory Barrier support
609 ----------------------
615 - | Generate a target memory barrier instruction to ensure memory ordering
616 as being enforced by a corresponding guest memory barrier instruction.
618 | The ordering enforced by the backend may be stricter than the ordering
619 required by the guest. It cannot be weaker. This opcode takes a constant
620 argument which is required to generate the appropriate barrier
621 instruction. The backend should take care to emit the target barrier
622 instruction only when necessary i.e., for SMP guests and when MTTCG is
625 | The guest translators should generate this opcode for all guest instructions
626 which have ordering side effects.
628 | Please see :ref:`atomics-ref` for more information on memory barriers.
631 64-bit guest on 32-bit host support
632 -----------------------------------
634 The following opcodes are internal to TCG. Thus they are to be implemented by
635 32-bit host code generators, but are not to be emitted by guest translators.
636 They are emitted as needed by inline functions within ``tcg-op.h``.
640 * - brcond2_i32 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *cond*, *label*
642 - | Similar to brcond, except that the 64-bit values *t0* and *t1*
643 are formed from two 32-bit arguments.
645 * - setcond2_i32 *dest*, *t1_low*, *t1_high*, *t2_low*, *t2_high*, *cond*
647 - | Similar to setcond, except that the 64-bit values *t1* and *t2* are
648 formed from two 32-bit arguments. The result is a 32-bit value.
651 QEMU specific operations
652 ------------------------
658 - | Exit the current TB and return the value *t0* (word type).
662 - | Exit the current TB and jump to the TB index *index* (constant) if the
663 current TB was linked to this TB. Otherwise execute the next
664 instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued
665 at most once with each slot index per TB.
667 * - lookup_and_goto_ptr *tb_addr*
669 - | Look up a TB address *tb_addr* and jump to it if valid. If not valid,
670 jump to the TCG epilogue to go back to the exec loop.
672 | This operation is optional. If the TCG backend does not implement the
673 goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0).
675 * - qemu_ld_i32/i64 *t0*, *t1*, *flags*, *memidx*
677 qemu_st_i32/i64 *t0*, *t1*, *flags*, *memidx*
679 qemu_st8_i32 *t0*, *t1*, *flags*, *memidx*
681 - | Load data at the guest address *t1* into *t0*, or store data in *t0* at guest
682 address *t1*. The _i32/_i64 size applies to the size of the input/output
683 register *t0* only. The address *t1* is always sized according to the guest,
684 and the width of the memory operation is controlled by *flags*.
686 | Both *t0* and *t1* may be split into little-endian ordered pairs of registers
687 if dealing with 64-bit quantities on a 32-bit host.
689 | The *memidx* selects the qemu tlb index to use (e.g. user or kernel access).
690 The flags are the MemOp bits, selecting the sign, width, and endianness
691 of the memory access.
693 | For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a
694 64-bit memory access specified in *flags*.
696 | For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of
697 the memory operation is known to be 8-bit. This allows the backend to
698 provide a different set of register constraints.
701 Host vector operations
702 ----------------------
704 All of the vector ops have two parameters, ``TCGOP_VECL`` & ``TCGOP_VECE``.
705 The former specifies the length of the vector in log2 64-bit units; the
706 latter specifies the length of the element (if applicable) in log2 8-bit units.
707 E.g. VECL = 1 -> 64 << 1 -> v128, and VECE = 2 -> 1 << 2 -> i32.
711 * - mov_vec *v0*, *v1*
715 - | Move, load and store.
717 * - dup_vec *v0*, *r1*
719 - | Duplicate the low N bits of *r1* into VECL/VECE copies across *v0*.
721 * - dupi_vec *v0*, *c*
723 - | Similarly, for a constant.
724 | Smaller values will be replicated to host register size by the expanders.
726 * - dup2_vec *v0*, *r1*, *r2*
728 - | Duplicate *r2*:*r1* into VECL/64 copies across *v0*. This opcode is
729 only present for 32-bit hosts.
731 * - add_vec *v0*, *v1*, *v2*
733 - | *v0* = *v1* + *v2*, in elements across the vector.
735 * - sub_vec *v0*, *v1*, *v2*
737 - | Similarly, *v0* = *v1* - *v2*.
739 * - mul_vec *v0*, *v1*, *v2*
741 - | Similarly, *v0* = *v1* * *v2*.
743 * - neg_vec *v0*, *v1*
745 - | Similarly, *v0* = -*v1*.
747 * - abs_vec *v0*, *v1*
749 - | Similarly, *v0* = *v1* < 0 ? -*v1* : *v1*, in elements across the vector.
751 * - smin_vec *v0*, *v1*, *v2*
753 umin_vec *v0*, *v1*, *v2*
755 - | Similarly, *v0* = MIN(*v1*, *v2*), for signed and unsigned element types.
757 * - smax_vec *v0*, *v1*, *v2*
759 umax_vec *v0*, *v1*, *v2*
761 - | Similarly, *v0* = MAX(*v1*, *v2*), for signed and unsigned element types.
763 * - ssadd_vec *v0*, *v1*, *v2*
765 sssub_vec *v0*, *v1*, *v2*
767 usadd_vec *v0*, *v1*, *v2*
769 ussub_vec *v0*, *v1*, *v2*
771 - | Signed and unsigned saturating addition and subtraction.
773 | If the true result is not representable within the element type, the
774 element is set to the minimum or maximum value for the type.
776 * - and_vec *v0*, *v1*, *v2*
778 or_vec *v0*, *v1*, *v2*
780 xor_vec *v0*, *v1*, *v2*
782 andc_vec *v0*, *v1*, *v2*
784 orc_vec *v0*, *v1*, *v2*
788 - | Similarly, logical operations with and without complement.
790 | Note that VECE is unused.
792 * - shli_vec *v0*, *v1*, *i2*
794 shls_vec *v0*, *v1*, *s2*
796 - | Shift all elements from v1 by a scalar *i2*/*s2*. I.e.
800 for (i = 0; i < VECL/VECE; ++i) {
804 * - shri_vec *v0*, *v1*, *i2*
806 sari_vec *v0*, *v1*, *i2*
808 rotli_vec *v0*, *v1*, *i2*
810 shrs_vec *v0*, *v1*, *s2*
812 sars_vec *v0*, *v1*, *s2*
814 - | Similarly for logical and arithmetic right shift, and left rotate.
816 * - shlv_vec *v0*, *v1*, *v2*
818 - | Shift elements from *v1* by elements from *v2*. I.e.
822 for (i = 0; i < VECL/VECE; ++i) {
823 v0[i] = v1[i] << v2[i];
826 * - shrv_vec *v0*, *v1*, *v2*
828 sarv_vec *v0*, *v1*, *v2*
830 rotlv_vec *v0*, *v1*, *v2*
832 rotrv_vec *v0*, *v1*, *v2*
834 - | Similarly for logical and arithmetic right shift, and rotates.
836 * - cmp_vec *v0*, *v1*, *v2*, *cond*
838 - | Compare vectors by element, storing -1 for true and 0 for false.
840 * - bitsel_vec *v0*, *v1*, *v2*, *v3*
842 - | Bitwise select, *v0* = (*v2* & *v1*) | (*v3* & ~\ *v1*), across the entire vector.
844 * - cmpsel_vec *v0*, *c1*, *c2*, *v3*, *v4*, *cond*
846 - | Select elements based on comparison results:
850 for (i = 0; i < n; ++i) {
851 v0[i] = (c1[i] cond c2[i]) ? v3[i] : v4[i].
854 **Note 1**: Some shortcuts are defined when the last operand is known to be
855 a constant (e.g. addi for add, movi for mov).
857 **Note 2**: When using TCG, the opcodes must never be generated directly
858 as some of them may not be available as "real" opcodes. Always use the
859 function tcg_gen_xxx(args).
865 ``tcg-target.h`` contains the target specific definitions. ``tcg-target.c.inc``
866 contains the target specific code; it is #included by ``tcg/tcg.c``, rather
867 than being a standalone C file.
872 The target word size (``TCG_TARGET_REG_BITS``) is expected to be 32 bit or
873 64 bit. It is expected that the pointer has the same size as the word.
875 On a 32 bit target, all 64 bit operations are converted to 32 bits. A
876 few specific operations must be implemented to allow it (see add2_i32,
877 sub2_i32, brcond2_i32).
879 On a 64 bit target, the values are transferred between 32 and 64-bit
880 registers using the following ops:
886 They ensure that the values are correctly truncated or extended when
887 moved from a 32-bit to a 64-bit register or vice-versa. Note that the
888 trunc_shr_i64_i32 is an optional op. It is not necessary to implement
889 it if all the following conditions are met:
891 - 64-bit registers can hold 32-bit values
892 - 32-bit values in a 64-bit register do not need to stay zero or
894 - all 32-bit TCG ops ignore the high part of 64-bit registers
896 Floating point operations are not supported in this version. A
897 previous incarnation of the code generator had full support of them,
898 but it is better to concentrate on integer operations first.
903 GCC like constraints are used to define the constraints of every
904 instruction. Memory constraints are not supported in this
905 version. Aliases are specified in the input operands as for GCC.
907 The same register may be used for both an input and an output, even when
908 they are not explicitly aliased. If an op expands to multiple target
909 instructions then care must be taken to avoid clobbering input values.
910 GCC style "early clobber" outputs are supported, with '``&``'.
912 A target can define specific register or constant constraints. If an
913 operation uses a constant input constraint which does not allow all
914 constants, it must also accept registers in order to have a fallback.
915 The constraint '``i``' is defined generically to accept any constant.
916 The constraint '``r``' is not defined generically, but is consistently
917 used by each backend to indicate all registers.
919 The movi_i32 and movi_i64 operations must accept any constants.
921 The mov_i32 and mov_i64 operations must accept any registers of the
924 The ld/st/sti instructions must accept signed 32 bit constant offsets.
925 This can be implemented by reserving a specific register in which to
926 compute the address if the offset is too big.
928 The ld/st instructions must accept any destination (ld) or source (st)
931 The sti instruction may fail if it cannot store the given constant.
933 Function call assumptions
934 -------------------------
936 - The only supported types for parameters and return value are: 32 and
937 64 bit integers and pointer.
938 - The stack grows downwards.
939 - The first N parameters are passed in registers.
940 - The next parameters are passed on the stack by storing them as words.
941 - Some registers are clobbered during the call.
942 - The function can return 0 or 1 value in registers. On a 32 bit
943 target, functions must be able to return 2 values in registers for
947 Recommended coding rules for best performance
948 =============================================
950 - Use globals to represent the parts of the QEMU CPU state which are
951 often modified, e.g. the integer registers and the condition
952 codes. TCG will be able to use host registers to store them.
954 - Don't hesitate to use helpers for complicated or seldom used guest
955 instructions. There is little performance advantage in using TCG to
956 implement guest instructions taking more than about twenty TCG
957 instructions. Note that this rule of thumb is more applicable to
958 helpers doing complex logic or arithmetic, where the C compiler has
959 scope to do a good job of optimisation; it is less relevant where
960 the instruction is mostly doing loads and stores, and in those cases
961 inline TCG may still be faster for longer sequences.
963 - Use the 'discard' instruction if you know that TCG won't be able to
964 prove that a given global is "dead" at a given program point. The
965 x86 guest uses it to improve the condition codes optimisation.